JP2010049464A - Electronic equipment, and method for downloading program for updating in the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten time required for downloading a program in electronic equipment having a plurality of hierarchical processors. <P>SOLUTION: The electronic equipment includes the plurality of hierarchical processors, storage devices formed correspondingly to respective processors to store programs and a means for inputting an updating program. Each processor performs processing for updating a program stored in the storage device corresponding to itself when acquiring the updating program and processing for transmitting the updating program to the lower processor. During the waiting period of either one processing, the processor starts the other processing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to downloading a program for an electronic device.

  Electronic devices such as information processing apparatuses and printing apparatuses generally include a plurality of processing apparatuses. Each processing device performs basic operations in accordance with a program stored in a nonvolatile storage device provided corresponding to the processing device.

  Such a program may be upgraded to add functions or correct defects after the electronic device is shipped. When the program is upgraded, the upgraded program is downloaded, and the program before the upgrade is rewritten.

Japanese Patent Application Laid-Open No. 2004-228561 provides a register for storing an upgraded program in addition to a non-volatile storage device provided in correspondence with the processing device for downloading the upgraded program. It is described that the upgraded program is read out and stored in a non-volatile storage device.
Japanese Patent Laid-Open No. 2005-11134

  By the way, a plurality of processing devices are often hierarchized, such as an upper processing device and a lower processing device. In the hierarchized configuration, in general, direct communication can be performed across the hierarchies. Can not. For this reason, acquisition of the upgraded program is also performed via the upper hierarchical device, and the technique described in Patent Document 1 cannot be applied as it is.

  When downloading an upgraded program in an electronic device having a plurality of hierarchical processing devices, each processing device has a process of writing the program in a nonvolatile storage device provided corresponding to the processing device, It is necessary to perform processing for transmitting the upgraded program to the processing device.

  If these processes are executed serially and a program is written in a non-volatile storage device and then the processes for sending the program to the lower-level processing devices are performed one by one, there is a problem that it takes a long processing time. In particular, this problem becomes significant when the hierarchy of processing devices is deep or when there are many lower-level processing devices.

  The present invention has been made in view of such a situation, and an object of the present invention is to reduce the time required for downloading a program in an electronic apparatus having a plurality of hierarchical processing devices.

  In order to solve the above-described problem, an electronic apparatus according to the first aspect of the present invention is provided with a plurality of processing devices hierarchized in a higher-order and lower-order relationship and corresponding processing devices. A storage device storing a program to be executed by the device; and program input means for inputting one or a plurality of update programs for updating the program. The highest-level processing device receives an update program. Then, a process of updating the program of the storage device corresponding to itself, a program update process including a period of waiting for a response from the storage device, and a process of transmitting the update program to a lower processing device And a program transmission process including a period of waiting for a response from the lower-level processing device, and the other processing devices receive an update program from the higher-level processing device. A process of updating the program of the storage device corresponding to itself, including a program update process including a period of waiting for a response from the storage device, and a process of transmitting the update program to a lower processing device. And performing a program transmission process including a period of waiting for a response from the lower level processing apparatus, and the uppermost level processing apparatus and the other processing apparatuses perform other processing during a response waiting period in any of the processes. It is characterized by starting.

  In the present invention, the processing device that performs the program update processing and the program transmission processing can start another processing before a certain processing is completed. Therefore, in an electronic apparatus having a plurality of hierarchical processing devices , The time required to download the program can be shortened.

  Here, the processing device is an integrated circuit that operates according to a rewritable program, and can be, for example, a CPU, a microcomputer, a DSP (Digital Signal Processor), an image processing device, an FPGA (Field Programmable Gate Array), or the like. . The rewritable program can be typically a firmware program. The program itself for the processing device to perform such processing can be stored in the storage device as a firmware program. The electronic device can be a printing device, for example.

  Specifically, the process of updating the program of the storage device includes a memory erase command transmission process to the storage device and a memory write command transmission process to the storage device, and a response from the storage device Can be a memory erase end report for the memory erase instruction and a memory write end report for the memory write instruction.

  In addition, the process of transmitting the update program to the lower processing apparatus includes a program transmission process and a result reception process for a completion report that is a response from the lower apparatus, and a response from the lower processing apparatus The waiting period may be a period after the program transmission process until a termination report is received from the lower-level device.

  Further, the display device further includes a display device, and when the update program is input, the uppermost processing device displays the version of the update program and the version of the program stored in each storage device on the display device. It is desirable to make it.

  At this time, if the version of the update program includes a version newer than the version of the program stored in each storage device, the top-level processing device updates all the programs. It is desirable to display on the display means a selection menu for updating only the new version of the program. As a result, the user can select whether to update all programs or only a new version of the program.

  The highest-level processing device and the other processing devices can determine the execution order of the program update processing and the program transmission processing according to a predetermined priority.

  At this time, it is desirable that the priorities are determined in descending order of evaluation values calculated for each process based on a predetermined evaluation criterion for evaluating the processing time. A process requiring a long processing time has a long response period. By increasing the priority of such processing and performing the processing quickly, a response waiting time for performing other processing can be secured. Thereby, the overall processing time can be further shortened.

  When the update program is compressed, the highest-level processing device can perform the decompression process of the update program in the order of priority when the update program is input. Thereby, processing start time can be advanced.

  Alternatively, when the update program receives an input or update program, the highest-level processing device and other processing devices calculate an evaluation value for each process based on a predetermined evaluation criterion for evaluating the processing time, and A priority may be set for each process in descending order of value, and the execution order of the program update process and the program transmission process may be determined according to the set priority.

  In order to solve the above-described problem, an update program download method in an electronic apparatus according to a second aspect of the present invention corresponds to a plurality of processing devices hierarchized in a high-order and low-order relationship, and each processing device. Update program download in an electronic device provided with a storage device provided and stored with a program executed by a corresponding processing device, and program input means for inputting one or more update programs for updating the program A method for updating a program of a storage device corresponding to itself when an update program is input to a highest-level processing device, including a period of waiting for a response from the storage device Processing for sending an update program to a lower processing device, waiting for a response from the lower processing device. When no process is performed, or when a process for waiting for a response in another process is started and an update program is received from a higher-level processing apparatus by another processing apparatus. A process for updating a program in a storage device corresponding to itself, a program update process including a response waiting period from the storage device, and a process for transmitting an update program to a lower processing device. The program transmission process including a period of waiting for a response from the lower-level processing device is started when no process is performed, or during a period of waiting for a response in another process.

  In the present invention, the processing device that performs the program update process and the program transmission process is hierarchized in order to start a certain process when no process is performed or during a response waiting period in another process. In an electronic device having a plurality of processing devices, it is possible to reduce the time required for downloading a program.

  ADVANTAGE OF THE INVENTION According to this invention, in the electronic device which has the several processing apparatus hierarchized, the time concerning download of a program can be shortened.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an electronic apparatus according to an embodiment of the present invention. As shown in the figure, the electronic device 10 includes a main board 100, a sub board 200, an operation panel unit 300, and an accessory device 400. The use of the electronic device 10 is not particularly limited, and can be, for example, an information processing device such as a computer, a printing device, a game device, a communication device, a home appliance, or the like.

  The main board 100 includes a CPU (Central Processing Unit) 110, a RAM (Random Access Memory) 120, an HDD (Hard Disk Drive) 130, and a USB I / F (Interface) 140. The RAM 120, the HDD 130, and the USB I / F (interface) 140 are bus-connected to the CPU 110, respectively. In addition, an operation panel unit 300 provided with a display device, operation buttons, and the like is connected to the CPU 110.

  An HDD 130 that is a rewritable nonvolatile storage device stores an F / W (firmware program) 131 that is a program executed by the CPU 110. The F / W 131 is expanded on the RAM 120 when the electronic device 10 is activated, and is executed by the CPU 110. The F / W 131 is a program incorporated in order to perform basic control of the electronic device 10, and is upgraded as necessary.

  The sub-board 200 includes a first microcomputer (microcomputer) 210, a RAM 220, a flash ROM 230, a second microcomputer 240, a flash ROM 250, and a third microcomputer 260. The first microcomputer 210 is connected to the CPU 110 of the main board 100 by a bus. The RAM 220, the flash ROM 230, the second microcomputer 240, and the third microcomputer 260 are each connected to the first microcomputer 210.

  A flash ROM 230 that is a rewritable nonvolatile storage device stores a first F / W 231 and a second F / W 232 that are programs executed by the first microcomputer 210. The first F / W 231 and the second F / W 232 are expanded on the RAM 220 when the electronic device 10 is activated, and are executed by the first microcomputer 210. However, it may be executed directly from the flash ROM 230 without being expanded on the RAM 220. The first F / W 231 and the second F / W 232 are upgraded as necessary.

  A flash ROM 250 is connected to the second microcomputer 240. The flash ROM 250 which is a rewritable nonvolatile storage device stores an F / W 251 which is a program executed by the second microcomputer 240. The third microcomputer 260 has a built-in flash ROM 261. The flash ROM 261 stores an F / W 262 that is a program executed by the third microcomputer 260. F / W251 and F / W262 are upgraded as necessary.

  Further, the accessory device 400 is connected to the USB I / F 140 of the main board 100. The accessory device 400 includes a microcomputer 410 and a flash ROM 420 that control the operation of the accessory device 400. The flash ROM 420 connected to the microcomputer 410 stores an F / W 421 that is a program executed by the microcomputer 410. The F / W 421 is upgraded as necessary.

  As described above, the application of the electronic device 10 is not limited in the present invention. For example, when the electronic device 10 is configured by a printing apparatus, the main board 100 is a controller board, and the sub board 200 is a print engine control board. The attachment device 400 can be configured as a scanner unit.

  F / W 131, first F / W 231, second F / W 232, F / W 251, F / W 262, F / W 421 version upgrade stored in each nonvolatile storage device recorded update F / W group 21 This can be done by connecting a USB memory to the connector of the USB I / F 140 and downloading the update F / W group 21. Specifically, the CPU 110 of the main board 100 reads the update F / W group 21 from the USB memory 20, stores it in the RAM 120, updates the F / W 131 in the HDD 130 connected to itself, and connects to it. F / W data necessary for updating the program in the update F / W group 21 is transmitted to the first microcomputer 210 of the sub-board 200 and the microcomputer 410 of the attached device 400.

  The first microcomputer 210 of the sub-board 200 that has received the F / W data temporarily stores it in the RAM 220, updates the first F / W 231 and the second W / F 232 in the flash ROM 230 connected to itself, and F / W data necessary for program update in the update F / W group 21 is transmitted to the second microcomputer 240 and the third microcomputer 260.

  The microcomputer 410 of the accessory device 400 that has received the F / W from the CPU 110 updates the F / W 421 in the flash ROM 420 connected to itself, and the second microcomputer 240 that has received the F / W from the first microcomputer 210 is: The third microcomputer 260 that has updated the F / W 251 of the flash ROM 250 connected thereto and received the F / W from the first microcomputer 210 updates the F / W 262 of the flash ROM 261 built therein. As a result, the F / W 131, the first F / W 231, the second F / W 232, the F / W 251, the F / W 262, and the F / W 421 stored in each nonvolatile storage device are upgraded.

  As described above, each of the processing devices of the CPU 110, the microcomputer 210, the second microcomputer 240, the third microcomputer 260, and the microcomputer 410 has a nonvolatile storage device connected to itself, and each storage device has its own storage device. One or more programs to be executed are stored. Further, each processing device forms a hierarchical structure of a tree structure. Specifically, the CPU 110 is a host device of the first microcomputer 210 of the sub-board 200 and the microcomputer 410 of the accessory device 400, and the first microcomputer 210 is a host device of the second microcomputer 240 and the third microcomputer 260. Communication between the processing devices is performed between the upper processing device and the lower processing device. Therefore, for example, when the CPU 110 collects information from the second microcomputer 240, the CPU 110 and the second microcomputer 240 do not directly communicate with each other, but the CPU 110 and the second microcomputer 240 via the first microcomputer 210. Communication is performed indirectly.

  The processing device is an integrated circuit that operates according to a rewritable program, such as a CPU, a microcomputer, a DSP (Digital Signal Processor), an image processing device, or an FPGA (Field Programmable Gate Array).

  FIG. 2 is a diagram that generalizes the relationship between the processing devices and the update program download process. As shown in the figure, each processing device has a hierarchical tree structure with the highest processing device as a vertex, and a nonvolatile storage device corresponds to each processing device. When the update program is downloaded, it is downloaded to the highest level processing device. Thereafter, each processing device performs processing for updating a program stored in a nonvolatile storage device connected to the processing device and processing for transmitting the program to a lower processing device.

  FIG. 3A is a timing chart for explaining a process of updating a program stored in a nonvolatile storage device connected to itself. In the program update process, since the program stored in the nonvolatile storage device is overwritten, it is necessary to erase the program before the update and write it. Therefore, the processing device designates an area for the nonvolatile storage device connected to itself and outputs a memory erase command. In accordance with this instruction, the non-volatile storage device executes memory erasure. When the memory erasure is completed, an end report is transmitted to the processing device. The processing apparatus is in a memory erasure waiting state after outputting the memory erasure command (time t1) until receiving an end report (time t2).

  When the processing device receives the memory erasure end report and confirms the end of memory erasure, it designates the update program and outputs a memory write command. In accordance with this instruction, the nonvolatile storage device writes the update program in the erased area. When the writing is completed, an end report is transmitted to the processing device. The processing device is in a memory write waiting state after outputting a memory write command (time t3) until receiving an end report (time t4).

  FIG. 3B is a timing chart for explaining a program transmission process for a lower-level processing device. In the program transmission process, the upper processing device transmits a program to the lower processing device. The lower-level processing device that has received the program performs program update processing for the non-volatile storage device connected to the program and processing for transmitting the program to the lower-level processing device. When these processes are completed, an end report is transmitted to the host processing apparatus. The upper processing apparatus is in a result waiting state after transmitting the program (time t4) until receiving an end report from the lower processing apparatus (time t5). Then, a result reception process is performed from the lower level processing apparatus. When other processing is performed at the time of completion reporting, the result reception processing is performed after the completion of the other processing.

  The processing device is in a busy state when executing a memory erase command, a memory write command, a program transmission command, and a result reception, and therefore cannot perform a plurality of processes simultaneously. However, other processes can be performed during the memory erasure wait state, the memory write wait state, and the result wait state.

  Next, program download processing in the highest-level processing device will be described with reference to the flowchart of FIG. The CPU 110 corresponds to the highest-level processing device in the example of FIG. This process starts when the USB memory 20 storing the update F / W group 21 is attached to the connector of the USB I / F 140 (S101). The CPU 110 can determine that the update F / W group 21 is stored in the USB memory 20 when predetermined data is recorded in a predetermined location of the attached USB memory 20. However, the recording medium is not limited to the USB memory 20 and may be another recording medium. Further, the update F / W group 21 may be received via a communication line. In this case, this process can be started by receiving a download instruction for the update program from the user.

  The USB memory 20 stores the index information of the stored update F / W group 21. The index information includes a list of stored update F / W groups 21 and versions of each F / W. The CPU 110 displays the new version indicated by the index information and the current F / W version recorded in each nonvolatile storage device on the display device of the operation panel unit 300 in a list format (S102). It is desirable that the CPU 110 collects the F / W version recorded in each nonvolatile storage device and stores it in the RAM 120 when the electronic device 10 is activated.

  If all the current F / W versions recorded in each nonvolatile storage device match the new version, the download process may be terminated. At this time, it is desirable to display on the display device of the operation panel unit 300 that the download is unnecessary.

  FIG. 5 is a diagram illustrating an example of a F / W version list display screen. In the example of this figure, the current version and the new version stored in the USB memory 20 are displayed in correspondence with each F / W. In this screen, the processing content is further displayed and the selection of the processing content is accepted from the user. The processing contents are “download only difference”, “overwrite download all”, and “cancel download”, and accept the selection from the user in association with the operation buttons of the operation panel unit 300, respectively. Here, in consideration of the program writing life (the number of times the nonvolatile storage device can be rewritten), it is desirable to select “download only the difference” that performs the minimum update as a default state. When the user selects “Cancel download”, the download process is stopped without performing the subsequent processes.

  When selection of processing content is received from the user (S103), update data is read from the USB memory 20 and stored in the RAM 120 (S104). At this time, if the selection of “overwrite all download” is accepted, all update data is read, and if the selection of “download only difference” is accepted, it is newer than the currently stored version. Update data corresponding to the version F / W is read. However, all the update data may be read and only the update data necessary for later processing may be used.

  If the update data is compressed, decompression processing is performed (S105). As will be described later, the order of decompression may be controlled according to the priority. Or you may make it decompress | decompress from the update data with a big size.

  Then, priority is set for the processing to be performed by the CPU 110 (S106). Here, the processing to be performed by the CPU 110 includes update processing of the F / W 131 stored in the HDD 130, program transmission processing to the first microcomputer 210 of the sub-board 200 that is a lower-level processing device, and an accessory device that is a lower-level processing device. This is a program transmission process to 400 microcomputers 410.

  In this embodiment, it is assumed that these priorities are determined in advance and are fixedly recorded in the current F / W 131. Therefore, the CPU 110 can set the priority of processing to be performed by referring to the F / W 131 expanded in the RAM 120. However, the priority may be recorded in the USB memory 20. In this case, the priority of processing to be performed can be set by referring to predetermined data recorded in the USB memory 20. Alternatively, as described later, the priority may be dynamically set based on the size of the read data.

  Then, a program update / transmission process is performed according to the priority (S107). The process determination method to be performed will be described later with reference to FIG. 8, and the specific contents of the program update / transmission process will be described later with reference to FIG.

  After that, it waits to receive the end report for all the processes (S108), and when it receives the end report for all the processes (S108: Yes), the display device of the operation panel unit 300 shows an example in FIG. A download end screen is displayed to notify the user that the download process has ended. In the example of this figure, the display “Firmware download complete. Please remove the USB memory.” Is displayed.

  Next, program download processing in a processing apparatus other than the top processing apparatus will be described with reference to the flowchart of FIG. In the example of FIG. 1, the processing devices other than the top processing device correspond to the first microcomputer 210, the second microcomputer 240, the third microcomputer 260, and the microcomputer 410 of the accessory device 400 in the sub-board 200. This process is started by receiving F / W update data from the host processor (S201).

  Then, priority is set for the processing to be performed by the processing device (S202). Here, the processing to be performed by the processing device is F / W update processing stored in a nonvolatile storage device connected to the processing device and program transmission processing to the lower processing device. However, there may be no subordinate processing device.

  In this embodiment, it is assumed that these priorities are determined in advance and fixedly recorded in the current F / W stored in the nonvolatile storage device connected to the apparatus. However, the priority may be recorded in the USB memory 20. In this case, the priority of processing to be performed can be set by acquiring the priority information recorded in the USB memory 20 from the host device. Alternatively, as described later, the priority may be set dynamically based on the received data size or the like.

  Then, a program update / transmission process is performed according to the priority (S203). The process determination method to be performed will be described later with reference to FIG. 8, and the specific contents of the program update / transmission process will be described later with reference to FIG. After that, it waits to receive completion reports for all processes (S204), and when it receives completion reports for all processes (S204: Yes), it sends an end report to the host processor (S205).

  Here, in the case of a program update process, a completion report is output when the last memory write process is completed. The reason for the last memory write process is that memory erasure and memory write may be performed in a plurality of times for one program update process, depending on the memory write unit. In the case of program transmission processing, a completion report is output when the result of the last program transmission processing is received. The reason for the last program transmission is that the program may be transmitted in multiple times for one program transmission process.

  Next, program update / transmission processing according to priority in each processing apparatus will be described. First, with reference to the flowchart of FIG. 8, a method for determining a process to be performed in the update / transmission process of the above-described process (S203) will be described. As described above, the priority is set for the processing to be performed in each processing device. Here, it is assumed that the priority is indicated by rank and there is no overlap.

  First, a process with the highest priority among the processes to be performed is set as a candidate for a process to be performed (S301). Then, it is determined whether the candidate process is either not required at that time or waiting for a response (S302). Here, the processing unnecessary is, for example, a case where the processing has already been completed. The response wait state is a memory erase wait state or a memory write wait state if the process is a program update process, and a result wait state if the process is a program transmission process. In the present embodiment, since it is not assumed that the processing apparatus performs a plurality of processes simultaneously, this flowchart is not performing a process, for example, when a process being executed is ended or a response is waited. Do it.

  As a result, if neither processing is required nor waiting for a response (S302: No), the candidate process is executed (S305). Therefore, processing with a high priority is preferentially executed. Specific execution contents will be described later with reference to FIG.

  On the other hand, if the process is not required or a response is waited (S302: Yes), it is checked whether there is a process with the next highest priority (S303), and the process with the next highest priority is performed. When it exists (S303: Yes), the process (S302) and subsequent steps are repeated as a candidate for a process to perform the process, which determines whether the process is unnecessary at that time or a response waiting state. . Therefore, a process with a low priority is performed when a process with a high priority is not required or is waiting for a response. Therefore, by setting a high priority for processing with a long response waiting time, a response waiting state is created early, and processing with a low priority is performed during the waiting state, thereby reducing the overall processing time. Can be shortened.

  If there is no process with the next highest priority (S303: No), the process with the highest priority among the processes to be performed is set as a process candidate (S301), and the above process is repeated. For this reason, for example, when a process with high priority is released from a response waiting state, it is preferentially executed.

  After executing the process that is the target candidate (S305), it is determined whether or not all the processes have been completed (S306). If the process remains (S306: No), the highest priority among the processes to be performed is determined. A high process is set as a process candidate (S301), and the above process is repeated. Then, when all the processes are finished (S306: Yes), this process is finished.

  Next, specific execution contents of the program update / transmission process will be described with reference to the flowchart of FIG. This process corresponds to the execution of the target process (S305) described above.

  First, it is determined whether the process to be executed is a program update process (S401). As a result, if it is a program update process (S401: Yes), it is checked whether or not the area where the program is overwritten has been erased (S402). This can be determined, for example, by recording a log in the update program download process.

  If not erased (S402: No), a memory erase command is output to the nonvolatile storage device (S403). The memory erase command may be divided into a plurality of times according to the memory write unit. When the memory erasure command is output, the processing apparatus enters a memory erasure waiting state (S404). During this waiting state, the processing device can perform other processes. The memory erasure waiting state is canceled when an erasure completion report is received from the nonvolatile storage device.

  On the other hand, if the data has been erased (S405: Yes), the data to be written is checked first in order to write the data (S405). In the data check, the validity or normality of the write data is confirmed using a hash value or the like. However, the data check may be performed when data is received.

  Then, a memory write command is output to the nonvolatile storage device (S406). The memory write command may be divided into a plurality of times according to the memory write unit. When the memory write command is output, the processor enters a memory write wait state (S407). During this waiting state, the processing device can perform other processes. Also, the memory write waiting state is canceled when a write end report is received from the nonvolatile storage device.

  When the process to be executed is not the program update process (S401: No), that is, in the case of the program transmission process, the update program data is transmitted to the lower level processing apparatus (S408). When the update program data is transmitted, the processing apparatus waits for a result (S409). During this waiting state, the processing device can perform other processes. The result waiting state is canceled when a result report is received from a lower-level processing device.

  The update program download process will be further described below using a specific example. Here, for the sake of simplicity, a case will be described as an example in which the update program download process is performed with the configuration shown in FIG. In the example of this figure, the first microcomputer, which is the host processor, updates the program 1 and program 2 stored in the flash ROM 230 connected to itself, and the second microcomputer 240, which is the lower processor. The second microcomputer program is transmitted, and the second microcomputer updates the program stored in the second microcomputer flash memory 250 connected to the second microcomputer program. Here, it is assumed that the update process of the program 1 is performed in two steps for convenience of writing units.

  The RAM 220 connected to the first microcomputer 210 has the highest priority 1 for the update process of the program 1, the priority of the update process of the program 2 is 2, and the program transmission process to the second microcomputer It is assumed that the priority is the lowest 3 is recorded.

  FIG. 11 is a timing chart showing the flow of download processing of the first microcomputer 210 and the second microcomputer 240 in this example. First, the update process of the program 1 with the highest priority is determined to be executed, and the first memory erase command is sent to the flash ROM 230 at time t1. After this instruction, the first microcomputer 210 is in a memory erasure waiting state, so that other processing can be performed. Therefore, the program 2 update process with the next highest priority is determined to be executed, and a memory erase command is sent to the flash ROM 230 at time t2. After this instruction, the first microcomputer 210 is in a memory erasure waiting state, so that other processing can be performed.

  Since the update process of the program 1 with the highest priority is in a response waiting state, it is determined as the process to be executed by the program transmission process to the second microcomputer with the lowest priority. Therefore, data transmission to the second microcomputer 240 is performed at time t3. The second microcomputer 240 that has received the data can perform processing independently of the first microcomputer 210, and the processing to be performed updates the program stored in the second microcomputer flash memory 250 connected to the second microcomputer 240. Just do it. For this reason, the second microcomputer 240 issues a memory erase command to the second microcomputer flash memory 250, and when the memory erase is completed, the second microcomputer 240 issues a memory write command. When the memory writing is completed, a completion report is transmitted to the first microcomputer.

  The first microcomputer 210 waits for a result when the data transmission to the second microcomputer 240 is completed. At this time, since the first memory erasure waiting state in the update process of the program 1 with the highest priority is released, the first memory write instruction in the update process of the program 1 is executed at the time t4. Sent against. Thereafter, the program 2 update process with the next highest priority is determined to be executed, and a memory write command is sent to the flash ROM 230 at time t5.

  After that, both processes wait for a response, and when the first memory write wait state in the update process of program 1 is canceled at time t6, the second memory erase instruction is sent to flash ROM 230. Sent. After that, all processes are in a response waiting state. Note that when the memory write wait state in the update process of the program 2 is released, the update process of the program 2 ends.

  Reception processing of the data transmission result sent from the second microcomputer 240 is performed at time t7. This process can be started by an interrupt signal from the second microcomputer 240, for example. As a result of the reception process, the program transmission process to the second microcomputer is completed.

  If the second memory erasure wait state for the update process of program 1 is canceled during the result reception process, the second memory write instruction for the update process of program 1 is flushed at time t8 when the result reception process ends. The first microcomputer 210 enters a memory write waiting state. When this memory write wait state is released, all the processes in the first microcomputer 210 are completed, and therefore the first microcomputer 210 transmits an end report to the host device.

  Next, a priority setting method will be described. As described above, in this embodiment, by setting a high priority for processing with a long response waiting time, a response waiting state is created early, and processing with a low priority is performed during the waiting state. The overall processing time is shortened. Here, the processes with a long response waiting time are a program update process with a long update time in the nonvolatile memory device and a program transmission process with a long process time in the lower-level processing device.

These response waiting times are, for example, the data size of the program to be updated or transmitted, the processing speed of the processing device, the communication speed between the processing devices, and the writing of one sector (write unit) of the flash memory (nonvolatile storage device). It can be evaluated using the erase response time. Here, the evaluation is performed using parameters as shown in Table 1.

That is, the data size evaluation value A is a value obtained by multiplying the data size by a predetermined coefficient. In this example, the coefficient is 50. The evaluation value B of the processing speed of the processing device is a value obtained by dividing a predetermined reference processing speed by the processing speed of the target processing device and multiplying by a predetermined coefficient. In this example, the predetermined reference processing speed is 500 MIPS, and the predetermined coefficient is 30. The evaluation value C of the communication speed between the processing apparatuses is a value obtained by converting the data size represented by KB into the number of bits, dividing by the communication speed (bps) between the processing apparatuses, and multiplying by a predetermined coefficient. In this example, the predetermined coefficient is 40. The evaluation value D of the write / erase response time of one sector of the flash memory is a value obtained by multiplying the write / erase response time of the flash memory by a predetermined coefficient. In this example, the predetermined coefficient is 10.

  The total value of the evaluation value A, the evaluation value B, the evaluation value C, and the evaluation value D is set as the priority value X, and the priority is determined in descending order of the priority value X.

  The priority setting will be further described by taking an electronic apparatus having a configuration as shown in FIG. 12 as an example. In the example of this figure, the first microcomputer 210 having a processing speed of 200 MIPS, which is the host processor, updates the 8192 KB program 1 and the 3072 KB program 2 stored in the flash ROM 230 connected to itself. A process for transmitting a 512 KB second microcomputer program to the second microcomputer 240 with a processing speed of 180 MIPS, which is a processing apparatus, and a 64 KB third microcomputer program to a third microcomputer 260 with a processing speed of 30 MIPS, which is a lower processing apparatus. The priority setting in the first microcomputer 210 when performing processing will be described.

Here, it is assumed that the communication processing speed between the first microcomputer 210 and the second microcomputer 240 is 38400 pbs, and the communication processing speed between the first microcomputer 210 and the third microcomputer 260 is 115200 bps. Further, the write / erase response time of the flash ROM 230 of the first microcomputer 210 is 600 ms, the write / erase response time of the flash ROM 250 of the second microcomputer 240 is 1000 ms, and the write of the flash ROM 261 of the third microcomputer 260 is performed. Assuming that the erasure response time is 800 ms, the specification table shown in Table 2 is created.

When the above-described evaluation value calculation is performed for each value in the specification table, the evaluation results shown in Table 3 can be obtained.

As a result, the program 1 update process with the highest priority value X is determined as the process with the highest priority. Hereinafter, the program 2 update process, the program transmission process to the second microcomputer, and the program transmission process to the third microcomputer will be described. Priorities are determined in order.

  The developer of the electronic device 10 determines the priority in advance based on the configuration of the electronic device 10 and stores the priority in a nonvolatile storage device corresponding to each processing device. As a result, each processing apparatus can perform processing according to the priority when the update program is downloaded. In addition, priority information may be recorded in the USB memory 20 in consideration of a case where the download size or the like is changed in the update program. In this case, the update program is downloaded in each processing device according to the priority recorded in the USB memory 20. Furthermore, the priority information itself stored in the nonvolatile storage device can be updated by an update program.

  When the uppermost processor reads the update data from the USB memory 20, it performs data decompression as necessary (S105), but this decompression order may also be performed according to the above priority. As a result, the start of the program update / transmission process can be accelerated. In this case, the priority setting process (S106) is performed prior to the data decompression process (S105).

  In the above example, the processing priority is determined in advance. However, the priority may be dynamically determined in each processing apparatus. In this case, prior to the start of the program update / transmission process, the priority is dynamically determined by performing the above-described evaluation value calculation in each processing device. Specifically, it can be performed according to the flowchart of FIG.

  That is, for the process to be evaluated, the evaluation value A is calculated with reference to the data size of the program related to the process (S501). Then, the evaluation value B is calculated with reference to the processing device processing speed related to the processing to be evaluated (S502). Note that the processing speed of the processing device is spec information and is known, and is recorded in advance in a nonvolatile storage device. When the process to be evaluated is program transmission (S503: Yes), the evaluation value C is further calculated with reference to the communication speed between the processing apparatuses that perform transmission and reception. Note that the communication speed between the processing devices is specification information and is known, and is recorded in advance in a nonvolatile storage device. Then, the evaluation value D is calculated with reference to the write / erase response time of one sector of the nonvolatile memory device related to the process to be evaluated (S505). Note that the write / erase response time for one sector of the nonvolatile storage device is the specification information and is known, and is recorded in advance in the nonvolatile storage device.

  When the evaluation value A, the evaluation value B, the evaluation value C, and the evaluation value D are calculated, by adding these evaluation values, the priority value X of the process that is the evaluation target can be calculated (S506). ). When the above priority order value X is repeated for all processes (S507) and calculation of the priority order value X is completed for all processes (S507: Yes), the priority is determined based on the calculated priority order value X. (S508). That is, priorities are determined in descending order of priority value X.

  As described above, according to the present embodiment, the time required for downloading a program can be shortened in an electronic apparatus having a plurality of hierarchical processing devices.

  In the above embodiment, the storage device for storing the program to be updated is a nonvolatile storage device such as an HDD (Hard Disk Drive) or Flash ROM. However, the present invention is not limited to a nonvolatile storage device, and can also be applied to a volatile storage device. In this case, the program stored in the non-volatile storage device is stored in the volatile storage device when the electronic device is started up, and the program stored in the volatile storage device is downloaded as described above. Try to update. Then, a program updated when the power of the electronic device is stopped may be stored in the nonvolatile storage device. Even in the case of using a volatile storage device, it is possible to reduce the time required to download a program in an electronic apparatus having a plurality of hierarchical processing devices.

It is a block diagram which shows the structure of the electronic device which is one Embodiment of this invention. It is the figure which generalized the download process of the relationship of a processing apparatus and the program for an update. It is a timing chart explaining a program update process and a program transmission process It is a flowchart explaining the program download process in a highest-order processing apparatus. It is a figure which shows an example of the list display screen of the version of F / W. It is a figure which shows an example of a download completion screen. It is a flowchart explaining the program download process in processing apparatuses other than the highest-order processing apparatus. It is a flowchart explaining the determination method of the process performed in a program update / transmission process. It is a flowchart explaining the specific execution content of a program update / transmission process. It is a block diagram which shows the structure of the electronic device for demonstrating the download process of the program for an update. 4 is a timing chart showing the flow of download processing of a first microcomputer 210 and a second microcomputer 240. It is a block diagram which shows the structure of the electronic device for demonstrating the setting of a priority. It is a flowchart explaining the process sequence which determines a priority.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electronic device, 20 ... USB memory, 21 ... Update F / W group, 100 ... Main board, 110 ... CPU, 120 ... RAM, 130 ... HDD, 140 ... USB I / F, 200 ... Sub board, 210 ... 1st microcomputer, 220 ... RAM, 230 ... Flash ROM, 240 ... 2nd microcomputer, 250 ... Flash ROM, 260 ... 3rd microcomputer, 261 ... Flash ROM, 300 ... Operation panel unit, 400 ... Attached device, 410 ... Microcomputer, 420 ... Flash ROM

Claims (10)

A plurality of processing devices that are hierarchized into upper and lower relationships;
A storage device provided corresponding to each processing device and storing a program executed by the corresponding processing device;
Program input means for inputting one or more update programs for updating the program,
When the update program is input, the highest-level processing device updates the program of the storage device corresponding to itself, and includes a program update processing including a response waiting period from the storage device, A process of transmitting an update program to the processing device, performing a program transmission process including a period of waiting for a response from the lower processing device,
When the other processing device receives the update program from the host processing device, the processing device updates the program of the storage device corresponding to itself, and includes a program update processing including a response waiting period from the storage device, A process for transmitting an update program to a lower-level processing device, and performing a program transmission process including a period of waiting for a response from the lower-level processing device,
The uppermost processing device and the other processing devices start other processing during a response waiting period in any processing. The electronic device according to claim 1,
The process of updating the program of the storage device includes a memory erase command transmission process to the storage device and a memory write command transmission process to the storage device,
The electronic device characterized in that the response from the storage device is a memory erase end report for the memory erase command and a memory write end report for the memory write command. The electronic device according to claim 1 or 2,
The process of transmitting the update program to the lower level processing apparatus includes a program transmission process and a result reception process for an end report that is a response from the lower level apparatus,
The electronic apparatus according to claim 1, wherein a period of waiting for a response from the lower order processing apparatus is a period from the end of the program transmission process until an end report is received from the lower order apparatus. The electronic device according to any one of claims 1 to 3,
A display device,
The top-level processing device, when an update program is input, displays the version of the update program and the version of the program stored in each storage device on the display device . The electronic device according to claim 4,
If the version of the update program includes a version newer than the version of the program stored in each storage device,
An electronic apparatus, characterized in that a menu for selecting whether to update all programs or only a new version program is displayed on the display means. The electronic device according to claim 1,
The electronic device, wherein the highest-level processing device and the other processing devices determine an execution order of the program update processing and the program transmission processing according to a predetermined priority. The electronic device according to claim 6,
The electronic device is characterized in that the priorities are determined in descending order of evaluation values calculated for each process based on a predetermined evaluation criterion for evaluating a processing time. The electronic device according to claim 7,
The update program is compressed,
The electronic device according to claim 1, wherein when the update program is input, the highest-level processing device performs decompression processing of the update program in the order of priority. The electronic device according to claim 1,
When the update program is input or the update program is received, the highest-level processing device and the other processing devices calculate an evaluation value for each process based on a predetermined evaluation criterion for evaluating the processing time. An electronic apparatus, wherein priority is set for each process in descending order, and the execution order of the program update process and the program transmission process is determined according to the set priority. A plurality of processing devices hierarchized in a higher and lower relationship, a storage device provided corresponding to each processing device and storing a program executed by the corresponding processing device, and for updating the program An update program download method in an electronic device comprising program input means for inputting one or more update programs,
When the update program is input to the highest-level processing device, the highest-level processing device is a process of updating the program of the storage device corresponding to itself, and includes a period of waiting for a response from the storage device When the program update process and the process for transmitting the update program to the lower-level processing device and including the period for waiting for a response from the lower-level processing device are not performed. Or start during a response waiting period in other processing,
When the update program is received by the other processing device from the host processing device, the other processing device is a process of updating the program of the storage device corresponding to itself, and waits for a response from the storage device. A program update process including a period and a program transmission process including a period of waiting for a response from the lower-level processing apparatus, which is a process of transmitting an update program to the lower-level processing apparatus, are performed. An update program download method for an electronic device, which starts in a period of waiting for a response in other processing.