JP2010045237A - Vertical semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing parasitic capacitance, without having large influence on resistance at breakdown voltage and in an On-state. <P>SOLUTION: The vertical semiconductor device is provided so that a gate electrode (12) is adjacently formed on a surface opposite to a first semiconductor layer (11) where a drain electrode (14) is formed, and a source electrode (13) is formed so as to cover a part between electrodes of the gate electrode (12) and the gate electrode (12), and includes a second semiconductor layer (17) formed between a first semiconductor area (18) and a first semiconductor layer (11) formed on the source electrode (13) side and having the impurity concentration lower than that of the first semiconductor area (18). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a vertical semiconductor device such as a vertical DMOSFET (Double Diffused Metal Oxide Semiconductor Field Effect Transistor) used as a switching element such as a semiconductor relay and a method for manufacturing the same.

Common power MOSFETs and semiconductor relays (SSR: Solid State Relay) are constituted by vertical semiconductor devices called vertical double diffusion MOSFETs (DMOSFETs). FIG. 9 is a cross-sectional view showing a configuration of a conventional vertical DMOSFET. As shown in FIG. 9, a conventional vertical DMOSFET100 is, n is an n-type silicon substrate ^- the gate electrode 102 and source electrode 103 is provided on the surface side of the type drift layer 101, n ^- -type drift layer A drain electrode 104 is provided on the back side of 101.

  In FIG. 9, the layer with the symbol “n” means a layer having electrons as a majority carrier, and the layer with a symbol “p” means a layer having holes as a majority carrier. The symbol “+” accompanying the symbol “n” or the symbol “p” means that the layer has a relatively high impurity concentration, and the symbol “−” means that the layer has a relatively low impurity concentration. .

The gate electrodes 102 are made of, for example, polysilicon, and a plurality of gate electrodes 102 are arranged along the n ⁻ type drift layer 101 with a predetermined interval. Note that an oxide film 105 is formed around the gate electrode 102 so as to surround the gate electrode 102. The source electrode 103 is formed so as to cover the gate electrode 102 via the oxide film 105 and to fill a gap between the gate electrodes 102. The drain electrode 104 is provided on the back surface side of the n ⁻ type drift layer 101 via the n ⁺ type contact layer 106.

In addition, a p-type base region 107 is formed on the surface side of the n ⁻ -type drift layer 101 by impurity diffusion using a gap between the gate electrodes 102, and the gate electrode 102 of the gate electrode 102 is formed in the p-type base region 107. The p ⁺ -type region 108 and the n ⁺ -type region 109 are formed by impurity diffusion using the gap again. A depletion layer 110 is formed between the p-type base region 107 and the n ⁻ -type drift layer 101. In addition, an n-type layer 111 below the gate electrode 102 and between the p-type base region 107 prevents an increase in on-state resistance due to a parasitic JFET (Junction Field-Effect Transistor). Is formed.

In the above structure, when no voltage is applied to the gate electrode 102, no current flows between the source electrode 103 and the drain electrode 104 unless a positive voltage is applied to the source electrode 103. On the other hand, when a voltage is applied to the gate electrode 102, an n channel is formed in the p-type base region 107. Therefore, when a voltage is applied between the source electrode 103 and the drain electrode 104, for example, an n channel, an n type layer 111, and an n ⁻ type drift formed from the source electrode 103 to the n ⁺ type region 109 and the p type base region 107. A current flows through a path reaching the layer 101, the n ⁺ -type contact layer 106, and the drain electrode 104.

For details of a conventional vertical semiconductor device other than the vertical DMOSFET 100 shown in FIG. 9, see, for example, Patent Document 1 below.
Japanese Patent Laid-Open No. 7-212296

By the way, one of the important characteristics of a vertical semiconductor device that performs switching is a drain-source capacitance Cds and a drain-gate capacitance Cdg. Both of them are preferably small in order to realize high-speed switching. . In the vertical DMOSFET 100 shown in FIG. 9, the drain-source capacitance Cds includes the junction capacitance C101 between the p-type base region 107 and the n ⁻ -type drift layer 101, the p-type base region 107, and the n-type layer 111. It is almost determined by the sum of the junction capacitance C102. The drain-gate capacitance Cdg is substantially determined by the capacitance C110 through the oxide film 105 between the gate electrode 102 and the n-type layer 111.

Here, if the concentration of the n ⁻ -type drift layer 101 is adjusted, the parasitic capacitance (drain-source capacitance Cds) can be reduced. However, resistance at the time of the breakdown voltage and on the vertical DMOSFET100 shown in FIG. 9, n ^- determined depending on a concentration and thickness of the type drift layer 101, in order to reduce the parasitic capacitance n ^- adjusting the concentration of the type drift layer 101 If this is the case, the withstand voltage of the vertical DMOSFET 100, the on-resistance, and the like may change, leading to a decrease in performance of the vertical DMOSFET 100.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a vertical semiconductor device capable of reducing parasitic capacitance without greatly affecting the withstand voltage and the on-state resistance. To do.

In order to solve the above-mentioned problem, in the present invention, as a first solving means relating to a vertical semiconductor device, a gate electrode is formed on the opposite surface of the first semiconductor layer (11) where the drain electrode (14) is formed. A vertical semiconductor device in which (12) is formed adjacent to each other and a source electrode (13) is formed so as to cover between the gate electrodes (12) and the gate electrode (12). ,
A second semiconductor layer formed between the first semiconductor region (18) formed on the source electrode (13) side and the first semiconductor layer (11) and having an impurity concentration lower than that of the first semiconductor region (18). (17).

 Further, as a second solving means relating to the vertical semiconductor device, in the first solving means, in the second semiconductor layer (17), the impurity concentration in a region other than the region immediately below the gate electrode (12) is The concentration is set lower than that of the first semiconductor region (18), and the conductivity is inverted in the region immediately below the gate electrode (12) when the impurity is lower in concentration than the second semiconductor layer (17) and below the threshold voltage. A third semiconductor layer (30) set to a concentration to be formed is formed.

 Further, as a third solving means relating to the vertical semiconductor device, in the first or second solving means, the first conductive type first semiconductor layer (11) and the first semiconductor layer (11) The second conductivity type second semiconductor layer (17) formed on one surface, and a plurality of second conductivity type first semiconductor layers formed on the surface of the second semiconductor layer (17) at a predetermined interval. A semiconductor region (18) and a second semiconductor region (20) of the first conductivity type formed on the surface of the first semiconductor region (18) and having a higher concentration than the first semiconductor layer (11) are adjacent to each other. A plurality of layers are formed so as to straddle the first semiconductor region (18) and the second semiconductor region (20), and an insulating region (15) made of a predetermined insulating material and embedded in the insulating region (15), respectively. The gate electrode (12) and the surface of the first semiconductor region (18) And the source electrode (13) formed to cover the insulating region (15), and the drain electrode (14) formed on the other surface of the first semiconductor layer (11). Features.

 On the other hand, according to the present invention, as a first means for solving the vertical semiconductor device manufacturing method, the vertical semiconductor device manufacturing method includes a first conductivity type first semiconductor having one surface connected to the drain. Forming a layer (11); forming a second conductive type second semiconductor layer (17) having one surface covering the other surface of the first semiconductor layer (11); and the first Forming a second conductivity type first semiconductor region (18) having an impurity concentration higher than that of the second semiconductor layer (17) on the other surface of the semiconductor layer (11); and the first semiconductor region (18). Connecting to the source.

 Further, as a second means for solving the vertical semiconductor device manufacturing method, the vertical semiconductor device manufacturing method includes a first conductivity type first semiconductor layer (11) having one surface connected to the drain. Forming an oxide film on the other surface of the first semiconductor layer (11), and no impurity is implanted into a region where the third semiconductor layer (30) is to be formed on the surface of the oxide film. Forming a resist, implanting an impurity for forming the second conductive type second semiconductor layer 17A from the surface side of the resist after the resist is formed, and after implanting the impurity In the first semiconductor layer (11), the impurity is diffused from both sides of the resist, and the impurity is connected in a region immediately below the resist, thereby connecting the second semiconductor layer (17A) and the second semiconductor. Forming a second conductive type third semiconductor layer (30) having a concentration lower than that of the layer (17A) and less than a threshold voltage and inverting to the first conductive type; and the first semiconductor layer (11 ) Forming a second conductivity type first semiconductor region (18) having an impurity concentration higher than that of the second semiconductor layer (17) on the other surface, and connecting the first semiconductor region (18) to the source And a step of performing.

In the present invention, the first semiconductor layer is formed between the first semiconductor region and the first semiconductor layer formed on the source electrode side and has a second semiconductor layer having an impurity concentration lower than that of the first semiconductor region. The depletion layer extending from the PN junction that is the boundary between the first semiconductor layer and the second semiconductor layer extends into the first semiconductor layer and the second semiconductor layer. As a result, the first semiconductor region and the first semiconductor layer are separated by a wide depletion layer, and the drain-source capacitance generated between the first semiconductor region and the first semiconductor layer is greatly reduced. The In addition, the gate electrode and the first semiconductor layer are also separated by a wide depletion layer, and the gate-drain capacitance generated between the gate electrode and the first semiconductor layer is greatly reduced.
Therefore, according to the present invention, without adjusting the concentration of the first semiconductor layer, that is, without greatly affecting the breakdown voltage and the on-state resistance of the vertical semiconductor device, the parasitic capacitance (drain-source capacitance and (Capacitance between gate and drain) can be significantly reduced.

 Hereinafter, an embodiment of a vertical semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. In the following, a vertical DMOSFET will be described as an example of a vertical semiconductor device according to the present invention.

[First Embodiment]
FIG. 1 is a cross-sectional view illustrating a schematic configuration of a vertical semiconductor device 10 according to the first embodiment. As shown in FIG. 1, the vertical semiconductor device 10 according to this embodiment includes a gate electrode on the surface side of a substrate (for example, n-type silicon) on which an n ⁻ -type drift layer 11 (first semiconductor layer) and the like are formed. 12 and a source electrode 13 are provided, and a drain electrode 14 is provided on the back side of the n ⁻ -type drift layer 11.

  In FIG. 1, the layer with the symbol “n” means a layer (first conductivity type layer) having electrons as majority carriers, and the layer with the symbol “p” has holes with majority carriers. (Layer of the second conductivity type). The symbol “+” accompanying the symbol “n” or the symbol “p” means that the layer has a relatively high impurity concentration, and the symbol “−” means that the layer has a relatively low impurity concentration. .

The gate electrodes 12 are made of, for example, polysilicon, and a plurality of gate electrodes 12 are arranged at predetermined intervals along the substrate surface on which the n ⁻ type drift layer 11 and the like are formed. An oxide film 15 (insulating region) such as SiO ₂ is formed around the gate electrode 12 so as to surround the gate electrode 12. The source electrode 13 is formed so as to cover the gate electrode 12 via the oxide film 15 and fill a gap between the gate electrodes 12. The drain electrode 14 is provided on the back side of the substrate on which the n ⁻ type drift layer 11 and the like are formed via the n ⁺ type contact layer 16.

On the n ⁻ -type drift layer 11, an extended p-type base layer 17 (the second p-type base layer 17) having a lower impurity concentration than a p-type base region 18 described later and a concentration that is inverted to the n-type below the threshold voltage. Semiconductor layer) is formed. Further, a p-type base region 18 (first semiconductor region) having a higher concentration than that of the extended p-type base layer 17 is formed on the surface side in the extended p-type base layer 17 due to diffusion of impurities using a gap between the gate electrodes 12. A plurality of p ⁺ type regions 19 and n ⁺ type regions 20 (second regions) are formed on the surface side in the p type base region 18 by diffusion of impurities using the gap of the gate electrode 12 again. Semiconductor regions) are respectively formed. Here, the p-type base region 18 is preferably formed shallow so as not to block the extension of the depletion layer 22 from the PN junction 21 that is the boundary between the n ⁻ -type drift layer 11 and the extended p-type base layer 17. It is.

As described above, in the vertical semiconductor device 10 of the present embodiment, without providing the n-type layer 111 which is provided in the conventional vertical DMOSFET100 shown in FIG. 9, n ^- extended over the entire surface of the type drift layer 11 p A configuration is adopted in which a mold base layer 17 is formed and each p-type base region 18 is formed in the extended p-type base layer 17. In the conventional vertical DMOSFET 100, the current path is secured by the n-type layer 111 provided under the gate electrode 102. However, in the vertical semiconductor device 10 of the present embodiment, the current path is provided by the extended p-type base layer 17. Secured.

Specifically, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 12 of the vertical semiconductor device 10 according to the present embodiment, as shown in FIG. The p-type region is inverted to the n-type to form the channel 23. At the same time, the extended p-type base layer 17 under the gate electrode 12 is also inverted to become n-type. However, since the impurity concentration of the layer is sufficiently low, the inversion region 24 is formed not only on the surface layer but also inside. As a result, electrons are filled in the inversion region 24 in the extended p-type base layer 17, and a carrier path that connects the channel 23 and the n ⁻ -type drift layer 11 is generated. In this state, if a voltage is applied between the source and the drain, a current flows.

On the other hand, when the parasitic capacitance when the off voltage is applied to the gate electrode 12 is verified, since the impurity concentration of the extended p-type base layer 17 is sufficiently low, it is a boundary between the n ⁻ -type drift layer 11 and the extended p-type base layer 17. The depletion layer 22 extending from the PN junction 21 extends into the n ⁻ -type drift layer 11 and the extended p-type base layer 17. As a result, the p-type base region 18 and the n ⁻ type drift layer 11 are separated by the wide depletion layer 22, and the drain / source generated between the p type base region 18 and the n ⁻ type drift layer 11. The inter-space capacitance Cds (symbol C11 in FIG. 1) is greatly reduced. Further, the gate electrode 12 and the n ⁻ type drift layer 11 are also separated by a wide depletion layer 22, and the gate-drain capacitance Cdg generated between the gate electrode 12 and the n ⁻ type drift layer 11 (FIG. In FIG. 1, the code C12) is also greatly reduced.

As described above, according to the vertical semiconductor device 10 in the present embodiment, by providing the extended p-type base layer 17 without providing the n-type layer 111 provided in the conventional vertical DMOSFET 100, the n ⁻ -type is provided. Parasitic capacitances (drain-source capacitance Cds and gate-drain capacitance Cdg) without adjusting the concentration of the drift layer 11, that is, without significantly affecting the breakdown voltage and on-resistance of the vertical semiconductor device 10. Can be greatly reduced.

 In addition, by adopting the configuration of the vertical semiconductor device 10 in the present embodiment as described above, the length Lg of the gate electrode 12 is increased by 10 times or more compared to the conventional vertical DMOSFET 100 shown in FIG. Therefore, the parasitic capacitance can be further reduced. However, when the length Lg of the gate electrode 12 is increased by adopting the configuration of the vertical semiconductor device 10 in the present embodiment, the number of cells per device unit area decreases because the unit of repeating FET called a cell increases. In addition, the channel resistance increases. Therefore, the configuration adopted in the vertical semiconductor device 10 of this embodiment is suitable for a high breakdown voltage device in which the channel resistance does not greatly affect the on-resistance as compared with the bulk resistance.

Next, a method for manufacturing the vertical semiconductor device 10 according to the first embodiment will be described with reference to FIGS.
As shown in FIG. 3A, first, an oxide film 15 is formed over the entire surface of one side of the n ⁻ type drift layer 11 (for example, an n-type silicon substrate) using, for example, a thermal oxidation method or a CVD method. Form. Subsequently, as shown in FIG. 3B, after the oxide film 15 is formed, an impurity for forming the extended p-type base layer 17 is implanted from the surface side of the oxide film 15 using an ion implantation method, and annealing is performed. The extended p-type base layer 17 is formed by diffusing impurities by performing a heat treatment such as the above.

 Thus, after the extended p-type base layer 17 is formed, the electrode layer 12 such as polysilicon is formed over the entire surface of the oxide film 15. Then, portions of the oxide film 15 and the electrode layer 12 where the p-type base region 18 is to be formed are removed to form an opening H. As a result, as shown in FIG. 4A, a part of the oxide film 15 and the gate electrode 12 are formed on the extended p-type base layer 17. Here, an example in which both the oxide film 15 and the electrode layer 12 are removed to form the opening H will be described. However, only the electrode layer 12 is removed and the oxide film 15 is buffered during ion implantation. It may be used as

   Subsequently, as shown in FIG. 4B, using the gate electrode 12 as a mask, impurities are implanted and diffused from the opening H formed in the gate electrode 12 into the extended p-type base layer 17 to form a p-type base. Region 18 is formed. At this time, the p-type base region 18 is formed so that the concentration of the p-type base region 18 is appropriate for forming a channel. Here, it is desirable to form the p-type base region 18 shallow so as not to limit the width of the depletion layer 22 formed in the extended p-type base layer 17.

Then, as shown in FIG. 4C, after the p-type base region 18 is formed, impurities are diffused into the p-type base region 18 from the opening H formed in the gate electrode 12 again using the gate electrode 12 as a mask. P ⁺ -type region 19 and n ⁺ -type region 20 are formed. When the above steps are completed, the step of forming the oxide film 15 around the gate electrode 12, the step of forming the source electrode 13, the step of forming the drain electrode on the back side of the n ⁻ drift layer 11, etc. in order. As a result, the vertical semiconductor device 10 shown in FIG. 1 is manufactured.

[Second Embodiment]
FIG. 5 is a cross-sectional view showing a schematic configuration of a vertical semiconductor device 10A in the second embodiment. In FIG. 5, the same components as those in FIG. As shown in FIG. 5, the vertical semiconductor device 10 </ b> A in the second embodiment is more on the n ⁻ type drift layer 11 than the p-type base region 18 compared to the vertical semiconductor device 10 in the first embodiment. An extended p-type base layer 17A having a low impurity concentration is formed. In the extended p-type base layer 17A, a region immediately below the gate electrode 12, that is, a region sandwiched between two adjacent p-type base regions 18 is formed. Is formed with a p ⁻⁻ type low concentration layer 30 (third semiconductor layer) having an impurity concentration lower than that of the extended p type base layer 17A and having a concentration that is inverted to the n type below the threshold voltage. It is different.

When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 12 of the vertical semiconductor device 10A having such a configuration, as shown in FIG. 6, the p-type base is the same as the vertical semiconductor device 10 of the first embodiment. The p-type region under the gate electrode 12 in the region 18 and the extended p-type base layer 17A is inverted to the n-type to form the channel 23A. At the same time, the p ⁻⁻ type low concentration layer 30 under the gate electrode 12 is also inverted to become n type, but since the impurity concentration of the layer is sufficiently low, the inversion region is formed not only in the surface layer but also in the interior. . As a result, electrons fill the p ⁻⁻ type low concentration layer 30, and a carrier path that connects the channel 23 </ b> A and the n ⁻ type drift layer 11 is generated. In this state, if a voltage is applied between the source and the drain, a current flows.

On the other hand, when verifying the parasitic capacitance during turn-off voltage applied to the gate electrode 12, extended p-type base layer 17A and p ^- since the impurity concentration of the type low concentration layer 30 is sufficiently low, n ^- -type drift layer 11 and the extended p The depletion layer 22A extending from the PN junction 21A, which is the boundary between the p-type base layer 17A and the p ⁻⁻ type low concentration layer 30, is the n ⁻ type drift layer 11, the extended p type base layer 17A and the p ⁻⁻ type low concentration. It will spread within the layer 30. As a result, as in the first embodiment, the p-type base region 18 and the n ⁻ -type drift layer 11 are separated by a wide depletion layer 22A, and the p-type base region 18 and the n ⁻ -type drift layer 11 are separated. The drain-source capacitance Cds (reference C11A) generated between the two is greatly reduced. Further, the gate electrode 12 and the n ⁻ type drift layer 11 are also separated by a wide depletion layer 22A, and the gate-drain capacitance Cdg (reference numeral) generated between the gate electrode 12 and the n ⁻ type drift layer 11 C12A) is also greatly reduced.

As described above, according to the vertical semiconductor device 10A in the second embodiment, the extended p-type base layer 17A and the p ⁻⁻ type low concentration can be obtained without providing the n-type layer 111 provided in the conventional vertical DMOSFET 100. By providing the layer 30, the parasitic capacitance (between the drain and the source is not adjusted without adjusting the concentration of the n ⁻ -type drift layer 11, that is, without greatly affecting the breakdown voltage and the on-state resistance of the vertical semiconductor device 10 < ^/ b> A. Capacitance Cds and gate-drain capacitance Cdg) can be greatly reduced.

 Similar to the first embodiment, by adopting the configuration of the vertical semiconductor device 10A in the second embodiment, the length Lg of the gate electrode 12 can be made longer than the conventional one, so that the parasitic capacitance can be further reduced. Can be achieved. Further, the configuration employed in the vertical semiconductor device 10A of the second embodiment is suitable for a high breakdown voltage device in which the channel resistance does not greatly affect the on-resistance as compared with the bulk resistance.

Next, a method for manufacturing the vertical semiconductor device 10A in the second embodiment described above will be described with reference to FIGS.
As shown in FIG. 7A, first, the oxide film 15 is formed over the entire surface of one side of the n ⁻ type drift layer 11 (for example, an n-type silicon substrate) using, for example, a thermal oxidation method or a CVD method. Form. Subsequently, as illustrated in FIG. 7B, a resist 40 is formed on the oxide film 15 so that impurities are not implanted into a region where the p ⁻⁻ type low concentration layer 30 is to be formed, for example, using a photolithography method or the like. To do.

Subsequently, as shown in FIG. 7C, after the oxide film 15 and the resist 40 are formed, an extended p-type base layer 17A is formed from the surface side of the oxide film 15 and the resist 40 using an ion implantation method. Impurities are implanted. Then, as shown in FIG. 7D, after the impurity implantation, the impurity is diffused from both sides of the resist 40 in the n ⁻ -type drift layer 11, and the impurity is connected in the region immediately below the resist 40, thereby expanding the impurity. The p-type base layer 17A and the p ⁻⁻ type low concentration layer 30 are formed.

Through the steps as described above, the n ⁻ type drift layer 11, the extended p type base layer 17 < ^/ b> A and the p ⁻⁻
After forming the mold low concentration layer 30, the electrode layer 12 such as polysilicon is formed over the entire surface of the oxide film 15. Then, portions of the oxide film 15 and the electrode layer 12 where the p-type base region 18 is to be formed are removed to form an opening H. Thereby, as shown in FIG. 8A, a part of the oxide film 15 and the gate electrode 12 are formed on the extended p-type base layer 17 </ b> A and the p ⁻⁻ type low concentration layer 30. Here, an example in which both the oxide film 15 and the electrode layer 12 are removed to form the opening H will be described. However, only the electrode layer 12 is removed and the oxide film 15 is buffered during ion implantation. It may be used as

  Subsequently, as shown in FIG. 8B, using the gate electrode 12 as a mask, impurities are implanted and diffused from the opening H formed in the gate electrode 12 into the extended p-type base layer 17A to form a p-type base. Region 18 is formed. At this time, the p-type base region 18 is formed so that the concentration of the p-type base region 18 is appropriate for forming a channel. Here, it is desirable to form the p-type base region 18 shallow so as not to limit the width of the depletion layer 22 formed in the extended p-type base layer 17A.

Then, as shown in FIG. 8C, after the p-type base region 18 is formed, impurities are diffused into the p-type base region 18 from the opening H formed in the gate electrode 12 again using the gate electrode 12 as a mask. P ⁺ -type region 19 and n ⁺ -type region 20 are formed. When the above steps are completed, the step of forming the oxide film 15 around the gate electrode 12, the step of forming the source electrode 13, the step of forming the drain electrode on the back side of the n ⁻ drift layer 11, etc. in order. As a result, the vertical semiconductor device 10A of the second embodiment shown in FIG. 5 is manufactured.

  As mentioned above, although one embodiment of the vertical semiconductor device according to the present invention has been described, the present invention is not limited to these embodiments, and can be changed without departing from the spirit of the present invention. For example, in the above-described embodiment, an n-channel vertical DMOSFET is exemplified as the vertical semiconductor device, but a p-channel vertical DMOSFET may be formed by reversing the conductivity type of each layer. The vertical semiconductor device according to the present invention is not limited to the vertical DMOSFET, and can be applied to other relay switching elements, power semiconductor elements, and the like.

1 is a cross-sectional view of a vertical semiconductor device 10 according to a first embodiment of the present invention. FIG. 3 is an operation explanatory diagram of the vertical semiconductor device 10 according to the first embodiment of the present invention. It is a 1st process figure showing a manufacturing method of vertical semiconductor device 10 in a 1st embodiment of the present invention. It is a 2nd process figure showing a manufacturing method of vertical semiconductor device 10 in a 1st embodiment of the present invention. It is sectional drawing of 10 A of vertical semiconductor devices in 2nd Embodiment of this invention. It is operation | movement explanatory drawing of 10 A of vertical semiconductor devices in 2nd Embodiment of this invention. It is a 1st process drawing showing a manufacturing method of vertical semiconductor device 10A in a 2nd embodiment of the present invention. It is a 2nd process drawing which shows the manufacturing method of 10 A of vertical semiconductor devices in 2nd Embodiment of this invention. It is sectional drawing of the conventional vertical DMOSFET100.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A ... Vertical type semiconductor device, 11 ... n < ^- > type | mold drift layer (1st semiconductor layer), 12 ... Gate electrode, 13 ... Source electrode, 14 ... Drain electrode, 17, 17A ... Extended p-type base layer (2nd semiconductor layer), 18 ... p-type base region (first semiconductor region), 19 ... ^{p +} -type region, 20 ... ^{n +} -type region (second semiconductor region), 30 ... ^{p -} -type low concentration layer (third semiconductor layer)

Claims (5)

A gate electrode is formed adjacent to the opposite surface of the first semiconductor layer on which the drain electrode is formed, and a source electrode is formed so as to cover between the gate electrodes and the gate electrode. A vertical semiconductor device,
A vertical semiconductor device comprising a second semiconductor layer formed between the first semiconductor region formed on the source electrode side and the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor region. . In the second semiconductor layer, the impurity concentration in a region other than the region directly under the gate electrode is set to be lower than that in the first semiconductor region,
A region immediately below the gate electrode is formed with a third semiconductor layer having a concentration lower than that of the second semiconductor layer and having a conductivity type that is inverted when the impurity voltage is lower than a threshold voltage. The vertical semiconductor device according to claim 1. The first semiconductor layer of the first conductivity type;
The second semiconductor layer of the second conductivity type formed on one surface of the first semiconductor layer;
A plurality of second conductivity type first semiconductor regions formed on the surface of the second semiconductor layer at a predetermined interval;
A second semiconductor region of a first conductivity type formed on a surface of the first semiconductor region and having a higher concentration than the first semiconductor layer;
A plurality of insulating regions formed of a predetermined insulating material so as to straddle the first semiconductor region and the second semiconductor region adjacent to each other;
The gate electrodes embedded in the insulating regions,
The source electrode formed to cover the surface of the first semiconductor region and the insulating region;
The drain electrode formed on the other surface of the first semiconductor layer;
The vertical semiconductor device according to claim 1, further comprising: A method for manufacturing a vertical semiconductor device, comprising:
Forming a first semiconductor layer of a first conductivity type having one surface connected to the drain;
Forming a second semiconductor layer of a second conductivity type, one surface covering the other surface of the first semiconductor layer;
Forming a second conductivity type first semiconductor region having an impurity concentration higher than that of the second semiconductor layer on the other surface of the first semiconductor layer;
Connecting the first semiconductor region to a source;
A method of manufacturing a vertical semiconductor device, comprising: A method for manufacturing a vertical semiconductor device, comprising:
Forming a first semiconductor layer of a first conductivity type having one surface connected to the drain;
Forming an oxide film on the other surface of the first semiconductor layer;
Forming a resist on the surface of the oxide film so that impurities are not implanted into a region where the third semiconductor layer is to be formed;
After the formation of the resist, implanting impurities for forming a second semiconductor layer of the second conductivity type from the surface side of the resist;
After the implantation of the impurities, the impurities are diffused from both sides of the first semiconductor layer sandwiching the resist, and the impurities are connected in a region immediately below the resist, thereby lowering the concentration of the second semiconductor layer and the second semiconductor layer. Forming the third semiconductor layer of the second conductivity type having a concentration which is inverted to the first conductivity type below the threshold voltage;
Forming a second conductivity type first semiconductor region having an impurity concentration higher than that of the second semiconductor layer on the other surface of the first semiconductor layer;
Connecting the first semiconductor region to a source;
A method of manufacturing a vertical semiconductor device, comprising:

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