JP2010041208A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which correctly tests a capability which absorbs a difference of a phase of an input signal and a phase of an internal clock signal in a predetermined range. <P>SOLUTION: The semiconductor integrated circuit includes a signal creation circuit which creates a signal with a phase controlled by the phase of the input signal, and a control value creation block which creates a control value, and tests the signal creation circuit by compulsorily shifting a phase of a signal created by the signal creation circuit according to the control value created by the control value creation block. While operating in synchronization with the internal clock signal, the control value creation block receives a target value synchronizing with an external clock signal from outside, which has a lower frequency than the internal clock signal, and creates the control value which changes in synchronization with the internal clock signal based on the received target value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a loopback test of a semiconductor integrated circuit having a signal generation circuit that generates an internal clock signal (recovered clock) having a phase controlled by the phase of an input signal (phase-synchronized).

  In order to generate an internal clock signal having a phase controlled by the phase of an input data signal or clock signal, a CDR (clock data recovery) circuit or a PLL (phase locked loop) circuit is used. Some CDR circuits and PLL circuits use a voltage controlled oscillator (VCO) as described in Patent Document 1 and others use a numerically controlled oscillator (NCO) as described in Patent Document 2.

  For example, in high-speed serial transfer, a clock is superimposed on output data from the transmission side (transmitter) and transmitted at a predetermined transmission frequency, which is received as input data at the reception side (receiver). In many cases, a clock extraction method is used. A CDR circuit is a circuit that extracts a clock from input data received on the receiving side, and acquires the input data by retiming with the extracted recovered clock.

  By the way, it is necessary to test the ability to absorb the difference between the phase of the input data (data signal, clock signal) and the phase of the recovered clock within a predetermined range in both cases of the CDR circuit and the PLL circuit of various configurations. is there. For example, in a CDR circuit, it is necessary to test the ability to absorb the difference between the transmission frequency of output data on the transmission side and the frequency of the reception clock (recovery clock) on the reception side within a predetermined range.

  On the other hand, as disclosed in Patent Document 3, it has been proposed to test the presence or absence of the above-mentioned capability by forcibly shifting the phase of the recovered clock and determining the result by a loopback test.

  FIG. 5 is a block diagram showing an example of the configuration of a conventional CDR circuit. A CDR circuit 40 shown in the figure represents a schematic configuration of the CDR circuit disclosed in FIG. The CDR circuit 40 includes a phase comparator 18, a digital filter 20, a control circuit 22, a phase divider 24, a retiming circuit 26, a signal output circuit 42, three counters 44, 46, 48, And a signal processing circuit 50.

  Here, the phase comparator 18 compares the phase of the input data and the recovered clock, and detects whether the phase of the recovered clock is advanced or delayed with respect to the phase of the input data. From the phase comparator 18, an up signal or a down signal is output according to the comparison result. That is, an up signal is output when the phase of the recovered clock is delayed from the phase of the input data, and a down signal is output when the phase is advanced.

  The digital filter 20 is a circuit that averages up signals or down signals and optimizes the phase position of the recovered clock. The average signal of the up signal or the down signal output from the digital filter 20 is input to the control circuit 22.

  The control circuit 22 determines a ratio of mixing a plurality of clock signals having different phases in the phase divider 24 based on an average signal of the up signal or the down signal or a pulse signal described later (the phase of the recovered clock). Control signal for changing the frequency).

  The phase divider 24 mixes a plurality of clock signals having different phases supplied from a PLL circuit (not shown) at a predetermined ratio based on the control signal to generate a restored clock having a predetermined phase and frequency ( Change the phase and frequency of the recovered clock).

  The retiming circuit 26 is a circuit that acquires input data by retiming (sampling) in synchronization with the restoration clock. Retiming data is output from the retiming circuit 26.

  In the loopback test, the signal output circuit 42 forcibly generates a predetermined phase difference between the input data input at the transmission frequency from the transmission side and the recovered clock that is the reception clock of the input data on the reception side. It is a circuit that outputs a pulse signal for causing

  When a pulse signal is output from the signal output circuit 42, a control signal is output from the control circuit 22. Thereby, in the phase divider 24, the phase of the recovered clock is shifted according to the control signal, and a phase difference is generated between the input data and the recovered clock. As a result, an up signal or a down signal for canceling the phase difference is output from the phase comparator 18.

  The three counters 44, 46, and 48 count the number of pulses within a predetermined period for the pulse signal output from the signal output circuit 42, the up signal and the down signal output from the digital filter 20, respectively.

  The signal processing circuit 50 detects whether or not the count value of the pulse signal input from the counter 48 and the count value of the up signal or down signal input from the counters 44 and 46 match within a predetermined range. . If the two count values match within a predetermined range, it is determined that there is an ability to absorb the difference between the transmission frequency and the frequency of the recovered clock within the predetermined range.

JP 2004-222115 A JP-A-7-326964 JP 2005-257376 A

  In Patent Document 3, the phase and frequency of the pulse signal output from the signal output circuit 42 are fixed to a monotone signal (the phase and frequency are fixed). Therefore, as shown in the timing chart of FIG. 6, only a monotonous phase shift can be created, and a complicated frequency change or phase change cannot be created. Therefore, there is a problem that it is difficult to accurately test the ability to absorb the difference between the transmission frequency and the frequency of the recovered clock within a predetermined range.

  If a control signal is input from the LSI tester to the control circuit 22 instead of the signal output circuit 24, various frequency changes and phase changes can be created to accurately absorb the frequency and phase difference. It is thought that it is possible to test in a short time by testing and creating such various changes continuously. However, LSI testers can usually handle only low-speed signals of about 100 MHz. Therefore, as shown in the conceptual diagram of FIG. 7, in the low-speed LSI tester 52 operating at a frequency of 100 MHz, the high-speed CDR circuit 40 and the PLL circuit operating at a high frequency (for example, 2 GHz) are continuously operated at high speed. There was a problem that it was difficult to control. On the other hand, an LSI tester that can handle high-speed signals is very expensive, and there is a problem that the test cost increases.

  An object of the present invention is to provide a semiconductor integrated circuit that can solve the problems of the prior art and accurately test the ability to absorb the difference between the phase of the input signal and the phase of the internal clock signal within a predetermined range. It is to provide a circuit.

To achieve the above object, the present invention comprises a signal generation circuit that generates a signal having a phase controlled by the phase of an input signal, and a control value generation block that generates a control value, the control value In a semiconductor integrated circuit that tests a signal generation circuit by forcibly shifting the phase of a signal generated by the signal generation circuit according to a control value generated by a generation block,
The control value generation block operates in synchronization with an internal clock signal, receives a target value from the outside in synchronization with an external clock signal having a frequency lower than that of the internal clock signal, and generates the received target value. The semiconductor integrated circuit is characterized in that the control value that changes in synchronization with the internal clock signal is generated.

  Here, it is preferable that the control value generation block includes an interpolation circuit that performs the interpolation calculation based on the first and second target values received at different timings to generate the control value.

  The control value generation block includes a current control value register that holds a current value of the control value and a target value register that holds a target value received from the outside, and is held in the current control value register It is preferable to include an interpolation circuit that generates the control value by performing an interpolation operation based on the obtained value and the value held in the target value register.

  Moreover, it is preferable that the signal generation circuit is a clock data recovery circuit including a phase comparator that compares the phase of the input signal with the phase of the generated signal.

  According to the present invention, it is possible to create various differences between the phase of the input signal and the phase of the internal clock signal, and to test the ability to absorb the difference more flexibly and accurately than before. In addition, a high-speed LSI tester is not required for the test, and the test can be performed at a low cost.

  Hereinafter, a semiconductor integrated circuit of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block diagram of an embodiment showing a configuration of a semiconductor integrated circuit according to the present invention. A semiconductor integrated circuit 10 shown in FIG. 1 includes a CDR circuit 12, a control value generation block 14, and a test circuit 16. In the semiconductor integrated circuit 10, the test circuit 16 tests the CDR circuit 12 by forcibly shifting the phase of the signal generated by the CDR circuit 12 according to the control value generated by the control value generation block 14.

  The CDR circuit 12 is an example of a signal generation circuit of the present invention that generates a signal having a phase controlled by the phase of an input signal. The CDR circuit 12 includes a phase comparator 18, a digital filter 20, a control circuit 22, a phase divider 24, and a retiming circuit 26. Since the CDR circuit 12 has already been described, repeated description is omitted.

  Subsequently, the control value generation block 14 includes a target value register 28, an interpolation circuit 30, a current control value register 32, and a signal output circuit 34. The control value generation block 14 operates in synchronization with the recovered clock, receives a target value from the LSI tester (external) in synchronization with an external clock signal having a frequency lower than that of the recovered clock, and sets the received target value. Based on this, a control value that changes in synchronization with the recovered clock is generated.

  The target value register 28 is a storage circuit that holds a target value of a control value that controls the difference (phase difference) between the phase of the input data and the phase of the recovered clock. The target value register 28 holds a target value similarly input from the LSI tester in synchronization with the low-speed clock signal input from the LSI tester. The target value output from the target value register 28 is input to the interpolation circuit 30.

  Here, the target value is input from the LSI tester at every predetermined target value setting interval (in this embodiment, as shown in the graph of FIG. 2A, the period T of the low-speed clock signal of the LSI tester). Is held in the target value register 28.

  The current control value register 32 is a storage circuit that holds the current value of the control value that controls the phase difference (current control value). The current control value register 32 holds the initial value of the control value input from the LSI tester in synchronization with the recovered clock signal, and thereafter holds the control value input from the interpolation circuit 30. The current control value output from the current control value register 32 is input to the signal output circuit 34.

  The interpolation circuit 30 generates a control value by performing an interpolation calculation between the current control value and the target value. The interpolation circuit 30 reads the target value held in the target value register 28 from the LSI tester in synchronization with the low-speed clock signal in synchronization with the restoration clock. For example, it is possible to detect the retention of the target value in the target value register 28 and control the reading so as to be read at the next restored clock edge. Thereafter, in synchronization with the restored clock signal, an interpolation operation is performed between the current control value and the target value with a predetermined division number M, and the control value is output. The control value output from the interpolation circuit 30 is input to the current control value register 32.

  Here, according to the speed of the LSI tester to be used and the period of the restoration clock, the period T of the low-speed clock signal is appropriately set so as to be an appropriate division number M. In the present embodiment, as shown in the graph of FIG. 2A, the division number M is set to '4' per period T of the low-speed clock signal of the LSI tester.

  The signal output circuit 34 outputs a pulse signal that forcibly causes a phase difference between the input data and the restored clock according to the control value. The signal output circuit 34 outputs a pulse signal corresponding to the up signal or the down signal in accordance with the up / down switching signal input from the LSI tester. The pulse signal output from the signal output circuit 34 is input to the control circuit 22.

  Here, in the case of the present embodiment, the pulse signal has a constant high level width, and a cycle (that is, the sum of the high level width and the low level width) is a control value input from the current control value register 32. It is a signal that changes in response to.

  Subsequently, the test circuit 16 includes two counters 36 and 38.

  The counters 36 and 38 respectively count the number of pulses of the average signal of the up signal and the down signal output from the digital filter 20. From the counters 36 and 38, the upper few bits of the count value are output in a bit width necessary for obtaining appropriate accuracy. The upper bits of the count value output from the counters 36 and 38 are input to the LSI tester.

  The LSI tester compares the count value input from the counters 36 and 38 with its expected value to test whether or not the CDR circuit 10 has the ability to absorb the difference between the transmission frequency and the frequency of the recovered clock within a predetermined range. Is done.

  Here, the LSI tester tests whether or not the CDR circuit 10 has the ability to absorb the difference between the transmission frequency and the frequency of the recovered clock within a predetermined range. Therefore, at the time of the test, the lower-order bits of the count value corresponding to the predetermined range are ignored. In this way, by ignoring the low-order few bits of the count value and using only the high-order few bits necessary for obtaining appropriate accuracy, it is possible to test at low cost and at high speed.

  Next, the operation of the CDR circuit 10 during the loopback test will be described.

  As shown in the graph of FIG. 2A, the target value m is set in the target value register 28 in synchronization with the low-speed clock signal input from the LSI tester. The interpolation circuit 30 performs an interpolation operation based on the set target value m, the current control value n held in the current control value register 32 at this time, and the division number M. For example, the control value change width (mn) / M is calculated, and the next control value n + (mn) / M is calculated. As described above, in the present embodiment, the division number M is “4”.

  The next control value n + (mn) / M is stored in the interpolation circuit 30, and is held in the current control value register 32 in synchronization with the restoration clock, and is output as the current control value. Further, assuming that the period of the low-speed clock signal is T, the value of change width (mn) / M is added to the current control value every T / M period, and the next control value is calculated. Similarly, in synchronization with the recovered clock, the value of the current control value register 32 is updated with this new control value and output as the current control value.

  Thus, the current control value is n + (mn) × k / M (k = 0, as shown in the graph of FIG. 2A) within one cycle of the low-speed clock signal input from the LSI tester. 1, 2, ..., M). That is, the current control value changes continuously with time, and the cycle of the pulse signal of the signal output circuit 34 changes with time. Therefore, the semiconductor integrated circuit 10 can create a complicated frequency change or phase change as a pulse signal.

  When the current control value changes as shown in the graph of FIG. 2A, the period of the pulse signal changes as shown in the graph of FIG. That is, a pulse signal corresponding to the up signal is output when the up / down switching signal is at a high level, and a pulse signal corresponding to the down signal is output when the up / down switching signal is at a low level. The period of the pulse signal continuously changes (up or down) with time.

  Further, when the pulse signal changes as shown in the graph of FIG. 2B, the phase difference between the input data and the recovered clock becomes as a quadratic curve with time as shown in the graph of FIG. Change.

  Next, FIG. 3 is a timing chart showing waveforms of a pulse signal corresponding to the up signal and a pulse signal corresponding to the down signal. In the range shown in this timing chart, the pulse signal corresponding to the up signal changes so that the frequency gradually becomes lower (the cycle becomes longer) with time. After that, after switching by the up / down switching signal, the pulse signal corresponding to the down signal changes so that the frequency gradually becomes higher (cycle becomes shorter) with time.

  As described above, the CDR circuit 10 can create a complicated frequency change and phase change. Therefore, the ability to absorb the difference between the phase of the input data and the phase of the recovered clock within a predetermined range can be tested more flexibly and accurately than in the past.

  For example, even when the test is performed using a low-speed LSI tester operating at a frequency of 100 MHz, if the division number M is set to “4”, the test is substantially the same as the case where the test is performed at a frequency of 400 MHz. The result can be obtained. That is, even a low-speed LSI tester can test the ability to absorb the difference between the phase of the input data and the phase of the recovered clock within a predetermined range at low cost and at high speed.

  Although an example of the CDR circuit has been described, the present invention can be applied to a CDR circuit having any configuration. Further, the present invention has a feedback path such as a PLL circuit as well as a CDR circuit, and has an internal clock signal (restored) having a phase controlled by the phase of the input signal (phase-synchronized). (Clock) is applicable to a signal generation circuit.

  It is not essential to input an up / down switching signal. For example, the graph of FIG. 4 corresponds to the graph of FIG. 2A, and a signed target value (positive or negative value) is set in the target value register 28 without using an up / down switching signal. This is an example of the case. When the target value is plus (+), it represents a pulse signal corresponding to an up signal, and when it is minus (−), it represents a pulse signal corresponding to a down signal.

  It is not essential to set an initial value of the current control value in the current control value register 32 (initialize the current control value register 32). For example, the target value (first target value) that is first input and stored in the target value register is stored in the current control value register when the next target value (second target value) is input, It is also possible to start control value generation. Further, it is not essential to use the current control value register 32. If the previous target value register for holding the previous target value is provided, the previous target value and the current target value set in the target value register 28 It is also possible to generate a control value by interpolating between the two. In the embodiment, the interpolation circuit 30 is a circuit that generates a current control value that changes linearly by linear interpolation calculation. However, it is also possible to use an interpolation circuit that performs various interpolation operations other than the linear interpolation operation.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

It is a block diagram of one embodiment showing composition of a semiconductor integrated circuit of the present invention. (A), (B), and (C) are graphs showing the relationship between the target value / current control value, the pulse signal period (absolute value), the phase difference of the recovered clock, and the time, respectively. It is a timing chart showing the waveform of the average signal of an up signal and a down signal. It is another graph showing the relationship between target value / current control value and time. It is an example block diagram showing the structure of the conventional CDR circuit. 6 is a timing chart showing waveforms of a pulse signal, input data, and a recovered clock in the CDR circuit shown in FIG. 5. It is a conceptual diagram showing the connection state of a LSI test and a CDR circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 40 Semiconductor integrated circuit 12 CDR circuit 14 Control value generation block 16 Test circuit 18 Phase comparator 20 Digital filter 22 Control circuit 24 Phase divider 26 Retiming circuit 28 Target value register 30 Interpolation circuit 32 Current control value register 34, 42 Signal output circuit 36, 38, 44, 46, 48 Counter 50 Signal processing circuit 52 LSI tester

Claims (4)

A signal generation circuit that generates a signal having a phase controlled by the phase of the input signal; and a control value generation block that generates a control value. The signal according to the control value generated by the control value generation block In a semiconductor integrated circuit that tests a signal generation circuit by forcibly shifting the phase of the signal generated by the generation circuit,
The control value generation block operates in synchronization with an internal clock signal, receives a target value from the outside in synchronization with an external clock signal having a frequency lower than that of the internal clock signal, and generates the received target value. And generating the control value that changes in synchronization with the internal clock signal.   The control value generation block includes an interpolation circuit that generates the control value by performing an interpolation operation based on first and second target values received at different timings. Semiconductor integrated circuit.   The control value generation block includes a current control value register that holds a current value of the control value, and a target value register that holds a target value received from the outside, and is held in the current control value register 2. The semiconductor integrated circuit according to claim 1, further comprising an interpolation circuit that performs an interpolation operation based on a value and a value held in the target value register to generate the control value.   4. The clock data recovery circuit according to claim 1, wherein the signal generation circuit is a clock data recovery circuit including a phase comparator that compares the phase of the input signal with the phase of the generated signal. A semiconductor integrated circuit according to claim 1.

Images