JP2010040734A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device allowing removal of an outside sidewall without damaging a sidewall serving as a base, to thereby form a connection hole reaching source/drain in a self-aligned manner between gate electrodes with reduced space. <P>SOLUTION: A gate structure A is formed on a semiconductor substrate 1, and a non-doped silicon insulation film 11 and an impurity-doped nitride silicon film 13 are formed in this order. Anisotropic etching is performed to the films 11, 13 to form a first sidewall 11a and a second sidewall 13a on a sidewall of the gate structure A. A source/drain diffusion layer 15 is formed on a surface side of the semiconductor substrate 1, and the second sidewall 13a is selectively removed by wet etching using an alkaline etching solution. An inter-layer insulation film is formed on the semiconductor substrate 1, and a connection hole reaching the source/drain diffusion layer 15 is formed in the inter-layer insulation film by etching wherein the first sidewall 11a is used as a stopper. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device applied to a method of forming a contact in a source / drain diffusion layer by self-alignment.

  In the manufacturing process of a semiconductor device, a self-alignment process is applied to contact formation for a source / drain arranged beside a gate electrode. FIG. 6 shows a manufacturing process diagram thereof.

  First, as shown in FIG. 6A, a gate structure a in which a gate insulating film 103, a gate electrode 105, and an offset insulating film 107 are stacked is formed on a semiconductor substrate 101, and this gate structure a is used as a mask. The LDD diffusion layer 109 is formed on the surface side of the semiconductor substrate 101 by the impurity implantation. Next, a sidewall having a two-layer structure including a first sidewall 111 and a second sidewall 113 is formed on the sidewall of the gate structure a, and the surface side of the semiconductor substrate 101 is implanted by impurity implantation using these as a mask. Then, a source / drain diffusion layer 115 is formed. Thereafter, an interlayer insulating film 117 is formed so as to cover them.

  Next, as shown in FIG. 6B, a resist pattern 119 is formed on the interlayer insulating film 117, and the contact hole 117a reaching the source / drain diffusion layer 115 is formed by etching the interlayer insulating film 117 using the resist pattern 119 as a mask. Form. At this time, by using the offset insulating film 107 and the sidewalls 111 and 113 as an etching stopper, a connection hole 117a reaching the source / drain diffusion layer 115 is formed in a self-aligning manner.

  After the above, as shown in FIG. 6 (3), the wiring 121 connected to the source / drain diffusion layer 115 through the connection hole 117a is formed.

  Here, the width W of the sidewalls 111 and 113 is set to a necessary value depending on transistor characteristics. For this reason, the opening diameter of the connection hole 117a tends to be reduced as the space between the gate electrodes 103 and 103 progresses as the semiconductor device is highly integrated. For this reason, in the formation of the connection hole 117a shown in FIG. 6B, it is difficult to remove the interlayer insulating film 17 at the bottom of the connection hole 117a, and an etching residue b is likely to occur. Such etching residue b causes an increase in contact resistance through the connection hole 117a.

  Therefore, after forming the source / drain diffusion layer 115 as shown in FIG. 6A and before forming the interlayer insulating film 117, the outer second sidewalls 111, 113 are formed. A method for removing the sidewall 113 has been proposed. At this time, the outer second sidewall 113 is made of a nitride material, and the base insulating film (for example, the first sidewall 111) is made of an oxide. Then, the outer second sidewall 113 is removed with a selectivity of 5 to 6: 1 with respect to the first sidewall 111 by wet etching using an etching solution containing phosphoric acid. As a result, a sufficient space for forming the connection holes is secured (see Patent Document 1 below).

JP 2001-250864 A (particularly paragraphs 0039, 0045, 0046)

  However, in the manufacturing method described in Patent Document 1 described above, the selectivity with respect to the base insulating film (for example, the first sidewall 111) when removing the outer second sidewall 113 is at most about 5 to 6: 1. Therefore, the first sidewall 111 is likely to be damaged. Thus damaged first sidewall 111 becomes difficult to function as an etching stopper when forming the connection hole, and the self-alignment in forming the connection hole is impaired. Further, since the interlayer insulating film 117 is mainly formed of a silicon oxide film, it is difficult to form a self-aligned connection hole using the first sidewall 111 as an etching stopper in the manufacturing method described in Patent Document 1. .

  Therefore, the present invention can remove the outer side wall without damaging the underlying side wall, thereby forming a connection hole reaching the source / drain in a self-aligned manner between the narrowed gate electrodes. Provided is a method of manufacturing a semiconductor device capable of

  The present invention for achieving such an object is characterized in that it is performed as follows. First, in the first step, a gate structure in which a gate insulating film, a gate electrode, and an offset insulating film are stacked in this order on a semiconductor substrate is formed. In the next second step, a non-doped silicon insulating film such as silicon oxide or silicon nitride and an impurity-doped silicon nitride film are formed in this order so as to cover the gate structure. This material configuration is the first point of the present invention. Thereafter, in a third step, the impurity-doped silicon nitride film and the non-doped silicon-based insulating film are anisotropically etched to form a first sidewall made of the non-doped silicon-based insulating film on the side wall of the gate structure and the impurity-doped silicon nitride film. And a second sidewall made of In the fourth step, a source / drain diffusion layer is formed using the gate structure, the first sidewall, and the second sidewall as a mask. In the fifth step, the second point of the present invention is to selectively remove the second sidewall with respect to the first sidewall by wet etching using an alkaline etching solution. Thereafter, in a sixth step, an interlayer insulating film is formed on the semiconductor substrate, and in a seventh step, a connection hole reaching the source / drain diffusion layer is formed in the interlayer insulating film by etching using the second sidewall as a stopper.

  In wet etching with an alkaline etching solution, the impurity-doped silicon nitride film constituting the second sidewall can be etched with a high etching selectivity of 30 times that of the non-doped silicon insulating film constituting the first sidewall. It becomes. For this reason, in the fifth step, it is possible to remove the second sidewall while reliably preventing damage to the first sidewall. Thus, in the seventh step, a connection hole having an enlarged side wall opening shape can be formed in the interlayer insulating film by etching the interlayer insulating film functioning using the first sidewall as an etching stopper.

  As described above, according to the present invention, the outer sidewalls can be removed without damaging the underlying first sidewalls, so that the sidewall opening shape is expanded in the interlayer insulating film. Connection holes can be formed. Therefore, it is possible to form a connection hole that reaches the source / drain in a self-aligned manner without any residue from the etching residue even between the narrowed gate electrodes.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, as shown in FIG. 1 (1), a semiconductor substrate 1 such as a single crystal silicon substrate is prepared, and a gate structure A in which a gate insulating film 3, a gate electrode 5, and an offset insulating film 7 are stacked thereon. Form a pattern. Next, an LDD diffusion layer 9 is formed on the surface side of the semiconductor substrate 1 by impurity implantation using the gate structure A as a mask. Up to this point, the normal procedure is performed. The offset insulating film 7 is made of a material (for example, silicon nitride) that serves as an etching stopper in subsequent etching for forming a connection hole.

Next, as shown in FIG. 1B, a laminated film of a non-doped silicon-based insulating film 11 and an impurity-doped silicon nitride film 13 is formed so as to cover the gate structure. Here, the non-doped silicon-based insulating film 11 is made of silicon nitride (SixNy) or silicon oxide (SiO ₂ ), and is formed with a film thickness sufficient to serve as an etching stopper when etching the impurity-doped silicon nitride film 13. And On the other hand, the impurity-doped silicon nitride film 13 is made of silicon nitride (hereinafter, SiBN) containing boron (B) as an impurity. The impurity-doped silicon nitride film 13 is formed to have a film thickness sufficient to form sidewalls obtained by anisotropic etching of the films 11 and 13 with a predetermined width.

  Hereinafter, a specific example of forming the non-doped silicon insulating film 11 and the SiBN film 13 will be described.

<First example>
A non-doped silicon insulating film 11 made of silicon nitride is formed by an ALD (Atomic Layer Deposition) method. The deposition gas includes silane (SiH ₂ Cl ₂ ), silane (SiH ₄ ), hexachlorodisilane (Si ₂ Cl ₆ ), trichlorosilane (SiHCl ₃ ) as a gas (Si-based gas) containing silicon (Si). ) Etc. In addition, ammonia (NH ₃ ) is used as a nitrogen (N) -containing gas (N-based gas).

  Then, the non-doped silicon insulating film 11 made of silicon nitride is formed by repeatedly performing the Si atomic layer deposition process to which Si-based gas is supplied and the N-based gas radicalization to nitridate the Si atomic layer. Film.

At this time, the film forming temperature is set to an optimum value around 500 ° C., and film forming is performed in the range of 400 ° C. to 650 ° C. Each film forming gas is used at an appropriate flow rate. For example, dichlorosilane (SiH ₂ Cl ₂ ) is supplied at 500 to 2000 sccm, and ammonia (NH ₃ ) is supplied at 1000 to 5000 sccm.

Next, an impurity-doped silicon nitride film 13 is formed by ALD. In addition to the Si-based gas and the N-based gas similar to the above, the film forming gas includes boron (B) -containing gas (B-based gas) such as trichloroborane (BCl ₃ ), diborane (B ₂ H ₆ ), Trimethylboron [B (CH ₃ ) ₃ : TMB] and borane (BH ₃ ) are used. The addition amount of the B-based gas is about 1% of the Si-based gas, and is in the range of 0.3% to 3% (preferably 0.3% to 1.2%).

  Then, by adding the B-based gas to the Si-based gas and supplying it, the film-forming step of the B-containing Si atomic layer and the step of nitriding the B-containing Si atomic layer by radicalizing the N-based gas are repeatedly performed. Thereby, an impurity-doped silicon nitride film 13 made of SiBN is formed.

At this time, the optimum film deposition temperature is around 500 ° C., and the film is formed in the range of 400 ° C. to 650 ° C. (preferably 400 ° C. to 600 ° C.). Each film forming gas is used at an appropriate flow rate. For example, dichlorosilane (SiH ₂ Cl ₂ ) is supplied at 500 to 2000 sccm, and trichloroborane (BCl ₃ ) is 0.3% to 3% (preferably 0.3%) with respect to dichlorosilane (SiH ₂ Cl ₂ ). And added in a flow rate range of -1.2%). Further, ammonia (NH ₃ ) is supplied at 1000 to 5000 sccm.

  In the above-described formation of the non-doped silicon insulating film 11 made of silicon nitride and the formation of the impurity-doped silicon nitride film 13 made of SiBN, these films are formed by sharing the Si-based gas and the N-based gas. It can be performed continuously.

  Here, FIG. 3 shows the ratio of the B-based gas addition flow rate to the Si-based gas flow rate in the case where the impurity-doped silicon nitride film 13 made of SiBN is formed by the ALD method, and the boron in the formed film. The relationship with the concentration (Boron Conc.) Is shown. As shown in this figure, it can be seen that the boron concentration in the film increases in the film formation temperature range of 400 ° C. to 600 ° C. as the ratio of the B-based gas addition flow rate increases and as the film formation temperature decreases.

  FIG. 4 shows the relationship between the ratio of the B-based gas addition flow rate to the Si-based gas flow rate in the case of forming a SiBN film and the etching rate in wet etching using dilute hydrofluoric acid (DHF). As shown in this figure, it can be seen that at the film forming temperature of 500 ° C., the etching rate is kept almost constant regardless of the B-based gas addition flow rate ratio. Therefore, the non-doped silicon insulating film 11 made of silicon nitride and the impurity-doped silicon nitride film 13 made of SiBN are formed at a film forming temperature of about 500 ° C., so that wet with dilute hydrofluoric acid (DHF) performed in a later step is performed. In the processing, it is possible to prevent either one of the etchings from proceeding excessively.

<Second example>
A non-doped silicon insulating film 11 made of silicon nitride is formed by a low pressure CVD method. As the deposition gas, a gas similar to the ALD method is used. That is, dichlorosilane (SiH ₂ Cl ₂ ), silane (SiH ₄ ), hexachlorodisilane (Si ₂ Cl ₆ ), trichlorosilane (SiHCl ₃ ), or the like is used as a gas (Si-based gas) containing silicon (Si). . In addition, ammonia (NH ₃ ) is used as a nitrogen (N) -containing gas (N-based gas).

  Then, a non-doped silicon insulating film 11 made of silicon nitride is formed by a CVD reaction between the Si-based gas and the N-based gas.

At this time, the film forming temperature can be applied in the range of 630 ° C to 800 ° C. Each film forming gas is used at an appropriate flow rate. For example, the pressure in the film-forming atmosphere is set to 0.1 to 1.0 torr, dichlorosilane (SiH ₂ Cl ₂ ) is supplied at 50 to 500 sccm, and ammonia (NH ₃ ) is supplied at 300 to 1000 sccm.

Next, an impurity-doped silicon nitride film 13 is formed by a low pressure CVD method. As the film forming gas, a gas similar to the ALD method is used. That is, in addition to the Si-based gas and the N-based gas, the gas containing boron (B) (B-based gas) includes trichloroborane (BCl ₃ ), diborane (B ₂ H ₆ ), trimethylboron [B (CH ₃ ) ₃ : TMB] and borane (BH ₃ ) are used. The addition amount of the B-based gas is set to an optimum value of about 1% of the Si-based gas, and is in the range of 0.3% to 3%.

  Then, a B-based gas is added to the Si-based gas, and an impurity-doped silicon nitride film 13 made of SiBN is formed by a CVD reaction with the N-based gas.

At this time, the film forming temperature can be applied in the range of 630 ° C to 800 ° C. Each film forming gas is used at an appropriate flow rate. For example, the pressure in the film-forming atmosphere is set to 0.1 to 1.0 torr, dichlorosilane (SiH ₂ Cl ₂ ) is supplied at 20 to 500 sccm, and trichloroborane (BCl ₃ ) with respect to dichlorosilane (SiH ₂ Cl ₂ ). Is used in a flow rate range of 0.3% to 3%. Further, ammonia (NH ₃ ) is supplied at 200 to 1000 sccm.

  In the above-described formation of the non-doped silicon insulating film 11 made of silicon nitride and the formation of the impurity-doped silicon nitride film 13 made of SiBN, the Si-based gas and the N-based gas are used in common, thereby forming these components. It is possible to carry out the membrane continuously.

<Third example>
After forming the non-doped silicon insulating film 11 made of silicon nitride by the ALD method, the impurity-doped silicon nitride film 13 is formed by the low pressure CVD method.

<Fourth example>
After forming the non-doped silicon insulating film 11 made of silicon nitride by the low pressure CVD method, the impurity doped silicon nitride film 13 is formed by the ALD method.

  After the above, as shown in FIG. 1 (3), the impurity-doped silicon nitride film 13 made of SiBN and the non-doped silicon-based insulating film 11 made of silicon nitride are anisotropically etched, and only on the side wall of the gate structure A. These films 11 and 13 are left. As a result, the first sidewall 11a made of the non-doped silicon-based insulating film 11 is formed from the sidewall of the gate structure A along the surface of the semiconductor substrate 1, and the second sidewall made of the impurity-doped silicon nitride film 13 is formed outside the first sidewall 11a. 13a is formed, and a sidewall having a laminated structure is obtained. This step is performed by anisotropic dry etching (plasma etching) as usual.

  After the formation of the sidewalls 11a and 13a, the surface of the semiconductor substrate 1 is cleaned using an acidic chemical such as hydrofluoric acid. At this time, both the side wall 11a made of silicon nitride and the side wall 13a made of silicon nitride are more resistant to acidic chemicals than the silicon oxide film, so that the change in the shape of the side wall is suppressed to an extent that does not cause a problem.

  In particular, as described with reference to FIG. 4, the film formation of the impurity-doped silicon nitride film 13 made of SiBN and the non-doped silicon-based insulating film 11 made of silicon nitride was performed by the ALD method with a film forming temperature of around 500 ° C. In some cases, the etching rates of these material films with respect to dilute hydrofluoric acid (DHF) are equivalent. For this reason, for example, the side wall shape can be prevented from collapsing due to excessive etching of the first side wall 11a made of the non-doped silicon-based insulating film 11 (silicon nitride).

  Next, as shown in FIG. 1 (4), the source / drain diffusion layer 15 is formed on the surface side of the semiconductor substrate 1 by impurity implantation using the gate structure A and the sidewalls 11a and 13b of the laminated structure as a mask. . This step may be performed as usual.

  Next, as shown in FIG. 1 (5), the second sidewall 13a made of SiBN is selectively etched away with respect to the first sidewall 11a made of silicon nitride. Here, wet etching with an alkaline chemical using an ammonia solution is performed. Thus, the second sidewall 13a made of SiBN is removed by etching at a term selection ratio of about 1:30 with respect to the first sidewall 11a made of silicon nitride.

  In this state, the first sidewall 11a protrudes on the semiconductor substrate 1 in accordance with the width of the second sidewall 13a. For this reason, the formation of the source / drain diffusion layer 15 described with reference to FIG. 1 (4) may be performed with the second sidewall 13a removed by etching.

  Thereafter, as shown in FIG. 2A, an interlayer insulating film 17 is formed on the semiconductor substrate 1 so as to cover the gate structure A, the first sidewall 11a, and the source / drain diffusion layer 15. The interlayer insulating film 17 is made of, for example, a silicon oxide film.

  Next, as shown in FIG. 2B, a resist pattern 19 is formed on the interlayer insulating film 17, and the source / drain diffusion layers between the gate structures A are etched by etching the interlayer insulating film 17 using the resist pattern 19 as a mask. A connection hole 17a reaching 15 is formed. At this time, the connection hole 17a is formed in a self-aligned manner with respect to the source / drain diffusion layer 15 by using the offset insulating film 7 and the first sidewall 11a as an etching stopper.

  After the above, as shown in FIG. 2 (3), the wiring 21 connected to the source / drain diffusion layer 15 through the connection hole 17a is formed, and the semiconductor device 23 is obtained.

  According to the embodiment described above, a laminated structure of the first sidewall 11a made of silicon nitride and the second sidewall 13a made of SiBN is adopted. Thus, in the wet etching using the alkaline etching solution described with reference to FIG. 1 (5), the etching selectivity of the second sidewall 13a made of SiBN to the first sidewall 11a made of silicon nitride is 30. Can be doubled.

FIG. 5 shows the relationship between the ratio of the B-based gas addition flow rate to the Si-based gas flow rate and the wet etching rate with an aqueous ammonia solution (NH ₄ OH), which is an alkaline etching solution, when forming a SiBN film. FIG. As shown in this figure, it can be seen that the etching rate increases as the B-based gas addition flow rate ratio increases with respect to the etching rate of the SiBN film formed at a gas flow rate ratio of 0%, that is, the silicon nitride film. If the deposition temperature is 450 ° C., the etching selectivity of the SiBN film to the silicon nitride film deposited at a gas flow ratio of 0% is increased by 30 times by setting the B-based gas addition flow ratio to about 0.8%. Can be.

  Thereby, in the step of removing the second sidewall 13a shown in FIG. 1 (5) by wet etching using an ammonia solution, damage to the first sidewall 11a can be reliably prevented. For this reason, in the step of forming the connection hole 17a shown in FIG. 2B, the shape of the side wall opening is enlarged in the interlayer insulating film 17 by etching the interlayer insulating film 17 which functions using the first sidewall 11a as an etching stopper. The formed connection hole 17a can be formed.

  As a result, it is possible to form the connection hole 17a reaching the source / drain diffusion layer 15 in a self-aligned manner without any residue of the etching residue even between the gate electrodes 5-5 having a narrow space. In addition, since etching residue can be prevented, an increase in contact resistance can be suppressed.

  In the above-described embodiment, the sidewall has a two-layer structure. However, a sidewall having a multilayer structure may be used. In this case, the outermost side wall may be constituted by the impurity-doped silicon nitride film 13 as the first side wall 13a, and the lower side wall may be constituted by the non-doped silicon insulating film 11 as the second side wall 11a. It is possible to obtain the effect.

It is sectional process drawing (the 1) which shows the manufacture procedure of embodiment. It is sectional process drawing (the 2) which shows the manufacture procedure of embodiment. Relationship between the ratio of the B-based gas addition flow rate to the Si-based gas flow rate and the boron concentration (Boron Conc.) In the formed film when an impurity-doped silicon nitride film made of SiBN is formed by the ALD method FIG. It is a figure which shows the relationship between the ratio of the B type | system | group gas addition flow rate with respect to Si type | system | group gas flow rate in the case of forming a SiBN film | membrane, and the etching rate in the wet etching using a dilute hydrofluoric acid (DHF). The ratio of B-based gas addition rate for Si-based gas flow rate in the case of forming a SiBN layer is a diagram showing the relationship between the wet etching rate of the aqueous ammonia solution is an alkali etching solution (NH ₄ OH). It is sectional process drawing which shows an example of the manufacturing procedure of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3 ... Gate insulating film, 5 ... Gate electrode, 7 ... Offset insulating film, 11 ... Non-doped silicon type insulating film, 13 ... Impurity doped silicon nitride film, 11a ... 1st side wall, 13a ... 2nd side Walls, 15 ... source / drain diffusion layers, 17 ... interlayer insulating films, 17a ... connection holes, 23 ... semiconductor devices, A ... gate structures

Claims (2)

Forming a gate structure in which a gate insulating film, a gate electrode, and an offset insulating film are stacked in this order on a semiconductor substrate;
A second step of forming a non-doped silicon-based insulating film and an impurity-doped silicon nitride film in this order so as to cover the gate structure;
By anisotropically etching the impurity-doped silicon nitride film and the non-doped silicon-based insulating film, a side wall of the gate structure has a first sidewall made of the non-doped silicon-based insulating film and the impurity-doped silicon nitride film. A third step of forming a second sidewall,
A fourth step of forming a source / drain diffusion layer on the surface side of the semiconductor substrate by introducing impurities using the gate structure, the first sidewall, and the second sidewall as a mask;
A fifth step of selectively removing the second sidewall with respect to the first sidewall by wet etching using an alkaline etching solution;
A sixth step of forming an interlayer insulating film on the semiconductor substrate after the fourth step and the fifth step;
And a seventh step of forming a connection hole reaching the source / drain diffusion layer in the interlayer insulating film by etching using the second sidewall as a stopper. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity-doped silicon nitride film is a boron-containing silicon nitride film.

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