JP2010040062A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale in a semiconductor memory device, on which a plurality of memory arrays are mounted. <P>SOLUTION: In the semiconductor memory device, a first topology, where one power source 201 and a plurality of memory arrays 11, 12 and 13 are connected in parallel, and the plurality of memory arrays 11, 12 and 13 and a ground are connected in parallel, and a second topology, where one end of a serial circuit having the plurality of memory arrays 11, 12 and 13 are connected is connected to the power source 201 in series, and the other end of the serial circuit is connected to the ground, are switched mutually in accordance with an operation mode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In recent years, flash memory has been rapidly spread. In particular, NAND flash memory is suitable for downsizing and large capacity, and is widely used as a recording medium for portable devices such as digital cameras, portable music players, and notebook PCs. Also in the field of flash memory, multi-chip packages in which a plurality of memory chips are stacked are put into practical use. Employing a multi-chip package can increase the capacity while suppressing an increase in circuit area.

Patent Document 1 discloses a semiconductor memory device having a multi-chip package structure in which a plurality of non-volatile semiconductor memory chips mounted with a booster circuit for supplying a boosting power for writing / erasing to a memory cell array are assembled.
JP 2006-286048 A

  In the nonvolatile memory, the power supply voltage used in each operation mode of the read mode, the write mode, and the erase mode is different. Therefore, it is necessary to generate a plurality of voltages having different levels by a plurality of DC-DC converters. However, since a DC-DC converter such as a charge pump has a relatively large circuit area, mounting a plurality of DC-DC converters leads to an increase in circuit area.

  The present invention has been made in view of such circumstances, and an object thereof is to reduce the circuit scale in a semiconductor memory device having a plurality of memory arrays.

  In a semiconductor memory device according to an aspect of the present invention, a plurality of memory arrays, one power source and each of the plurality of memory arrays are connected in parallel, and each of the plurality of memory arrays and a ground are connected in parallel. The first connection form and the second connection form in which one end of a series circuit in which a plurality of memory arrays are connected in series is connected to a power supply and the other end of the series circuit is connected to the ground, according to the operation mode. And a controller for switching.

  According to the present invention, the circuit scale can be reduced in a semiconductor memory device equipped with a plurality of memory arrays.

  FIG. 1 is a diagram showing an overall configuration of a semiconductor memory device 100 according to an embodiment of the present invention. The semiconductor memory device 100 includes a memory unit 10, a power supply unit 20, a control unit 30, and an I / O unit 40. The memory unit 10 includes a plurality of memory arrays. Here, three memory arrays (first memory array a11, second memory array b12, and third memory array c13) are included. The memory unit 10 may have a configuration in which each memory array is made into one chip and stacked.

  The power supply unit 20 includes a DC-DC converter and a stabilization circuit (not shown), and converts a power supply voltage supplied from an external DC power supply (for example, a lithium ion battery) into a power supply voltage to be supplied to the memory unit 10. For example, 7V and 15V are generated from 3V supplied from an external DC power supply.

  The control unit 30 receives a data read instruction, a data write instruction, a data erase instruction, and the like including address designation from an external processor (not shown) (for example, a CPU mounted on a notebook PC), and executes those instructions. A control signal for output to the memory unit 10 and the I / O unit 40 is output. In addition, in the present embodiment, the control unit 30 also outputs a control signal for switching the connection form of the path for supplying power to the plurality of memory arrays.

  That is, the controller 30 specifies the operation mode by receiving the command, and in accordance with the operation mode, the first connection configuration in which the power supply voltage is supplied in parallel and the second connection mode in which the power supply voltage is supplied in series. Switch between connection types. More specifically, the first connection form is a form in which one power supply and each of a plurality of memory arrays are connected in parallel, and each of the plurality of memory arrays and a ground are connected in parallel. The second connection form is a form in which one end of a series circuit in which a plurality of memory arrays are connected in series is connected to a power supply, and the other end of the series circuit is connected to ground. Details of the process for switching between the first connection form and the second connection form will be described later.

  The I / O unit 40 controls data transmission / reception between an external work memory (not shown) and the memory unit 10 according to control by the control unit 30.

  In semiconductor memory device 100, the ratio between the power supply voltage to be supplied to each memory array in the first operation mode and the power supply voltage to be supplied to each memory array in the second operation mode. And the number of the memory arrays may be associated with each other. More specifically, both may substantially coincide with each other. Details of this correspondence will be described later.

Hereinafter, a case where each memory array is configured by a NAND flash memory will be described as an example.
FIG. 2 is a schematic diagram for explaining the configuration and operation mode of the memory array according to the embodiment of the present invention. Each memory array has a large number of bit lines BL (hereinafter collectively referred to simply as bit lines BL) and a large number of word lines WL (hereinafter collectively referred to simply as word lines WL) wired in a matrix. A memory cell S is formed at the intersection. More specifically, a plurality of transistors with floating gates are connected to each bit line, and the control gate of each transistor with floating gates is connected to one of the word lines. In FIG. 2, 3 × 3 memory cells S are drawn to simplify the configuration, but a large number of memory cells S are actually arranged.

  The bit line BL is connected to the amplifier unit 15. The amplifier unit 15 includes a read amplifier and a write amplifier. A read amplifier is used for data reading, and a write amplifier is used for data writing. At the time of data reading, data read from the bit line BL by the read amplifier is output to the outside through the input / output circuit 17 in the cell array and the I / O unit 40 outside the cell array. At the time of data writing, data is input from the outside via the I / O unit 40 and the input / output circuit 17 and applied to the bit line BL by the write amplifier. The word line WL is connected to the decoder 16, and the decoder 16 selectively activates each word line included in the word line WL.

  FIG. 3 is a diagram showing bias conditions in each operation mode of the memory array shown in FIG. In the read mode, the decoder 16 is connected to the control gate of the selected cell SS while 5 V is applied to all bit lines (whether or not the selected cell SS is connected) and 0 V is applied to the well W of the substrate. 0V is applied to the selected word line, and 5V is applied to the word line to which the control gate of the selected cell SS is not connected. Under this bias condition, current flows when the value written in the selected cell SS is “1”, and no current flows when the value is “0”. Unselected cells function as transfer gates.

  In the write mode, the decoder 16 is connected to the bit line to which the selected cell SS is connected, 7 V is applied to the bit line to which the selected cell SS is not connected, and 0 V is applied to the well W of the substrate. 15V is applied to the word line to which the control gate is connected, and 7V is applied to the word line to which the control gate of the selected cell SS is not connected. Under this bias condition, a tunnel current flows from the floating gate of the selected cell SS to the well W, and electrons are injected into the floating gate. A tunnel current does not flow in a non-selected cell.

  The erase mode is a mode in which the values of all the memory cells sharing the well W are erased (value is set to “0”). In the erase mode, 15 V is applied to the well W in a state where 0 V is applied to all bit lines and all word lines (both whether or not the selected cell SS is connected). Under this bias condition, a tunnel current flows from the well W to the floating gate, and electrons in the floating gate escape.

  FIG. 4 is a diagram showing a power supply path to the first memory array a11, the second memory array b12, and the third memory array c13 included in the memory unit 10 according to the embodiment of the present invention. Hereinafter, description will be made on the assumption of the bias condition shown in FIG. The first power supply voltage (15V) 201 and the second power supply voltage (7V) 202 are power supply voltages generated by the power supply unit 20. The switch SW1 is controlled by the control unit 30.

  The first power supply voltage (15V) 201 is supplied to the read power supply terminal VddR of the first memory array a11 via the switch SW1. The first power supply voltage (15V) 201 is supplied to the write / erase power supply terminal VddWE of the first memory array a11 via the switch SW1. The second power supply voltage (7V) 202 is supplied to the write power supply terminal VddW of the first memory array a11. The read ground terminal GNDR of the first memory array a11 is connected to the read power supply terminal VddR of the second memory array b12. The write / erase ground terminal GNDWE and the write ground terminal GNDW of the first memory array a11 are connected to the ground.

  The first power supply voltage (15V) 201 is supplied to the write / erase power supply terminal VddWE of the second memory array b12 via the switch SW1. The second power supply voltage (7V) 202 is supplied to the write power supply terminal VddW of the second memory array b12. The read ground terminal GNDR of the second memory array b12 is connected to the read power supply terminal VddR of the third memory array c13. The write / erase ground terminal GNDWE and the write ground terminal GNDW of the second memory array b12 are connected to the ground.

  The first power supply voltage (15V) 201 is supplied to the write / erase power supply terminal VddWE of the third memory array c13 via the switch SW1. The second power supply voltage (7V) 202 is supplied to the write power supply terminal VddW of the third memory array c13. The read ground terminal GNDR, the write / erase ground terminal GNDWE, and the write ground terminal GNDW of the third memory array c13 are connected to the ground.

  Here, the second power supply voltage (7V) 202 is supplied in parallel to the first memory array a11, the second memory array b12, and the third memory array c13, and the connection form is general.

  In the write mode or the erase mode, the control unit 30 switches the switch SW1 so that the voltage source of the first power supply voltage (15V) 201 and the write / erase power supply terminal VddWE of each memory array are brought into conduction. This connection form corresponds to the first connection form. In this connection configuration, the first power supply voltage (15V) 201 is supplied in parallel to the first memory array a11, the second memory array b12, and the third memory array c13.

  On the other hand, in the read mode, the control unit 30 switches the switch SW1 so that the voltage source of the first power supply voltage (15V) 201 and the read power supply terminal VddR of the first memory array a11 are brought into conduction. This connection form corresponds to the second connection form. This connection form is a series circuit using the first memory array a11, the second memory array b12, and the third memory array c13 as loads. When the voltage is divided substantially equally by the first memory array a11, the second memory array b12, and the third memory array c13, this is equivalent to a state in which a power supply voltage of 5 V is supplied to each. Details of this equivalent circuit will be described later.

  FIG. 5 is a diagram illustrating a power supply path to the first memory array a11, the second memory array b12, and the third memory array c13 included in the memory unit 10 according to the comparative example. Hereinafter, differences from the power supply path shown in FIG. 4 will be described. In the comparative example, in addition to the first power supply voltage (15V) 201 and the second power supply voltage (7V) 202 shown in FIG. 4, the third power supply voltage (5V) 203 needs to be generated by the power supply unit 20. In that case, the switch SW1 is not provided.

  A third power supply voltage (5V) 203 is supplied in parallel to the read power supply terminals VddR of the first memory array a11, the second memory array b12, and the third memory array c13. The read ground terminals GNDR of the first memory array a11, the second memory array b12, and the third memory array c13 are connected to the ground.

  FIG. 6 is a diagram showing an equivalent circuit of the series circuit formed in the read mode in the connection mode shown in FIG. The operation in the memory array in the read mode is as follows. First, the bit line BL and the word line WL are charged to 5V. Next, the word line connected to the selected cell SS is discharged by the decoder 16. Next, the data appearing on the bit line BL is amplified by the read amplifier. Next, the input / output circuit 17 outputs the amplified data to the outside of the memory array.

  Here, in FIG. 6, the first equivalent capacitor C110 in the first memory array a11, the second equivalent capacitor C210 in the second memory array b12, and the third equivalent capacitor C310 in the third memory array c13 shown in FIG. The bit line BL and the word line WL to be charged and discharged are expressed as equivalent capacitances. Thus, the first memory array a11 in the read mode can be expressed by a parallel circuit of the first equivalent capacitor C110, the first read amplifier equivalent resistor R115, and the first input / output circuit equivalent resistor R117. Similarly, the second memory array b12 in the read mode can be expressed by a parallel circuit of the second equivalent capacitor C210, the second read amplifier equivalent resistor R215, and the second input / output circuit equivalent resistor R217. Similarly, the third memory array c13 can be expressed by a parallel circuit of a third equivalent capacitor C310, a third read amplifier equivalent resistor R315, and a third input / output circuit equivalent resistor R317.

  In the NAND flash memory, strictly speaking, in the bit line BL, a current flows through the bit line in which “1” is written in the selected cell SS, and a current substantially flows in the bit line in which “0” is written. Not flowing. However, it can be considered that the number of bit lines in which “1” is written in the bit line BL and the number of bit lines in which “0” is written are substantially equal. Therefore, it can be considered that the parallel circuit always consumes substantially constant power. Therefore, if the first memory array a11, the second memory array b12, and the third memory array c13 are connected in series and 15V is supplied to the power supply terminal of the series circuit, the voltage drops by 5V each.

  More specifically, the first equivalent capacitor C110, the second equivalent capacitor C210, and the third equivalent capacitor C310 can be regarded as equivalent, and 15V is third in the initial charge to the bit line BL and the word line WL. Be divided. In the read mode, the values of the read amplifier equivalent resistance and the input / output circuit equivalent resistance differ depending on whether the data read from the bit line BL is “1” or “0”. However, since a large number of data are read at the same time, the number of “1” read from the bit line BL is substantially equal to the number of “0”. Therefore, the values of the read amplifier equivalent resistance and the input / output circuit equivalent resistance are substantially equal in the first memory array a11, the second memory array b12, and the third memory array c13. Therefore, 15V is divided into three equal parts at the time of amplification by the read amplifier and at the time of output of the input / output circuit 17.

  As described above, according to the embodiment of the present invention, in a semiconductor memory device mounted with a plurality of memory arrays, each of the first connection mode and the second connection mode is switched according to the operation mode. A plurality of power supply voltages having different levels to be supplied to the memory array can be generated from one voltage source. Therefore, it is not necessary to provide a DC-DC converter in each memory array, and the circuit scale can be reduced. Further, since the types of power supply voltages to be generated by the power supply unit 20 outside the memory array can be reduced, the circuit scale of the power supply unit 20 can be reduced. Comparing the connection configuration according to the present embodiment shown in FIG. 4 and the connection configuration according to the comparative example shown in FIG. 5, the former operates with two types of power supply voltages, while the latter has three types of power supply voltages. Otherwise it will not work. Specifically, the former can reduce the circuit scale by the amount of circuit elements that generate the third power supply voltage (5 V) 203 than the latter.

  In the second connection configuration in which a plurality of memory arrays are connected in series, the current flowing through the first memory array a11 can be reused in the second memory array b12 and the third memory array c13, thereby reducing power consumption. can do. Further, by switching between the first connection mode and the second connection mode, the power supply voltage to each memory array can be switched at high speed, and high-speed verify operation is possible. In addition, since the same power supply is used for the read and the program, the number of power on / off times can be reduced compared to the case of using separate power supplies, and high-speed mode switching and low power consumption can be achieved. be able to.

  As described above, the power supply voltage to be supplied to each memory array in the read mode (5 V in the embodiment) and the power supply voltage to be supplied to each memory array in the write mode or erase mode (implementation) 15V in the embodiment (1: 3 in the embodiment) and the number of memory arrays (“3” in the embodiment) are associated with each other. More specifically, the following effects are obtained when they are substantially matched. That is, a power supply voltage required in the read mode can be supplied to each memory array without connecting an adjustment load in the series circuit. Therefore, an increase in circuit scale can be suppressed.

  The present invention has been described based on some embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the above-described embodiment, the NAND flash memory has been described as an example. However, the present invention can also be applied to a NOR flash memory and other nonvolatile memories. The memory unit 10 and its power supply wiring described in the embodiment may be configured as one unit, and a semiconductor memory device including a large number of the unit configuration may be constructed. Further, one or two of the first memory array a11, the second memory array b12, and the third memory array c13 may be replaced with an adjustment load that consumes equivalent power. In this case, the number of memory arrays can be arbitrarily adjusted while using the power supply method according to the present embodiment.

1 is a diagram showing an overall configuration of a semiconductor memory device according to an embodiment. It is a schematic diagram for demonstrating the structure and operation mode of the memory array which concern on embodiment. FIG. 3 is a diagram showing bias conditions in each operation mode of the memory array shown in FIG. 2. It is a figure which shows the power supply path | route to the 1st memory array a contained in the memory part which concerns on embodiment of this invention, the 2nd memory array b, and the 3rd memory array c. It is a figure which shows the power supply path | route to the 1st memory array a contained in the memory part, the 2nd memory array b, and the 3rd memory array c based on a comparative example. FIG. 5 is a diagram showing an equivalent circuit of the series circuit formed in the read mode in the connection mode shown in FIG. 4.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 memory part, 11 1st memory array a, 12 2nd memory array b, 13 3rd memory array c, 15 amplifier part, 16 decoder, 17 input / output circuit, 20 power supply part, 30 control part, 40 I / O part , 100 semiconductor memory device, 201 first power supply voltage (15V), 202 second power supply voltage (7V), 203 third power supply voltage (5V), W well, BL bit line, WL word line, S cell, SS selection cell SW1 switch, C110 first equivalent capacitance, C210 second equivalent capacitance, C310 third equivalent capacitance, R115 first read amplifier equivalent resistance, R215 second read amplifier equivalent resistance, R315 third read amplifier equivalent resistance, R117 first input Output circuit equivalent resistance, R217 Second input / output circuit equivalent resistance, R317 Third input / output circuit equivalent resistance.

Claims (5)

Multiple memory arrays;
A first connection configuration in which one power source and each of the plurality of memory arrays are connected in parallel, and each of the plurality of memory arrays and ground are connected in parallel, and the plurality of memory arrays are connected in series A second connection configuration in which one end of the connected series circuit is connected to the power source and the other end of the series circuit is connected to the ground, and a control unit that switches according to an operation mode;
A semiconductor memory device comprising:   The ratio between the power supply voltage to be supplied to each memory array in the first operation mode and the power supply voltage to be supplied to each memory array in the second operation mode, and the number of the memory arrays The semiconductor memory device according to claim 1, wherein the semiconductor memory device is associated with each other.   2. The semiconductor memory device according to claim 1, wherein the control unit selects the second connection form in a read mode and selects the first connection form in a write mode or an erase mode.   The ratio between the power supply voltage to be supplied to each memory array in the read mode and the power supply voltage to be supplied to each memory array in the write mode or erase mode is associated with the number of the memory arrays. 4. The semiconductor memory device according to claim 3, wherein:   5. The semiconductor memory device according to claim 1, wherein the plurality of memory arrays are constituted by NAND flash memories.

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