JP2010034666A - Optical receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical receiver which is equipped with the sufficient number of pixels, correctly detects a light source of modulation light and detects a signal from the light source. <P>SOLUTION: The optical receiver is provided with: a light receiving section in which a plurality of imaging blocks each consisting of a pixel unit for short cycle and a pixel unit for long cycle are arranged in matrix; and a lens for forming an image on the light receiving section upon receiving light from the outside. The optical receiver is further provided with; a long cycle scanning means for scanning the pixel units for long cycle in all the imaging blocks of the light receiving section; and a light source detecting means for detecting a light source from the output to be read from the pixel unit for long cycle. The optical receiver is provided with: a short cycle scanning means for scanning pixel units for short cycle in the a light source detection region including the plurality of imaging blocks in the vicinity of the pixel unit corresponding to the detected light source; and a signal detecting means for detecting a signal from the output to be read from the pixel units for short cycle. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a receiver that belongs to the field of optical communication and receives and demodulates modulated light.

  Non-Patent Document 1 describes a basic standard for a visible light communication system. In visible light communication, there are a baseband communication method and a subcarrier communication method, the former is a method in which information is directly communicated while being converted into an electric signal, and the latter is after information is converted into an electric signal, In this method, a predetermined subcarrier (subcarrier) is modulated and transmitted / received. Both methods include a digital method and an analog method.

  Non-Patent Document 2 describes a basic standard for a unidirectional communication system (visible light ID system) using visible light as a carrier wave. 4PPM is used as an encoding method for modulating a subcarrier of 28.8 kHz, and is called SC-4PPM. In 4PPM, one symbol is divided into four slots, and a 2-bit code is represented by a slot in which a subcarrier pulse train is arranged. That is, of the four slots, when the subcarrier pulse train is arranged in the first slot, 00 is represented, and when the pulse train is arranged in the second slot, 01 is represented, and the pulse train is represented in the third slot. When arranged, it represents 10, and when a pulse train is arranged in the fourth slot, 11 is represented.

  In Patent Document 1, as a signal processing circuit for detecting light from a remote controller using infrared rays of home appliances, the output of a light receiving element is amplified, the frequency band of a carrier wave is filtered by a band pass filter, and then detected by a detector. It is described that demodulation is performed by integrating with an integrator and shaping the waveform with a comparator having hysteresis characteristics.

  Further, Patent Document 2 irradiates a plurality of capacitors connected to a photodiode through a gate with light generated by irradiating light from a light source in a pulsed manner and incident on the photodiode from a visual field. It is described that sorting is performed in synchronization with It describes that signal processing is performed on the charges accumulated in the plurality of capacitors, an output waveform corresponding to pulsed light irradiation from the light emission source is extracted, and the distance to the subject is measured from the phase difference. Yes.

  Patent Document 3 describes a structure and manufacturing method of an embedded photodiode. A P-type region 13 is formed on the N-type region 6 (FIG. 1 (e)) of the photodiode formed on the semiconductor substrate, and the N-type photodiode region 6 is embedded (FIG. 1 (f)). The charges generated in the photodiode region 6 are transferred to the N-type region 7 serving as a charge transfer portion by the action of the silicon electrode serving as a transfer gate.

  In Non-Patent Document 3, modulated light is sent in parallel from a plurality of LEDs, and a receiver forms an image of a light source on a light receiving surface in which light receiving elements are arranged two-dimensionally via a lens, and is received at a plurality of image positions. A parallel optical communication system that demodulates light in parallel is described.

  Non-Patent Document 4 describes an ID camera system using a CMOS image sensor that can recognize the ID of a beacon from a long distance. This camera system has two operation modes, a scene mode and an ID mode. In the ID mode, an ID image is created by performing a sampling process of 12 kHz on all pixels (192 × 124) of the image.

The frequency that can be handled by the method of Non-Patent Document 4 is 12 kHz, and cannot cope with the modulated light frequency of 40 kHz used in a general remote controller.
JP-A-8-237207 US Patent 6,239,456 JP-A-2-304974 Visible light communication system, JEITA CP-1221, Japan Electronics and Information Technology Industries Association, published in March 2007 Visible light ID system, JEITA CP-1222, Japan Electronics and Information Technology Industries Association, published in June 2007 "Analysis of LED-Allocation for High-Speed Parallel Wireless Optical Communication System", Satoshi Miyauchi, Radio and Wireless Symposium, 2006 IEEE, January 17-19, 2006, pp 191-194 “ID CAM: a smart camera for scene capturing and ID recognition Mixed and augmented Reality”, Nobuyuki Matsushita, 2003, Proceedings, The Second IEEE and ACM International Symposium, October 7-10, 2003, pp 227-236

  There is a need for a receiver capable of accurately detecting a light source of modulated light and detecting a signal from the light source while arranging light receiving elements in two dimensions and having a sufficient number of pixels.

  An optical receiver that receives light from a light source that emits modulated light according to the present invention has a plurality of imaging blocks each composed of a short-cycle pixel unit and a long-cycle pixel unit arranged in a matrix. A light receiving unit; and a lens that receives light from the outside and forms an image on the light receiving unit. The optical receiver further includes a long cycle scanning unit that scans the long cycle pixel units of all the imaging blocks of the light receiving unit, and a light source detection unit that detects a light source from an output read from the long cycle pixel unit. . In addition, the optical receiver includes a short cycle scanning unit that scans a short cycle pixel unit in a light source detection region including a plurality of imaging blocks in the vicinity of the pixel unit corresponding to the detected light source, and a short cycle pixel unit. Signal detecting means for detecting a signal from the output read from the signal.

  According to the present invention, the entire light receiving unit is scanned with a long period to detect the light source, and a region with the detected light source is scanned with a short period to detect the signal, so that the signal can be efficiently detected as a whole. Can do.

  In one form of this invention, a light source detection means is comprised so that environmental light may be removed and a light source may be detected by using the difference output from each of the pixel unit for long periods. Optical receiver.

  According to this aspect, the ambient light is offset by using the differential output from the pixel unit, and the light from the flashing light source is detected as the difference between the output in the on state and the output in the off state. Can be detected.

  In another aspect of the present invention, the short period scanning means is configured to scan the light source detection region at a speed at which sampling can be performed at a rate that is twice or more the rate of the signal from the light source.

  According to this embodiment, only the light source detection region can be sampled accurately according to the sampling theory.

  In one aspect of the present invention, the short cycle pixel unit is configured to sequentially distribute the charge generated in the light receiving region to a plurality of charge storage units, and configured to execute the sampling by the distribution. Yes.

  According to this embodiment, sampling is performed by the charge distribution operation based on the physical structure of the pixel unit, so that the processing burden on the circuit is reduced.

  In one aspect of the present invention, the optical receiver includes a first vertical scanning circuit connected to the long-cycle pixel row of the imaging block, and a second vertical scan circuit connected to the short-cycle pixel row of the imaging block. A vertical scanning circuit of the imaging block, a first horizontal scanning circuit connected to a column of pixels for a long cycle of the imaging block, a second horizontal scanning circuit connected to a column of pixels for a short cycle of the imaging block, Is provided.

  According to another aspect of the present invention, each of the imaging blocks includes first and second pixel units for a short period and first and second pixel units for a long period, and the first pixel The second pixel unit is exposed (charge accumulation) during the unit readout period, and the first pixel unit is exposed during the second pixel unit readout period.

Base Technology Next, the base technology of the present invention will be described with reference to FIGS. This base technology is described in Japanese Patent Application No. 2008-148455 by the applicant of this application. FIG. 1 is a functional block diagram of the optical receiver 10, and the optical receiver 10 includes a light receiving unit 12 that receives an image formed by a lens 19. The light receiving unit 12 has a structure in which a plurality of pixel units are two-dimensionally arranged. The pixel unit outputs four samples at a predetermined time interval with respect to the charge generated in the photoelectric conversion unit, and holds the samples in the sampling capacitors 14a, 14b, 14c, and 14d.

  The difference circuit 16 takes the difference between the voltages held in the sampling capacitors. When the light from the light source that always emits light takes a difference, the sample value as the difference becomes zero. On the other hand, the intensity-modulated light, that is, the light from the blinking light source, has a difference value representing the intensity of the light pulse. The pulse discriminator 18 discriminates the presence of an optical pulse according to this criterion, and sends an electric pulse signal corresponding to the sequentially detected optical pulse to the decoder 20. The timing control unit 22 controls the read timing so that charges are read from the four charge storage regions of the pixel unit at a speed suitable for the pulse frequency of the intensity modulated light to be received.

  By performing the pulse discrimination process for all the pixel units of the light receiving unit 12, it is possible to detect one or more light sources that emit intensity-modulated light in the image. The function of the pulse discriminator 18 will be described in detail later.

  In FIG. 1, a projector 17 outputs blinking light provided from the computer 11, coded by the encoder 13, and modulated as a light pulse by the modulator 15. The projector 17 may be a light emitting diode (LED) or a laser diode capable of emitting a high rate (repetitive frequency) light pulse. The projector 17 may be a light emitting diode that emits a high-rate infrared pulse.

  FIG. 2 shows a conventional general arrangement of the pixel units 25 in the light receiving unit 12. FIG. 3 is a diagram created by estimating the layout of the pixel unit described in Patent Document 2. In FIG. Each pixel unit 25 includes a photoelectric conversion unit 25a that converts light into electric charge. As shown in the A-A ′ sectional view, the photoelectric conversion unit 25 a is a buried photodiode formed by embedding an N-type region in a P-type region (P well) of a semiconductor substrate. The charges generated by the photoelectric conversion unit 25a are distributed by the distribution gates Tx1 and Tx2, and are stored at different timings in the first charge storage region 27a and the second charge storage region 27b. The first and second charge storage regions 27a and 27b are formed of N-type regions embedded in the P-type region.

  The difference circuit 16 shown in FIG. 2 reads out charges from the first and second charge accumulation regions of each pixel under the control of the vertical operation circuit 23 and the horizontal scanning circuit 27, takes a difference between output values, and outputs a difference image output. Output. The charge storage regions 27a and 27b are connected to the reset electrodes 29a and 29b via the reset gates Ra and Rb. At the beginning of the cycle for detecting the charge generated by the photoelectric conversion unit 25a, the reset gates Ra and Rb are opened, and the charge storage regions 27a and 27b are charged by the voltage V applied to the reset electrode. This is called reset, and the electrons generated in the photoelectric conversion unit 25a act in a direction to reduce the charge in the charge storage regions 27a and 27b in the charged state.

  FIG. 3 schematically shows the structure of the pixel unit 25 of the light receiving section as shown in Patent Document 2, for example. The photoelectric conversion unit 25a of the pixel unit 25 is a photodiode, and is connected to the charge storage region 27a via the distribution gate Tx1 and to the charge storage region 27b via the distribution gate Tx2. The charge storage regions 27a and 27b are connected to the reset electrodes 29a and 29b via the reset gates Ra and Rb. The cross-sectional view shown in the lower part of FIG. 3 shows that the photoelectric conversion part 25a is formed by embedding an N-type region in a P-type well of a semiconductor substrate. The edge of the N-type region is drawn up on the surface of the substrate. The N-type is shown in FIGS. 1 (f), 2 (e) and 3 (a) of Patent Document 3. This is to represent the same structure as the edge of the region 6 and represents a known structure. By applying a potential to the gate Tx1, the charge moves from the photoelectric conversion region 25a to the N + region of the charge storage region 27a.

  The lower part of FIG. 3 shows an A-A ′ cross section of the pixel unit 25. An N-type layer 25a is buried in a P-type well (P-well), and a photodiode is formed by a PN junction with a P + region formed thereon. A charge storage region 27a is formed next to the MOS structure transfer gate Tx1. The charge storage region 27a is composed of an N region embedded in a P-type well region 61. The N + region 29a forms a reset electrode and is connected to the wiring of the voltage V. The N + region 27a and the N + region 29a are electrically connected by applying a signal to the gate R1 of the MOS structure. The pixel unit 25 is entirely covered with a light-shielding curtain 51 except for the photoelectric conversion region 25a.

  FIG. 4 is a circuit diagram of the pixel unit of FIG. 3, and FIG. 5 shows a potential well change in this circuit. The light receiving region 25a, that is, the photoelectric conversion unit 25a is indicated by a diode having a photoelectric conversion action and a capacitor C0. Referring to FIG. 5, (A) shows a potential well in a state where no operation is applied to the circuit. In (B), the distribution gates Tx1 and Tx2 and the reset gates R1 and R2 are opened and a voltage V is applied to eliminate charges in the photoelectric conversion unit and the charge storage region. (C) shows a state in which charges are generated in the photoelectric conversion unit 25a during the first period of the first exposure. (D) shows a state in which the distribution gate Tx1 is opened and charges accumulated in the photoelectric conversion unit 25a are transferred to the charge storage region 27a (capacitor C1).

  Next, (E) shows how charges are generated in the photoelectric conversion unit 25a during the second period of the first exposure. (F) shows a state where the sorting gate Tx2 is opened and charges are transferred to the charge storage region C2. (G) shows a state in which the first period of the second exposure has started, and (H) shows how the charges accumulated in the photoelectric conversion unit in (G) are transferred to the charge storage region 27a (capacitor C1). . In this manner, the exposure cycle is repeated n times, and the charges accumulated in the charge accumulation region 27a (capacitor C1) and the charge accumulation region 27b (capacitor C2) during this time are read by opening the output gate T. The L1 and L2 FET transistors are level shift transistors, and when the output gate T is opened, a current corresponding to the potential of the capacitor C1 or C2 is sent to a downstream sampling capacitor (difference circuit).

  FIG. 6 is a layout diagram of the pixel unit 25 used in the light receiving unit 12 of the optical receiver 10. In this example, the photoelectric conversion unit of one pixel is divided into four micro conversion units 25a, 25b, 25c, and 25d. Four charge storage regions 27a, 27b, 27c, and 27d are provided corresponding to the four micro conversion units. The charges generated by the micro conversion units 25a, 25b, 25c, and 25d move to the charge transfer region 31 having a lower potential. The four micro conversion parts 25a, 25b, 25c, 25d and the charge transfer region 31 can be formed by an integral N-type region embedded in a P-type region (P-well). A light-shielding curtain (light-shielding mask) is provided above the integrated N-type region so that light enters only the micro conversion units 25a, 25b, 25c, and 25d.

  When one of the distribution gates Tx1, Tx2, Tx3, and Tx4 is opened at a timing that will be described later, the charge in the charge transfer region 31 flows to one of the charge accumulation regions 27a, 27b, 27c, and 27d corresponding to the opened gate. Similar to the structure of FIG. 3, the pixel unit 25 is covered with a light-shielding curtain (not shown) except for the micro conversion units 25a, 25b, 25c, and 25d that are photoelectric conversion regions.

  The pixel unit 25 is provided with reset electrodes 29a, 29b, 29c, and 29d adjacent to the charge storage regions 27a, 27b, 27c, and 27d. When the reset gates R1, R2, R3, and R4 are opened, the charge storage regions 27a, 27b, 27c, and 27d are charged by the voltage V applied to the reset electrodes 29a, 29b, 29c, and 29d to be in a reset state. As is clear from the timing chart shown later, the reset process is performed simultaneously on all the charge accumulation regions of all the pixel units.

  FIG. 7 is an equivalent circuit of the pixel unit 25 of FIG. 6, in which the micro conversion units 25a, 25b, 25c, and 25d are shown as a pair of a photodiode and capacitors C0a, C0b, C0c, and C0d. The charge transfer region 31 is indicated by a capacitor C3. Charge storage regions 27a, 27b, 27c, and 27d adjacent to the distribution gates Tx1, Tx2, Tx3, and Tx4, respectively, are represented by capacitors C1, C2, C3, and C4. These capacitors are charged with the voltage V when the FET transistors of the reset gates R1, R2, R3, and R4 are turned on. This operation is called reset and is for creating an initial state before accumulating the charge generated by the photodiode.

  The FET transistors L1, L2, L3, and L4 are level shift transistors, and when the read gates T1, T2, T3, and T4 are opened, currents corresponding to the charges held in the capacitors C1, C2, C3, and C4 are generated. It acts to feed to the sampling capacitors 14a, 14b, 14c, 14d of FIG.

  FIG. 8 shows the operation timing of the pixel unit 25. The waveform of incident light indicates a pulse waveform of modulated light emitted from a visible light ID transmitter, an infrared remote controller, a beacon, or the like. In this example, the light from the remote controller is transmitted using a subcarrier, and the waveform of the incident light in FIG. 8 shows the pulse waveform of the subcarrier. In this example, sampling is performed four times per period of the subcarrier.

  First, the pixel unit 25 is reset immediately before the remote control light symbol. At the same time when the reset gate is opened, the four sorting gates Tx1, Tx2, Tx3, and Tx4 are opened to reset (charge) the charge transfer region 31 and the charge storage regions 27a, 27b, 27c, and 27d. Next, in the first sampling period, the sorting gate Tx1 is opened, and the charges generated by the four micro conversion units 25a, 25b, 25c, and 25d are transferred to the charge accumulation region 27a (capacitor C1) via the charge transfer region 31. store. The charge received from the charge transfer region 31 acts in the direction of decreasing the voltage of the capacitor C1.

  Subsequently, in the second sampling period, the distribution gate Tx2 is opened, and the charges generated by the four micro conversion units 25a, 25b, 25c, and 25d are stored in the charge storage region 27b (capacitor C2) via the charge transfer region 31. Next, in the third sampling period, the distribution gate Tx3 is opened, and the charges generated by the four micro conversion units 25a, 25b, 25c, and 25d are stored in the charge storage region 27c (capacitor C3) via the charge transfer region 31. . Further, in the fourth sampling period, the distribution gate Tx4 is opened, and the charges generated by the four micro conversion units 25a, 25b, 25c, and 25d are stored in the charge storage region 27d (capacitor C4) via the charge transfer region 31.

  When one cycle is completed in this way, the next cycle is entered and the same sampling is repeated. The capacitors C1, C2, C3, and C4 are sequentially integrated with the charges received in the first, second, third, and fourth samplings of each period until the m period is completed. When the m period ends, the transfer gates T1, T2, T3, and T4 are opened. Since the voltages of the capacitors C1, C2, C3, and C4 are applied to the gates of the level shift transistors L1, L2, L3, and L4, the current corresponding to the voltage level of each capacitor is the sampling capacitor 14a in FIG. , 14b, 14c, 14d.

  FIG. 9 is a timing chart showing a sampling form in an example in which a pulse of one symbol of modulated light is displayed by 21 subcarrier pulses. FIG. 10 shows the timing of sampling over a plurality of symbols. In other words, FIG. 9 shows the sampling timing at the level of the 21 subcarrier pulses constituting the pulse of one symbol of FIG.

In FIG. 9, in this example, the sub-carrier repeats the accumulation cycle and the read cycle every five cycles of the pulse. In this method, after accumulating charges in the charge accumulation regions 27a, 27b, 27c, 27d in the accumulation cycle, the output gate is opened in the read cycle and output to the sampling capacitors 14a, 14b, 14c, 14d, and the difference circuit 16 and The pulse discriminator 18 obtains a sampling value. In the example of FIG. 11, assuming that the values read from the sampling capacitors 14a, 14b, 14c, and 14d are C (θ ₀ ), C (θ ₁ ), C (θ ₂ ), and C (θ ₃ ), The sampling value R is obtained according to the equation 1 shown below. Formula 1 also includes an expression for obtaining the phase θ of the modulated light.

  In FIG. 9, only Tx1 is shown in the distribution gate due to restrictions on drawing. However, according to the timing shown in FIG. 8, the distribution gates Tx1, Tx2, Tx3, and Tx4 are opened the same number of times in the accumulation cycle. The reset gate is opened at the beginning of the accumulation cycle.

  FIG. 10 shows a logical value of zero by a space of the same width following a main pulse composed of 21 subcarrier pulses, and a logical value of 1 by a space of three times the width following the main pulse. An example of a remote control signal representing is shown. In FIG. 10, the first symbol represents a logical value of zero and the second symbol represents a logical value of one. Sampling is performed at the timing shown in FIG. 9 for each symbol. A sampling value is determined by the pulse discriminator 18 in FIG. 1, and a pulse train shown in FIG. 10D is sent to the decoder 20.

  FIG. 12 shows an example of the specification of intensity modulation used for a remote control using infrared light of home appliances. Referring to FIG. 12A, a 38 KHz pulse is used as a subcarrier, and a logic zero symbol is represented by 21 subcarrier pulses (560 microseconds) followed by a space of the same width. A logic one symbol is represented by 21 subcarrier pulses followed by a space three times as wide.

  Referring to FIG. 12B, a 9 ms continuous subcarrier pulse train followed by a 4.5 millisecond space is arranged as a leader indicating the start of the symbol train before the symbol train. The symbol string includes 16 bits indicating the device number consisting of a low address (Address low) and a high address (Address high). This address is followed by 8 bits of the command, followed by 8 bits that invert this command. After this, a pulse train indicating the end is arranged at the end of the symbol train, and a blank section is provided as a trailer between the next symbol train.

  FIG. 13 shows processing for detecting a reader from the remote control signal shown in FIG. 11 using this method. Since the reader is a 9-ms pulse train as shown in FIG. 12 (B), the timing controller 22 detects the pulse train by accumulating charges at a cycle of 2.25 ms, which is a quarter of the reader period. Enter the mode to do. (101). As shown in FIG. 8, since one period of the subcarrier is 26.7 microseconds, 2.25 milliseconds corresponds to 84.3 periods of the subcarrier. Therefore, in FIG. 8, m = 84, and charge accumulation in the charge accumulation regions 27a, 27b, 27c, 27d is performed, and subsequently read out to the sampling capacitors 14a, 14b, 14c, 14d and based on the difference calculation of the difference circuit 16 The pulse discriminator 18 determines the sampling value. By repeating this process during 9 milliseconds of the reader period, the pulse discriminator 18 discriminates the leader pulse.

  This process is executed for the entire screen of the light receiving unit 12 (103). Thereby, it is possible to detect transmission of the reader from one or a plurality of light sources that are transmitting remote control signals. When the reader is detected (105), the timing controller 22 enters a mode for accumulating charges at a cycle of 1.1 milliseconds, which is 1/4 of that, in order to detect a 4.5 millisecond space following the reader. 1.1 milliseconds corresponds to 41.2 periods of subcarriers. Therefore, in this mode, the pulse discrimination as described above is performed by setting the charge accumulation period m in FIG. 8 to m = 41. In this mode, it is not necessary to perform processing for the entire screen, and a reader can be detected and partial readout of pixels and several to several tens of pixels around them can be performed (109).

  If no optical pulse is detected by this partial readout process, a 4.5 millisecond space is detected. Thus, the process enters a 140 microsecond charge accumulation mode for that quarter period to detect a 560 microsecond symbol pulse (113). Even in this mode, partial readout is limited to the pixel in which the reader is detected and the surrounding pixels (115).

  When an optical pulse is detected in this mode (117), the reader detection process is terminated, and the bit reading process of FIG. 14 is continued. In the bit reading process, the logical value of the symbol is determined according to the symbol arrangement described with reference to FIG. Blocks 131 and 133 are identical to blocks 113 and 115 in FIG. If no light pulse is detected in the charge accumulation mode of 140 microseconds and the pixel is in a dark state (135), it means that a space of 560 microseconds has been detected, so the space count n is set to 1 ( 137). Subsequently, charge accumulation for 140 microseconds is performed in blocks 139 and 141, and the space count n is incremented by one. (143). Steps 139 to 143 are repeated until the pixel becomes bright.

  When the pixel becomes bright, that is, when a light pulse is detected (145), if the count n exceeds 3, it means that the width of the space is 3 times the pulse width, so the logical value is determined to be 1. (149). If n does not exceed 3, the logical value of the symbol is determined to be 0 according to the encoding rule of FIG. 12A (151). In this way, the remote control signal is decoded.

First Embodiment FIG. 15 shows a configuration of an optical receiver according to an embodiment of the present invention. The pixel units 25-00, 25-01, ... 25-pk have a structure in which the charge generated in the photoelectric conversion area is distributed and accumulated at a predetermined time interval, and the difference can be extracted in the readout circuit. It is. Specifically, one pixel shown in FIG. 3 may correspond to one photoelectric conversion region, or one pixel shown in FIG. 6 may have a structure corresponding to four fine photoelectric conversion regions.

  In this embodiment, the pixel unit has the structure shown in FIG. 6, and the overall configuration of the apparatus is the same as that shown in FIG. In FIG. 15, the wiring from the pixel unit to the readout circuits 16a and 16b is shown by one line, but as seen in the equivalent circuit shown in FIG. 7, there are four output lines from the pixel unit. In FIG. 15, the four output lines are bundled and shown as one line.

  In one embodiment, two adjacent pixel units form one imaging block. For example, the pixel units 25-00 and 25-10 form one imaging block, and all the other pixel units similarly form a pair to form an imaging block.

  One of the two pixel units included in one imaging block is for long-period scanning, and the other is for short-period scanning. For example, the pixel unit 25-00 is for long cycle scanning, and the pixel unit 25-10 is for short cycle scanning. Since all the imaging blocks are assigned in the same manner, the rows of the pixel units 25-00, 25-01,... 25-0k are rows for long-period scanning. Similarly, the rows of the pixel units 25-10, 25-11,..., 25-1k are rows for short cycle scanning. Since the entire pixel unit array 50 of the light receiving unit is configured in the same manner, rows for long-period scanning and rows for short-period scanning are alternately arranged.

  The long cycle scanning unit 51 scans and sequentially reads the long cycle pixel units of the imaging block. A high-speed reading setting start 201 in FIG. 16 indicates a long-period scanning process. Since this scanning is a process for detecting a light source that emits light, scanning is performed at a relatively low speed. In one embodiment, the number of pixels on the light receiving surface is 240 horizontal and 180 vertical. The number of pixels for the long period is 240 × 180/2 = 21,600. This is read out in half the time of 2.25 milliseconds, for example, and judged in half the time. In this case, the read frequency is 19 MHz.

  The entire light-receiving surface is read by long-period scanning (203), and the light source is detected by the difference output of the long-cycle pixel unit (205). The light source detection unit 53 represents each of one or a plurality of light sources detected on the light receiving surface by, for example, an area of 10 pixels in length and width, and creates an xy coordinate of the start point as a light emitting area list (207). This is sent to the short cycle scanning unit 55.

  The short cycle operation unit 55 stores the received xy coordinates of one or a plurality of light emitting areas in a register, and executes a short period, that is, high speed reading of the light emitting areas. The fast read start 211 in FIG. 16 illustrates this process. As an initial state, the number m of read light emitting areas is set to zero (213). The xy coordinates of the start point of one or a plurality of light emitting areas sent from the light source detection unit 53 are set in the register (215).

  First, high-speed sampling partial reading is executed for one light emitting region (217). When the light emission in the light emitting area is detected and reading is completed (219), the light emitting area is processed and the setting of the light emitting area is updated (221). The update can be performed by setting a processed flag in the processed light emitting area. The number m of processed light emitting areas is incremented (223), and if m is smaller than the total number of light emitting areas, the process returns to step 215 to execute a short period scanning of the next light emitting area. Thus, when the number m of processed light emitting areas reaches the total number of light emitting areas (225), this process is terminated.

  In the short cycle scanning, a light emitting region whose start point is defined by xy coordinates is scanned, and a signal is detected by the method described with reference to FIGS.

Second Embodiment Next, another embodiment of the present invention will be described. In this embodiment, the imaging block is composed of four pixel units. Referring to FIG. 15, in this embodiment, the first imaging block is composed of four pixel units 25-00, 25-01, 25-10, and 25-11. Similarly, all the pixel units are incorporated in the imaging block, and the entire light receiving surface 50 is an array of imaging blocks having a 4-pixel configuration.

  In the first imaging block, the pixel unit 25-00 is an even pixel for short cycle scanning, and the pixel unit 25-01 is an odd pixel for short cycle scanning. The pixel unit 25-10 is an even pixel for long-period scanning, and the pixel unit 25-11 is an odd pixel for long-period scanning. Four pixels of all imaging blocks are configured in the same manner.

  FIG. 17 is a timing diagram corresponding to FIG. 9 when the imaging block of this embodiment is used. This timing chart is for a short period scan. In FIG. 9, charge accumulation cycles and read cycles occur alternately. In FIG. 17, when the even pixel unit finishes the charge accumulation cycle (indicated by even exposure) and enters the readout cycle, the odd pixel unit enters the charge accumulation cycle, and the even pixel readout cycle and the odd pixel charge accumulation cycle ( (Shown by odd exposure) simultaneously proceed in parallel.

  In the timing diagram of FIG. 9, when the pixel unit is in the readout cycle, information from the light source cannot be captured, but according to this embodiment, information from the light source can be captured at all times, and signal processing is performed. Increases efficiency.

  FIG. 18 is a timing chart corresponding to FIG. 10 when the imaging block of this embodiment is used. It is shown that when an even pixel finishes a charge accumulation cycle using a sorting gate and enters an output cycle, an odd pixel enters a charge accumulation cycle using a sorting gate. Similarly, when the odd pixel enters the output cycle, the even pixel enters the charge accumulation cycle.

Reference Example FIGS. 19 to 21 show an example of pulse position modulation (abbreviated as PPM) of visible light ID shown in Non-Patent Document 2. FIG. The symbol period is divided into four slots, and coding is performed depending on where the modulated light (flashing light) exists in the four slots. Such coding using four slots is called 4PPM. If there is modulated light in the first slot, 00 is indicated, if there is modulated light in the second slot, 01 if the modulated light is in the third slot, 10 if the modulated light is in the fourth slot, and 11 is indicated.

  As shown in FIG. 19, the time for one symbol and four slots is 416 microseconds, and the time for one slot is 104 microseconds, which is one fourth of the time. Since the frequency of the subcarrier is 28.8 kHz, three periods (28.8 * 0.104 = 3) of the subcarrier appear in one slot. One period of the subcarrier is 34.7 microseconds (104/3 = 34.7).

  As shown in FIG. 19, the start of the visible light ID 4PPM signal is the 12 slots in which the subcarriers are sequentially arranged in the first, second and third slots, followed by 9 slots of 0. (3 symbol periods) This is indicated by a 1248 microsecond preamble.

  FIG. 20 shows the timing for sampling the subcarrier pulses. During the 34.7 microsecond exposure period, the charge is distributed to the four micro photoelectric conversion areas of one pixel, and during the next 34.7 microsecond readout period, the charge in each micro photoelectric conversion area is read out, and the sample value R according to Equation 1 Is required. Thus, since one sampling requires an exposure period of 34.7 microseconds and a readout period of 34.7 microseconds, for a total of 69.4 microseconds, 416 / 69.4 = 6 samplings during one symbol 416 microseconds Is executed.

  FIG. 21 shows a frame structure of coding by 4PPM. In the frame, a frame type field is arranged after the preamble field. A payload (data) field follows, followed by a CRC field.

  In 4PPM, when a symbol “00” with a subcarrier comes in a first slot following a symbol “11” with a subcarrier in a fourth slot, two slots with a subcarrier continue. However, there are no three consecutive subcarrier slots in data coding. Therefore, the preamble can be detected by detecting that the subcarriers are continuously present in the three slots and the subsequent slots without the subcarrier are consecutive.

  FIG. 22 shows a process for detecting a preamble based on the above items. Exposure (241) of 34.7 microseconds, which is one cycle of the subcarrier, is performed, and pixels in the area portion where the light source image is detected are read (243). When the sample value calculated as described above is 1, it is determined that there is a bright pixel (245). When a bright pixel is detected, the exposure reading cycle count number i is set to 0 (247). In steps 249 and 251, the next exposure and readout cycles are executed, and the count number i is incremented (253). If a bright pixel is detected (255), the process returns to step 249 to execute the next pixel exposure and readout cycle.

  The count i starts from 0. When no bright pixel is detected in step 255, it is determined whether the count number i exceeds 3 (257). When the count number i is 3 or less, no preamble is detected, and the process returns to step 241. As described with reference to FIG. 19, six exposure and readout cycles are performed for one symbol, and the preamble has 4.5 sub-carrier pulses in three consecutive slots. * 3/4 = 4.5) Detected as bright pixels. That is, the preamble is detected by detecting bright pixels continuously four times or more.

  If the count number i is 4 or more, the count number j of the counter that counts the number of exposure and readout cycles for blank pixels is set to 0 (259), and the number of exposure readout cycles for blank pixels is counted ( 261, 263, 265). Blank pixel exposure and readout cycles are counted until i + j reaches 18 corresponding to 3 symbols (267). When 18 is reached, that is, when processing for 3 symbols constituting the preamble is completed (269), the preamble is counted. The detection of is terminated.

  As shown in FIG. 21, in the frame of the 4PPM signal, 4 slots (8 bits) following the preamble represent the frame type. FIG. 23 shows a process flow for reading four slots representing the frame type.

  As shown in FIG. 21, a field of payload (data) of 256 slots (512 bits) is arranged next to 4 slots representing the frame type. FIG. 24 shows a flow of processing for reading 256 slots of this payload.

  As seen in FIG. 21, an 8-slot (16 bits) CRC (Cyclic Redundancy Check) code is arranged in a 4PPM frame. CRC is a cyclic code for detecting a transmission error. FIG. 25 shows a flow of processing for reading these 8 slots.

  Next, the decoding of the frame type field, the payload field, and the CRC field will be described with reference to FIGS. By detecting the three symbols of the preamble as described above, the division of the symbols becomes clear. FIG. 26 is a decoding table, and the rightmost column shows 2 bits represented by one symbol of 4PPM. t0 is the number of exposure and readout cycles counted from the beginning of the symbol until the subcarrier pulse is detected. t1 is the count number of exposure and readout cycles in which the subcarrier pulse is detected. t2 is the count of exposure and readout cycles in the slot where no pulse is detected after detecting a subcarrier pulse in that symbol.

  As described above, since there are six exposure and readout cycles for one symbol, t0 + t1 + t02 = 6. Referring to FIGS. 19 and 26, in the first and second lines of FIG. 26, when the count of t0 is 0, the count of t1 is 1 or 2, and the rest is the count of t2, It is determined that there is a carrier wave, indicating that the symbol is decoded into 2 bits of 00.

  Similarly, in the third and fourth lines, when t0 is 1 or 2, t1 is 2 or 1, and the remaining is t2, the second slot is determined to have a subcarrier, and the symbol is 2 of 01. Indicates that it is decoded into bits.

  In the fifth and sixth lines, when t0 is 3, t1 is 1 or 2, and t2 is 2 or 1, it is determined that there is a subcarrier in the third slot, and the symbol is decoded into 2 bits of 10. It is shown that. Further, in the seventh and eighth lines, when t0 is 4 or 5, and t1 is 2 or 1, it is determined that there is a subcarrier in the fourth slot, and the symbol is decoded into 11 2 bits. Is shown.

  27 and 28 are flowcharts of processes for executing another decoding method. The 34.7 microsecond exposure 303 and the partial readout 305 are the exposure and readout cycles described with reference to FIG. The initial value of t is set to -1 in step 301, and is set to 0 in the first step 307. As a result of sampling by the exposure and readout cycles in steps 303 and 305, if it is determined that the sample is bright (ie, there is a subcarrier pulse), 1 is set to V [0] (311), and no subcarrier pulse is detected. , V [0] is set to 0 (313). V [0] stores a numerical value 1 or 0 as a result of the first sampling.

  If t is smaller than the sampling number 6 of one symbol (315), the process returns to step 303 to repeat the exposure and readout cycle. Depending on the result, 1 or 0 is entered in V [1] that stores the value of the second sampling (311, 313). This process is repeated until six samplings are completed, and the resulting values are stored in V [2], V [3], V [4], and V [5].

  FIG. 28 shows an algorithm for decoding a symbol based on the value of the V [t] array thus obtained. If the result of the first sampling V [0] is 1 (321), since there is a subcarrier in the first slot, the symbol is decoded to 00 (329). If the result of the third sampling V [2] is 1 (323), since there is a subcarrier in the second slot, the symbol is decoded to 01 (331). If the result of the fourth sampling V [3] is 1 (325), since there is a subcarrier in the third slot, the symbol is decoded to 10 (333). If the result V [5] of the sixth sampling is 1 (327), since there is a subcarrier in the fourth slot, the symbol is decoded to 11 (335).

  Although the present invention has been described with respect to specific embodiments, the present invention is not limited to such embodiments.

1 is a block diagram showing the overall configuration of an optical receiver according to an embodiment of the present invention. The figure which shows an example of the arrangement | sequence of a light receiving element. The figure which shows the layout of the light receiving element of a prior art. The figure which shows the equivalent circuit of FIG. FIG. 4 is a diagram showing potential and charge movements in the light receiving element of FIG. 3. The figure which shows the structure of the pixel unit of one Example of this invention. The figure which shows the equivalent circuit of the pixel unit of FIG. The figure which shows the timing of the sampling in a pixel unit. The figure which shows the relationship between a charge accumulation cycle and a read cycle. The timing diagram which shows the timing of FIG. 9 macroscopically. The figure which shows the principle of sampling. The figure which shows the relationship between symbol coding and a subcarrier. 6 is a flowchart showing a reader search process. 6 is a flowchart showing a process of reading bits. The figure which shows the structure of the imaging device of the Example of this invention. The flowchart which shows the scanning process using a long period and a short period. The figure which shows the timing of the reading using even exposure and odd exposure. The figure which shows the timing of the reading using even exposure and odd exposure. The figure which shows the example of a coding of pulse position modulation (PPM). The timing diagram which shows the relationship between the exposure cycle for reading the subcarrier of 4PPM signal, and a read cycle. The figure which shows the frame structure of 4PPM signal. The flowchart which shows the process which searches the preamble of 4PPM signal. The flowchart which shows the process which reads the frame type of 4PPM signal. The flowchart which shows the process which reads the payload of 4PPM signal. The flowchart which shows the process which reads CRC contained in a 4PPM signal. The figure which shows an example of the table which can be used for the decoding of 4PPM signal. The flowchart which shows an example of the process which decodes 4PPM signal. The flowchart which shows an example of the process which decodes 4PPM signal.

Explanation of symbols

50 pixel unit array 51 long cycle scanning unit 53 light source detection unit 55 short cycle scanning unit

Claims (6)

An optical receiver for receiving light from a light source that emits modulated light,
A light receiving section in which a plurality of imaging blocks each consisting of a pixel unit for a short period and a pixel unit for a long period are arranged in a matrix;
A lens that receives light from the outside world and forms an image on the light receiving unit;
Long-period scanning means for scanning pixel units for long periods of all imaging blocks of the light receiving unit;
Light source detection means for detecting a light source from an output read from the long-cycle pixel unit;
Short cycle scanning means for scanning the short cycle pixel unit in a light source detection region including a plurality of imaging blocks in the vicinity of the pixel unit corresponding to the detected light source;
Signal detection means for detecting a signal from an output read from the short cycle pixel unit;
The optical receiver.   2. The optical receiver according to claim 1, wherein the light source detection unit is configured to detect a light source by removing ambient light by using a differential output from each of the long-cycle pixel units.   2. The optical receiver according to claim 1, wherein the short period scanning unit is configured to scan the light source detection region at a speed at which sampling can be performed at a rate that is twice or more the rate of a signal from the light source. Machine.   The short-cycle pixel unit is configured to sequentially distribute charges generated in the light receiving region to a plurality of charge storage units, and configured to execute the sampling by the distribution. The optical receiver described. A first vertical scanning circuit connected to a row of pixels for the long period of the imaging block;
A second vertical scanning circuit connected to a row of pixels for the short period of the imaging block;
A first horizontal scanning circuit connected to the long-cycle pixel row of the imaging block;
A second horizontal scanning circuit connected to the column of pixels for the short period of the imaging block;
The optical receiver according to claim 1, comprising:   Each of the imaging blocks is composed of first and second pixel units for a short cycle and first and second pixel units for a long cycle, and the second pixel unit is read out during the readout period of the first pixel unit. 2. The optical receiver according to claim 1, wherein the optical receiver is configured to perform exposure (charge accumulation) of a pixel unit and to perform exposure of the first pixel unit during a reading period of the second pixel unit.

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