JP2010033323A - Multiprocessor, debugging device for debugging the same, and debug method for debugging the multiprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor, a debugging device, and a debug method for executing steps in order of a program even when there are a plurality of CPU cores in one chip. <P>SOLUTION: In the multiprocessor 1 incorporating a CPU 2a, CPU 2b and CPU 2c, respective commands of the CPU 2a, CPU 2b and CPU 2c are decoded by a decoder 21 so as to transit them to a monitor state when operating steps, a monitor transitable signal is output when a command is transitable to a monitor state, and the respective CPU are transited to the monitor state when all the CPU output monitor transitable signals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multiprocessor including a plurality of CPUs (Central Processing Units) as a core, a debugging apparatus for debugging the multiprocessor, and a debugging method for debugging the multiprocessor.

  In recent years, in order to improve the processing capability of LSI (Large Scale Integration), many have adopted a multiprocessor configuration in which a plurality of CPU cores are built in one chip. In debugging a processor including a plurality of CPU cores, since the plurality of CPU cores operate synchronously, it is necessary to perform debugging in accordance with a time series of programs executed in the respective CPU cores. When there is a CPU core that does not operate as intended by the programmer during debugging, a breakpoint is set on the program of the target CPU core, and each CPU core is debugged from the program execution state to the monitor state. The mode is shifted to the mode, and the value stored in the register or the memory is checked while performing the step execution operation one instruction at a time in the vicinity thereof.

  Patent Documents 1 to 5 disclose the transition of a plurality of cores to the monitor state at the same time.

Further, step execution in which instructions are executed one by one in a multiprocessor configuration is disclosed in Patent Document 6. Patent Document 6 describes that when the operating frequencies of a plurality of CPU cores are different, a plurality of CPU cores can be stepped simultaneously by executing the number of instructions inversely proportional to the frequency.
JP 2005-122375 A JP 2007-141200 A Japanese Patent No. 2774770 Japanese Patent Laid-Open No. 10-198578 JP-A-4-114241 JP 2006-53835 A

  However, a RISC (Reduced Instruction Set Computer) processor has a pipeline structure such as a delay branch and a delay load, and this delay branch and delay load are executed in steps because the destination register update is delayed by one cycle or more. If the instruction is an instruction with a delayed branch or delayed load, there is a problem that the value of the register is not updated according to the program.

  The above problem will be described in detail with reference to FIGS. 7 to 9 show the pipeline flow of the most typical processor. That is, it is composed of five stages of instruction fetch (Instruction Fetch), instruction decode (Instruction Decode) and register read (Register Read), operation (Execute), memory access (Memory Access), and register write (Write Back).

In the processor having the pipeline of FIGS. 7 to 9, for example, consider a case where there are three consecutive instruction sequences as follows.
Instruction 1: LD [add], R0 (load data from memory address add and store in R0 register)
Instruction 2: ADD R0, R1, R2 (store the sum of the R0 and R1 registers in the R2 register)
Instruction 3: ADD R0, R3, R4 (the sum of the R0 and R3 registers is stored in the R4 register)

  The above-described instruction sequence is executed as shown in FIG. 7, but since the value is stored in the R0 register by the instruction 1, the R2 register is read by the instruction 2 and the instruction 3. A pipeline failure called a data hazard occurs. The instruction 3 responds by opening a bypass path called Forwarding that directly supplies the value read from the memory to the ALU. However, since the instruction 2 is not in time, the value before the update is calculated as the value of the R0 register. . That is, it can be said that the instruction 1 (LD instruction) is an instruction in which the update of the destination register has a delay of one cycle. In the RISC processor, in order to improve the operation speed, this situation is left to the scheduling of a program, and it is not solved by hardware. This is called lazy loading. In other words, in this case, the programmer is creating a program in the expectation that the instruction 2 performs an operation using the value of the R0 register before being updated by the instruction 1.

  Here, the case where the instruction 1 is executed in steps will be described. Step execution is realized by saving the instruction (instruction 2) next to the target instruction (in this case, instruction 1) on the host computer of the debugging device and replacing it with a software break instruction (EBRK instruction). However, in the case of step execution, as shown in FIG. 8, instruction 1 is executed until the end of the pipeline and stops. Therefore, when the next instruction 2 is executed stepwise, the value of the R0 register is updated. It will not be possible to debug according to the program. Similarly, in the case of delayed branching, step execution is not performed according to the program.

  In order to avoid such a problem, a processor having only one CPU core in the chip does not replace instruction 2 with an EBRK instruction during step execution, but replaces instruction 3 with an EBRK instruction as shown in FIG. By replacing it, this problem is avoided.

  However, in a multiprocessor having a plurality of CPU cores in one chip, if each core takes this workaround independently, a CPU core executing an instruction including a delay load and a delay branch There was a problem that step execution could not be performed simultaneously with other CPU cores.

  The present invention aims to solve such problems.

  That is, the present invention relates to a multiprocessor capable of performing step execution in which each CPU core operates in synchronization with a program even when there are a plurality of CPU cores in one chip, and a debugging device for debugging the same. It is another object of the present invention to provide a debugging method for debugging the multiprocessor.

  According to the first aspect of the present invention, in a multiprocessor having a plurality of CPUs operating at the same frequency by transitioning from an execution state to a monitor state by a break instruction, monitoring that monitors instructions executed by each of the plurality of CPUs And when the monitoring means detects that all of the CPUs are executing instructions that can transition to the monitor state when the break instruction is input to the CPU, the CPUs And a transition means for transitioning to the monitor state.

  The invention described in claim 2 is the invention described in claim 1, wherein the transition means is included in the CPU.

  The invention described in claim 3 is characterized in that in the invention described in claim 1 or 2, it further comprises selection means for selecting a CPU that transitions to the monitor state from the plurality of CPUs. To do.

  According to a fourth aspect of the present invention, there is provided a debugging apparatus comprising: a multiprocessor having a plurality of CPUs that transition from an execution state to a monitor state by a break instruction and operating at the same frequency; and a debugging unit that debugs the multiprocessor. Monitoring means for monitoring instructions executed by each of the plurality of CPUs; and when the break instruction is input to the CPU, the monitoring means provides instructions that allow all of the CPUs to transition to a monitor state. And a transition unit configured to transition the plurality of CPUs to the monitor state when the execution is detected.

  According to a fifth aspect of the present invention, in a debugging method for debugging a multiprocessor having a plurality of CPUs operating at the same frequency by transitioning from an execution state to a monitoring state by a break instruction, each of the plurality of CPUs executes the debugging method. The instruction is monitored, and when the break instruction is input to the CPU, if it is detected that all the CPUs are executing an instruction that can transition to the monitor state, the plurality of CPUs are monitored. This is a debugging method characterized by transitioning to a state.

  According to the first aspect of the present invention, the monitoring unit monitors the instruction executed by each of the plurality of CPUs, and when the break instruction is input to the CPU, the monitoring unit sets all the CPUs to the monitor state. If it is detected that a transitionable instruction is being executed, multiple CPUs are transitioned to the monitor state, so that the instruction being stepped in the multiple CPUs is placed in the monitor state such as delayed branch or delayed load. If there is even one command that cannot be reproduced as programmed by shifting, all the CPUs are synchronized by executing the next command without shifting to the monitor state. Thus, it is possible to perform step execution that can reproduce the movement according to the program. In addition, since it is controlled by hardware, the processing load of the debugging host computer during step execution can be reduced.

  According to the second aspect of the present invention, since the transition means is included in the CPU, the wiring between the monitoring means and the transition means is shortened, which is advantageous when operating at high speed.

  According to the third aspect of the present invention, since there is a selection means for selecting a CPU that transitions to a monitor state from among a plurality of CPUs, it is possible to exclude an object having no dependency relationship with other CPUs. Thus, the number of instructions in one step when performing step execution can be reduced.

  According to the fourth aspect of the present invention, the monitoring unit monitors the instruction executed by each of the plurality of CPUs, and when the break instruction is input to the CPU, the monitoring unit sets all the CPUs to the monitor state. If it is detected that a transitionable instruction is being executed, multiple CPUs are transitioned to the monitor state, so that the instruction being stepped in the multiple CPUs is placed in the monitor state such as delayed branch or delayed load. If there is even one command that cannot be reproduced as programmed by shifting, all the CPUs are synchronized by executing the next command without shifting to the monitor state. Thus, it is possible to perform step execution that can reproduce the movement according to the program.

  According to the fifth aspect of the present invention, the instruction executed by each of the plurality of CPUs is monitored, and when a break instruction is input to the CPU, all the CPUs execute an instruction that can transit to the monitor state. If it is detected that a plurality of CPUs are in the monitor state, the instructions being executed in steps in the plurality of CPUs are shifted to the monitor state such as delayed branching and delay load, and the program is executed. If there is at least one command that cannot reproduce the movement of the CPU, the next command is executed without shifting to the monitor state, so that all CPUs shift to the monitor state synchronously. Therefore, it is possible to perform step execution that can reproduce the motion as programmed.

[First Embodiment]
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a multiprocessor according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a modification of the multiprocessor shown in FIG. FIG. 3 is an explanatory diagram showing an example of the chip layout of the multiprocessor shown in FIG.

  The multiprocessor 1 shown in FIG. 1 includes CPUs 2a, 2b, and 2c and a break generation device 3, and is configured by a one-chip LSI.

  The CPU (also referred to as CPU core, core CPU, or simply core) 2 a includes a decoder 21 and AND circuits 22 and 23. Although not shown, the CPU 2a includes a program RAM for storing programs, a data RAM for storing operation data, a program counter for holding program addresses, an instruction register for storing instructions read from the program RAM, an arithmetic circuit, and various registers. It also has. The CPUs 2b and 2c have the same configuration. The CPUs 2a, 2b and 2c operate with clocks having the same frequency.

  The decoder 21 serving as a monitoring unit is a decoder that decodes an instruction stored in the instruction register. In this embodiment, the monitor 21 outputs a monitor transition enable signal when the instruction can be changed to the monitor state. The monitor state is a state in which a transition is made from an execution state that is a state in which a program is being executed. In this state, debugging such as step execution of a program and reading of a data memory or the like can be performed. In addition, the instruction that can transit to the monitor state indicates an instruction other than an instruction accompanied by a delay load and a delay branch among instructions installed in the CPUs 2a, 2b, and 2c.

  The AND circuit 22 as a transition means takes the logical product of the monitor transition enable signals of the CPUs 2a, 2b, and 2c, and when all the monitor transition enable signals become active (for example, high level), an active level signal (for example, high level) Is output.

  The AND circuit 23 as a transition means takes a logical product of a hardware break signal output from a break generation device 3 to be described later and the output of the AND circuit 22, and outputs both when active (for example, high level). The monitor state transition signal is activated (for example, high level).

  The break generation device 3 generates and outputs a hardware break signal by a signal from the outside of the multiprocessor 1 or the like.

  Next, the step operation in the multiprocessor 1 shown in FIG. 1 will be described. In order to simplify the explanation, a case where the CPUs 2a and 2b are step-executed will be described. As an example, a case where the instruction 1 is step-executed by the following program will be considered.

CPU2a program instruction 1: LD [add], R0 (load data from memory address add and store in R0 register)
Instruction 2: ADD R0, R1, R2 (store the sum of the R0 and R1 registers in the R2 register)
Instruction 3: ADD R0, R3, R4 (the sum of the R0 and R3 registers is stored in the R4 register)
Command 4: NOP (do nothing)

CPU2b program instruction 1: LD [add], R0 (load data from memory address add and store in R0 register)
Instruction 2: LD [add], R1 (load data from memory address add and store in R1 register)
Instruction 3: ADD R1, R6, R7 (the sum of the R1 register and R6 register is stored in the R7 register)
Instruction 4: ADD R1, R9, R10 (store the sum of the R1 and R9 registers in the R10 register)

  First, when the instruction 1 is decoded by the decoder 21 of each CPU, the monitor transition enable signal is not activated because both the CPUs 2a and 2b are delayed load instructions. Next, when the instruction 2 is decoded by the decoder 21 of each CPU, since the CPU 2a is neither delayed load nor delayed branch, the monitor transition enable signal of the CPU 2a becomes active, but since the CPU 2b is a delay load instruction, the monitor transition enable signal of the CPU 2b Is not active. Therefore, the output of the AND circuit 22 is not active. When stepping instruction 1, the hardware break signal becomes active at the timing of instruction 2. When the next instruction 3 is decoded by the decoder 21 of each CPU, neither the CPU 2a nor the CPU 2b is delayed loading nor delayed branching, so that each monitor transition enable signal becomes active, the AND circuit 22 becomes active, and the hardware break signal Is active, the AND circuit 23 becomes active, and both the CPU 2a and CPU 2b break (stop) at the timing of the instruction 4.

  In this way, since both the CPU 2a and the CPU 2b execute the instructions 1 to 3 and transition to the monitor state, step execution can be performed according to the program.

  As in this embodiment, a signal for breaking the CPU is provided as hardware, and the transition from the execution state to the monitoring state by applying the signal to the processor is called a hardware break. The break signal corresponds to a break instruction in the claims.

  According to the present embodiment, in the multiprocessor 1 incorporating the CPU 2a, CPU 2b, and CPU 2c, in order to shift to the monitor state during the step operation, each instruction of the CPU 2a, CPU 2b, and CPU 2c is decoded by the decoder 21 to enter the monitor state. In the case of a transitionable instruction, a monitor transition enable signal is output, and when all CPUs output a monitor transition enable signal, each CPU is transitioned to the monitor state, so step execution that can reproduce the behavior as programmed Can do.

  In addition, since the transition to the monitor state is controlled by hardware in the multiprocessor 1, it is possible to reduce the processing load of the debugging host computer at the time of step execution. Furthermore, since a hardware break is used, the step execution can be speeded up because the operation of reading data from the program memory of each CPU and rewriting the program memory of each CPU becomes unnecessary.

  Note that the AND circuit 22 and the AND circuit 23 are not built in the CPUs 2a, 2b, and 2c, respectively, and as shown in FIG. 2b and 2c may be output.

  With this configuration, the break generation device 3 collectively performs logical product and generates monitor transition signals and outputs them to the CPUs 2a, 2b, and 2c, so that circuit changes to the CPUs 2a, 2b, and 2c are minimized. It ’s all you need.

  However, the configuration shown in FIG. 1 is more advantageous than the configuration shown in FIG. 2 because the wiring between each CPU and the AND circuit is shortened. In general, in the LSI chip layout, the CPUs 2a, 2b, and 2c are often arranged side by side as shown in FIG. On the other hand, a debug circuit such as the break generating device 3 is not likely to be related to normal operation or communicates with the outside, so it is highly likely that the debug circuit is arranged on the outer periphery away from the CPUs 2a, 2b, and 2c. In this case, the wiring between each CPU and the break generating device 3 becomes long, and in the configuration in which a signal is taken out from each CPU as shown in FIG. It is difficult to increase the speed. Therefore, the configuration shown in FIG. 1 is preferable when breaking each CPU with hardware.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. Note that the same parts as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted. FIG. 4 is a block diagram of a multiprocessor according to the second embodiment of the present invention.

  In the present embodiment, the break generation device 3 as selection means outputs a CPU 2a mask signal, a CPU 2b mask signal, and a CPU 2c mask signal in addition to the hardware break signal.

  Further, in the CPU 2a, the CPU 2b mask signal and the monitor transition enable signal output from the CPU 2b are ORed by the OR circuit 24 and input to the AND circuit 22, and the CPU 2c mask signal and the monitor transition enable signal output from the CPU 2c are ORed. A logical sum is taken by the circuit 25 and inputted to the AND circuit 22. In the CPU 2b, the CPU 2a mask signal and the monitor transition enable signal output by the CPU 2a are ORed by the OR circuit 24 and input to the AND circuit 22, and the CPU 2c mask signal and the monitor transition enable signal output by the CPU 2c are OR circuit 25. Is logically summed and input to the AND circuit 22. In the CPU 2c, the CPU 2a mask signal and the monitor transition enable signal output from the CPU 2a are ORed by the OR circuit 24 and input to the AND circuit 22, and the CPU 2b mask signal and the monitor transition enable signal output from the CPU 2b are OR circuit 25. Is logically summed and input to the AND circuit 22.

  By adopting such a configuration, it is possible to perform step execution by excluding CPUs that do not have to operate synchronously. For example, when excluding the CPU 2a, the CPU 2a mask signal is made active (high level). Then, since the input of the AND circuit 22 is always active (high level) by the OR circuit 24 in the CPUs 2b and 2c, the CPUs 2b and 2c can perform step execution regardless of the state of the CPU 2a. In other words, the CPU that changes to the monitor state is selected by the CPU 2a mask signal, the CPU 2b mask signal, and the CPU 2c mask signal output from the break generation device 3.

  According to the present embodiment, the break generation device 3 outputs a mask signal (CPU 2a mask signal, CPU 2b mask signal, CPU 2c mask signal) to each CPU, and each CPU receives a monitor transition enable signal from another CPU. Since it is configured to take the logical product of its own signal after taking the logical sum of the mask signal, it is possible to exclude those that do not depend on other CPUs, Even if an instruction that cannot be shifted to the monitor state is being executed, the monitor state can be set, and the number of instructions in one step when performing step execution is reduced as compared with the case where all CPUs execute step by step synchronously. be able to.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first and second embodiments described above are denoted by the same reference numerals and description thereof is omitted. FIG. 5 is a block diagram of a debugging device according to the third embodiment of the present invention. FIG. 6 is a flowchart showing the step execution operation of the debugging apparatus shown in FIG.

  The debugging device 10 shown in FIG. 5 includes a multiprocessor 1 ′ and a break generation device 3 ′.

  The multiprocessor 1 ′ includes CPUs 2a ′, 2b ′, and 2c ′. The CPUs 2a ′, 2b ′, and 2c ′ are a decoder 21, a program RAM (not shown) for storing a program, a data RAM for storing operation data, a program counter that holds a program address, and an instruction that stores an instruction read from the program RAM. The point that a register, an arithmetic circuit, and various registers are provided is the same as the CPUs 2a, 2b, and 2c of the first and second embodiments, except that the AND circuits 22 and 23 are deleted.

  Furthermore, in the first and second embodiments, the built-in break generation device 3 is deleted from the multiprocessor 1 ′, and the multiprocessor 1 ′ is provided outside the multiprocessor 1 ′ as a break generation device 3 ′. The break generation device as the monitoring means and the transition means may be constituted by, for example, a debugging computer or a workstation.

  Next, the operation when performing step execution in the debug device 10 having the above-described configuration will be described with reference to the flowchart of FIG. The flowchart shown in FIG. 6 is executed by the break execution device 3 ′.

  First, in step S1, an instruction to be inspected is set as an instruction at the program counter position of each CPU, and the process proceeds to step S2. In this step, the program of each CPU is read from the program memory to the break generation device 3 ', and the instruction to be executed in step is set in the program counter.

  Next, in step S2, the target instruction is checked in all the CPUs, and the process proceeds to step S3. In this step, it is checked whether or not the command is capable of transitioning to the monitor state.

  Next, in step S3, it is determined whether or not all CPUs can transition to the monitor state, and if transition is possible (in the case of YES), the process proceeds to step S5. Proceed to S4. That is, it is determined whether or not the instruction checked in step S2 can transition to the monitor state.

  Next, in step S4, since all the CPUs are not instructions that can make a transition to the monitor state, the target instruction is advanced to the next instruction and the process returns to step S2.

  Next, in step S5, since all the CPUs are instructions that can transition to the monitor state, the instruction next to the target instruction is saved and the process proceeds to step S6.

  Next, in step S6, the instruction next to the target instruction is corrected to a software break instruction (EBRK instruction), and the process proceeds to step S7. In this step, a software break instruction is substituted for the instruction saved in step S5.

  Next, in step S7, all the CPUs are set to the program execution state. In this step, the modified program is written in the program memory of each CPU and the program is executed. The executed program causes the decoder 21 to decode the EBRK instruction to output a monitor transition enable signal to stop the CPU, and then transitions to the monitor state to perform step execution.

  An operation example of the above-described flowchart will be described in the case where the instruction 1 is stepped by the program exemplified in the first embodiment. First, when each of the instructions 1 is inspected, both CPU 2a 'and CPU 2b' are skipped because they are delayed load instructions. Next, when each of the instructions 2 is inspected, the CPU 2a 'is neither a delay load nor a delay branch, but skips because the CPU 2b' is a delay load instruction. When each of the next instructions 3 is inspected, neither the CPU 2a 'nor the CPU 2b' is a delayed load or delayed branch, so the next instruction 4 is replaced with a software break instruction (EBRK instruction).

  As in this embodiment, replacing an instruction at a place where a break is desired with an EBRK instruction, leaving the transition to the monitor state to the instruction decoder of the processor and shifting to the monitor mode is called a software break, and this EBRK instruction This corresponds to the break instruction in the claims.

  According to the present embodiment, the debug device 10 reads the programs of the CPUs 2 a ′, 2 b ′, and 2 c ′ in the multiprocessor 1 ′ with the break generation device 3 ′ in order to transit to the monitor state during the step operation. The instruction to be executed is inspected, and if the instruction is not a delayed load or delayed branch instruction in all the CPUs, the next instruction is saved and replaced with a software break instruction. If there is at least one delayed load or delayed branch instruction, all CPUs skip the instruction and check the next instruction until the delay load and delayed branch instructions are not issued. Step execution that can reproduce the movement of the street can be performed.

  In addition, since step execution is performed by replacing the software break instruction with the break generation device 3 ', an additional circuit or the like is not required for the multiprocessor 1'.

  Further, in the third embodiment described above, it has been described that the instruction immediately after cannot be replaced with the EBRK instruction in the case of a delay load. If it is different from the source, there is no problem even if the immediately following instruction is replaced with the EBRK instruction. Therefore, if the determination is made considering not only the instruction to be inspected but also the immediately following instruction, the instruction at the time of step execution The number of executions can be reduced.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

1 is a block diagram of a multiprocessor according to a first embodiment of the present invention. FIG. FIG. 6 is a block diagram showing a modification of the multiprocessor shown in FIG. 1. FIG. 2 is an explanatory diagram showing an example of a chip layout of the multiprocessor shown in FIG. 1. It is a block diagram of the multiprocessor concerning the 2nd Embodiment of this invention. It is a block diagram of the debugging apparatus concerning the 3rd Embodiment of this invention. 6 is a flowchart showing a step execution operation of the debugging apparatus shown in FIG. 5. It is explanatory drawing which shows the example of the pipeline of a delay load instruction. It is explanatory drawing which shows the example of the pipeline at the time of making the delay load instruction execute step. It is explanatory drawing which shows the example of the pipeline of step execution except the problem at the time of a delay load instruction.

Explanation of symbols

1 Multiprocessor 2a, 2b, 2c CPU
21 Decoder (monitoring means)
22, 23 AND circuit (transition means)
24, 25 OR circuit (selection means)
3 Break generation device (selection means)
10 Debugging device (selection means)
1 'multiprocessor 2a', 2b ', 2c' CPU
3 'Break generation device (monitoring means, transition means)

Claims (5)

In a multiprocessor having a plurality of CPUs that transition from an execution state to a monitor state by a break instruction and operate at the same frequency,
Monitoring means for monitoring instructions executed by each of the plurality of CPUs;
When the break instruction is input to the CPU, if the monitoring unit detects that all the CPUs are executing an instruction that can transition to the monitor state, the plurality of CPUs are placed in the monitor state. Transition means for transitioning to
A multiprocessor characterized by comprising:   The multiprocessor according to claim 1, wherein the transition unit is included in the CPU.   The multiprocessor according to claim 1, further comprising a selection unit that selects a CPU that transitions to the monitor state from the plurality of CPUs. In a debugging device having a multiprocessor having a plurality of CPUs that transition from an execution state to a monitor state by a break instruction and operate at the same frequency, and debugging means for debugging the multiprocessor,
Monitoring means for monitoring instructions executed by each of the plurality of CPUs;
When the break instruction is input to the CPU, if the monitoring unit detects that all the CPUs are executing an instruction that can transition to the monitor state, the plurality of CPUs are placed in the monitor state. Transition means for transitioning to
A debugging device characterized by comprising: In a debugging method for debugging a multiprocessor having a plurality of CPUs operating at the same frequency by transitioning from an execution state to a monitor state by a break instruction,
An instruction executed by each of the plurality of CPUs is monitored, and when the break instruction is input to the CPU, it is detected that all the CPUs are executing an instruction that can transition to a monitor state. In this case, the debugging method is characterized by causing the plurality of CPUs to transition to the monitor state.

Images