JP2010028632A - Amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier which saves energy by preventing efficiency reduction during low output. <P>SOLUTION: The amplifier includes: a distributor 46 for distributing an input signal to a plurality of distribution signals and outputting them; at least two amplifying elements 41 to 44 for inputting the distribution signals, amplifying the signals with predetermined amplification factors and outputting the amplified signals, respectively; and a combiner 47 for receiving input of the respective outputs and combining the inputs into one output signal to obtain a predetermined signal power. Each of the amplifying elements includes an operation ON/OFF control terminal 49, wherein an operation ON/OFF control signal is generated so as to correspond to the amount of a distortion component that is generated in an amplification process of the amplifying element and by adjusting the number of amplifying elements to be operated, efficiency reduction while the predetermined power is small is suppressed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to the efficiency of an amplifier, and more particularly to an amplifier suitable for use in controlling a circuit having a multi-stage amplifier element.

  Since the input signal is a multi-carrier wideband signal, the amplifier provided in the base station apparatus of the cellular phone system may have a small or large number of appearances of the carrier, and the level of the multi-carrier combined input signal is the network line. It changes according to the usage situation. That is, when the channel access is small, the level of the combined signal is reduced, and when the channel access is large, the level of the combined input signal is increased. Furthermore, even if attention is paid to one carrier, the amount of power required in the area is controlled by other devices to match the amount of power, so that the power amount of the input signal is changed from small to large at any time. Or there is a change from large to small.

  As such an amplifying circuit system that amplifies an input signal having a wide bandwidth and a large level change so as to have high distortion, low distortion, and high output, there is a feedforward distortion compensation system shown in FIG.

  In this amplification circuit system, an input signal (waveform 1) is distributed by a coupler A, and is amplified to a specified output by a circuit of a route A including a main amplifier 4 (referring to an amplifier). A distortion component is generated in the amplified signal as shown by waveform 2. The other input signal distributed by the coupler A passes through the delay line 5 and the waveform 3 is output to the coupler B. The coupler B combines the input signals of the route A signal (waveform 2) and the route B signal (waveform 3) so as to have the same amplitude and opposite phase, and outputs a distortion component (waveform 4) to the route D. In the circuit of route D, the distortion component (waveform 4) extracted from the waveform 2 is input, and further, the distortion component (waveform 4) has the same amplitude and opposite phase as the distortion component of the main signal that is the waveform 2. The vector adjuster 7 and the error amplifier 8 are controlled to obtain a signal like the waveform 5. The main signal (waveform 2) delayed by the delay unit 9 of the route C and the waveform 5 which is the distortion component signal are synthesized by the coupler C (waveform 6), and the distortion component of the main signal is removed, and the waveform 7 The output signal with high output and low distortion shown in

  As shown in FIG. 11, the main amplifier 4 has a plurality of amplifying elements (for example, FET; Field Effect Transistor; electric field) in order to amplify an input signal having a wide band and a large level change to a high output signal. A parallel circuit is formed by effect transistors), and these outputs are combined into an output signal.

  When a plurality of FETs such as FET-1 to FET-N are used, the output per one can be set low, so that high output can be achieved by synthesis while satisfying the specifications of the distortion component included in the output. .

  In this way, the conventional amplifier in which a plurality of FETs are always operated in a fully operating state enables high output with a wide bandwidth and high input, but on the other hand, each FET even at low output with low input. There is also a demerit that the power consumption of the amplifier is large for the output and the efficiency is reduced.

  For example, in an amplifier that synthesizes N single FETs having a maximum output of A (W) and an idle current (standby power) of B (A), A (W / piece) × N (pieces) = AN (W ) And N times output is possible, but the standby power is also N times as B (A / piece) × N (pieces) = BN (A).

  However, even in an operation below the maximum output AN (W), the standby power becomes BN (A), and the efficiency decreases.

As a prior art of the present invention, there is a proposal of an amplifying apparatus that puts an amplifier into a sleep mode so as not to generate unnecessary power consumption. (For example, see Patent Document 1)
JP 2006-222828 A (FIG. 1)

In the prior art of FIG. 11, the same Idle current (standby power) BN (A) at high output and low output
Is consumed. The reduction in efficiency at the time of low output is a problem, and it is a problem to provide an amplifier that operates with appropriate values of the number of operating FETs, generated distortion, output, and efficiency.

  An object of the present invention is to provide an amplifier that solves the above-described problems of the prior art, prevents a reduction in efficiency at low output, and saves energy.

  In order to achieve this object, an amplifier according to the present invention distributes an input signal to a plurality of distribution signals and outputs them, and receives the distribution signals as input, amplifies them at a predetermined amplification degree, and outputs each of them. And at least two amplifying elements, a synthesizer that takes the respective outputs as inputs, synthesizes the inputs into one output signal, and obtains a predetermined signal power, and distortion that occurs during the amplification process of the amplifying elements And a control unit that generates a signal for controlling ON / OFF of the amplifying element corresponding to the component amount.

  According to the present invention, in an amplifier that synthesizes N single FETs having a maximum output of A (W) and an Idle current of B (A), when the output of the device is sufficiently low, the amplification factor of the amplifier is For example, since the FET can be covered by one operation and the rest can be stopped, the power consumption of the amplifier can be reduced to B (A), that is, 1 / N. In this way, an energy saving amplifier with reduced power consumption at the time of low output becomes possible.

  FIG. 1 shows a block diagram of a main amplifier according to an embodiment of the present invention, and the configuration thereof will be described.

  The main amplifier 40 has the following configuration. The input signal input from the terminal 45 is supplied to the distributor 46, and the N-distributed outputs here are FET-1 (41), FET-2 (42), and FET-3 (43) which are amplification elements, respectively. ) And FET-N (44), and the signal is amplified by a predetermined amplification degree.

  The outputs of the FET-1 (41) to the FET-N (44) are input to the combiner 47, and power is combined into one signal. An amplified signal a, which is an output signal obtained by combining the power in the combiner 47, is output from the terminal 48.

  Each of FET-1 (41) to FET-N (44) has a gate terminal, and an ON / OFF control signal is input to control operation / non-operation of the FET alone. Is called.

  The FET ON / OFF signal c, which is a control signal, is input to the terminal 49 and supplied to each gate terminal of the FET-1 (41) to FET-N (44), and the operation / non-operation control for each FET alone is controlled. Done.

  FIG. 2 shows an example of an output signal spectrum diagram of a single FET amplifying element of the present invention, and its properties will be described.

  The example of the output signal spectrum diagram of FIG. 2 (a) is an operation when the number of appearances of carriers decreases, that is, the FET is at a low output, and the spectrum shown (example: one carrier) is the original signal. Although it is a component and is not shown, the distortion component spectrum is small or minimal. Even if the output is low, a predetermined Idle current flows, so that the power efficiency of the FET is poor.

  The example of the output signal spectrum diagram of FIG. 2 (b) is when the number of appearances of carriers ceases, that is, the FET operates at a high output, and with the high power amplification, the original signal component spectrum (example: carrier 4). There is a spectrum of distortion components on both sides of the book. This distortion component is a component that cannot be ignored and is reduced by the vector cancellation operation of the distortion compensation circuit (details will be described later with reference to FIG. 4). Also at this time, a predetermined Idle current similar to that at the time of low output flows. Since the output is high, the power efficiency of the FET is good.

  FIG. 3 shows an example of a characteristic diagram of a single FET amplifying element of the present invention, and the characteristic will be described.

  The characteristic curve connected at the white square measurement points shows a change in the efficiency (%) with respect to the output value (dBm), and the characteristic curve connected at the black square measurement points shows the distortion amount with respect to the output value (dBm) ( The change in dBc) is shown.

  The distortion specification value is −40 dBc, and the maximum usable output (about 46 dBm) is obtained by the k point that is the intersection of the −40 dBc line and the distortion characteristic curve.

  Next, it can be seen that the efficiency is about 37% by the point p which is the intersection of the line of the maximum usable output (about 46 dBm) and the efficiency characteristic curve. Each value obtained by the k point and the p point indicates an operating condition in which the maximum usable power, the best efficiency, and the distortion can be compensated.

  Since this efficiency characteristic curve is proportional to the output, it indicates that the efficiency decreases as the output decreases.

  That is, since the FET alone needs to be used within a range that does not exceed the upper limit value of the distortion component, it is ideal to use the FET with the maximum output satisfying the specification of the distortion component. In this case, the distortion component is satisfied (distortion compensation is possible), and the efficiency is good.

  However, since the input signal level changes, as a result of amplification, there is a state of low output to high output, and even a single FET has a state of low efficiency to high efficiency. If the present invention is applied, the efficiency is improved when the combined output is low by the FET operation number control described below.

  Although the characteristic diagram example of the FET amplifying element alone has been described above, this characteristic can be explained as the same characteristic for the main amplifier and the entire amplifier (device).

  In addition, the distortion amount as an apparatus needs to be less than (−63 dBc). Since the amount of distortion compensation by the error amplifier circuit is 30 dB, the amount of distortion allowed in the main amplifier circuit needs to be equal to or less than (−33 dBc), which is the difference between the values. For example, the output distortion of the main amplifier circuit When the amount is (−31 dBc), a distortion compensation amount of 30 dB is added to the amount to be (−61 dBc). As a result, the device becomes out of specification.

  FIG. 4 shows a block diagram of an amplifying apparatus in which the amplifier of the present invention is used, and the configuration thereof will be described. In addition, the same code | symbol as FIG. 10 shows the same or equivalent.

  The basic operation of the feedforward type distortion compensation circuit has been described in the section of the prior art, and is omitted here.

  Hereinafter, a description will be given of the control operation of the main amplifier 40 according to the present invention with variable number of FETs. The distortion component b (waveform 4) generated by the main amplifier 40 is input to the error amplifier 8 after vector adjustment by the vector adjuster 7. Since the level of the distortion component b (waveform 4) corresponds to the operation state of the FET power amplification of the main amplifier 40, the level of the distortion component b can be used for controlling the number of operating FETs.

  The distortion component b is branched by the coupler D (12), and the branched distortion component b is input to the detection circuit 13, where the level of the distortion component b is converted into a change amount of the DC voltage and input to the control unit 14. Is done.

  The control unit 14 performs signal processing on the distortion component b converted into the change amount of the DC voltage, and activates / deactivates the FET-1 (41) to FET-N (44) included in the main amplifier 40. FET / ON / OFF signal c for controlling the above is generated and output to the main amplifier 40.

  When the distortion component b (corresponding to the input of the error amplifier 8) is a small value, since the distortion generated in the main amplifier 40 is also small, the output of each FET of the main amplifier is small, and the efficiency of each FET is low (bad). ).

  On the other hand, when the distortion component b (corresponding to the input of the error amplifier 8) is a large value, the distortion amount included in the amplified signal a that is the output of the main amplifier 40 also increases. The output is large, the amount of distortion components generated in each FET is large, and the efficiency of each FET is high. Therefore, the efficiency of the main amplifier 40 is also high (good). Note that the distortion component at this time can be reduced by the operation of the distortion compensation circuit.

  The amplifier according to the present invention uses the control information obtained from the magnitude of the distortion component to control operation / non-operation of a plurality of FETs, and is provided in the main amplifier 40 so as to obtain the best efficiency in power at that time. In addition, the number of operating FETs can be optimized.

  The operation progress of one embodiment of the present invention will be described with reference to FIGS.

  In the present embodiment, as shown in FIG. 5, first, the control unit 14 performs FET · ON / ON input to all the FETs FET- 1 (41) to FET-N (44) included in the main amplifier 40. The operation starts when the control signal of the OFF signal c is turned on and all the FETs are put into operation.

  FIG. 5 is an excerpt block diagram showing the main amplifier 40, the coupler B (6), the coupler D (12), and the detector circuit 13 extracted from the feedforward circuit configuration shown in FIG.

  In the internal configuration of the amplifier 40, the description of the distributor 46, the combiner 47, and the terminal 48 shown in FIG. 1 is omitted.

  The amplified signal a, which is the output of the main amplifier 40, is in an operation state where the output is “small”, and the output of the synthetic FET has distortion components on both sides of the original signal component d as shown by the spectrum waveform of waveform 2. It does not appear, that is, as shown by the distortion component b (waveform 4), the detection circuit 13 hardly detects the level of the distortion component b.

  This means that the output of each FET is controlled to the “small” operating state, and the combined output is also in the “small” operating state.

  Therefore, the level of the distortion component b is used in the signal processing of the control unit 14 as being minute or none. The operation of the amplifier 40 controlled by the control unit 14 will be described later with reference to FIG.

  Looking at the operation of the amplifier 40 in FIG. 5, if the output of each FET of FET-1 (41) to FET-N (44) is A (W) and the Idle current is B (A), N FETs. Since they are combined, the combined output is NA (W), and the idle current is NB (A).

  Also, looking at the operating status of each FET, each FET is operating at a small output while consuming Idle current, and the distortion component is minute, but the efficiency is poor. Accordingly, a predetermined output is similarly obtained after the synthesis, but the distortion component is very small and can be said to be an excessive specification.

  Even if the output of the main amplifier 40 is sufficiently small, if all FETs are operating, the current consumption of each FET is occupied by the Idle current, so the current consumption in the main amplifier 40 is NB (A).

  In such a case, for any number of FETs, if the gate voltage is turned off, the number of operating FETs is reduced, the amplification capability of the remaining FETs is increased, and a predetermined output can be obtained. Good. By doing so, it is possible to relatively reduce the current consumption of the main amplifier.

  Next, the operation of FIG. 6 will be described. The operation of FIG. 6 is to reduce the operation of the FET to one by the control of the control unit 14 and improve the power consumption efficiency of the amplifier 40.

  When the main amplifier 40 has a small output, the detection circuit 13 detects that the distortion component is minute or absent, and based on this, the control unit 14 performs signal processing for reducing the number of operating FETs. .

  In FIG. 6, it is determined by the control unit 14 that the signal power for NA (W), which is a small power, can be covered by the maximum usable output for one FET and can reach a predetermined signal power, and FET-1 (41 ) Remains in the operating state (ON), and FET-2 (42) to FET-N (44) are turned OFF and become inoperative. At this time, it goes without saying that the input signal is routed to the non-operating FET and distribution loss does not occur.

  As a result, the amplified signal a, which is the output of the main amplifier 40, remains in the “small” operating range, and is set to the maximum usable output for one FET as shown in waveform 2 of FIG. Therefore, distortion components appear on both sides of the original signal component d, that is, as shown by the distortion component b (waveform 4), the detection circuit 13 generates the distortion component b as a small level that cannot be ignored. Is done. If the level of the distortion component b is about this level, it is reduced by the distortion compensation circuit.

  Here, although the output of the main amplifier 40 is a predetermined output in a sufficiently small range, the current consumption for one FET is about the same as the Idle current, so in FIG. Compared to when the FET is operating, 1 / N, that is, B (A) is sufficient.

  As a further embodiment of the present invention, FIG. 7 shows a block diagram at the time of 1FET operation, and FIG. 8 shows a block diagram when the operation is changed at the time of 2FET operation. Each operation will be described.

  FIG. 7 is an operation example when the output of the main amplifier 40 increases and the distortion component of the FET increases. This state may be considered as a state in which the level of the input signal changes in the increasing direction with respect to the operating state of the maximum usable output shown in FIG.

  Although the input signal increases, the amplified signal a, which is the output of the main amplifier 40, is still in the “small” operating range.

  This is a state in which large distortion components appear on both sides of the original signal component d as shown in waveform 2 in FIG. That is, as indicated by the distortion component b (waveform 4), the detection circuit 13 detects a large level of the distortion component b. With such a large distortion component b, it is difficult to reduce distortion in the distortion compensation circuit. If this is the case, the distortion component will be out of spec. (Corresponds to point n in Fig. 3)

  Therefore, based on the level of the detected distortion component b, looking at the operating status of each FET, there is a sufficient number of non-operating FETs, the number of FETs is increased, and a predetermined output is obtained after synthesis. The control unit 14 determines that there is a margin.

  FIG. 8 shows that the FET cannot be used with an output that causes the distortion component to be out of spec. Therefore, when the distortion component b increases, the number of operation of the FET is increased, and the output signal power value is a predetermined power value. The control unit 14 may control so that the distortion component is kept within the standard.

  In this case, an arbitrary number of FET gate voltages are controlled to be ON to increase the number of operating FETs. The combined signal power becomes a predetermined output value due to the characteristics of the amplification capability of the active FET including the increased FET and the distribution loss of the input signal. By doing so, an increase in current consumption of the main amplifier 40 can be minimized.

  Therefore, the detection circuit 13 detects that the distortion component at the time of 1FET operation with increased input and small output is large, and based on this, the control unit 14 needs to increase the number of operating FETs by one. Is determined.

  In FIG. 8, in order to obtain signal power corresponding to NA (W) with small power, it is appropriate to set a predetermined output (2 × A (W) capacity) by using two FETs as appropriate. The FET-1 (41) and the FET-2 (42) are turned on to make two operating states. Note that FET-3 (43) to FET-N (44) remain OFF and become non-operating. At this time, it goes without saying that the input signal is routed to the non-operating FET and distribution loss does not occur.

  As a result, the predetermined amplification degree per FET is reduced, but the signal amount per FET is reduced due to the distribution loss of the input to the two active FETs, and the distortion component generated is considerably reduced. Is expected.

  As a result, the input signal increases, but the amplified signal a, which is the output of the main amplifier 40, falls within the operating range where the output is “small”, and on both sides of the original signal component d as shown in the waveform 2. The number of FETs is controlled so that an appropriate amount of distortion component remains. That is, as shown by the distortion component b (waveform 4) in FIG. 8, the detection circuit 13 detects the level of the distortion component b in an appropriate amount. With such an appropriate amount of distortion component b, distortion can be reduced on the distortion compensation circuit side. In this state, the distortion component does not spec out.

  Therefore, the output of the main amplifier 40 is a predetermined output in a sufficiently small range even after the synthesis by operating two FETs, and an appropriate amount of distortion component remains, but the consumption current for the two FETs is the Idle current. Therefore, the current consumption in the main amplifier 40 in FIG. 8 is 2 / N, that is, 2B (A) compared to when all FETs are operating.

  In this way, if the amount of distortion further increases, the number of active FETs is further increased, and the number of FETs is controlled so that the distortion compensation circuit functions sufficiently.

  FIG. 9 shows an operation state table in which the number of FETs increases and decreases and a distortion amount determination table for 2 FET operation as an embodiment of the present invention, and the comparison of the contents will be described.

  The upper column of FIG. 9A shows the next operation state. The input signal level to the main amplifier is steady. That is, this is an operation state in which the distortion compensation circuit can normally reduce distortion. At this time, the output of the main amplifier (waveform 2, amplified signal a) is an amplified signal having a predetermined power including a predetermined appropriate amount of distortion component. The detected distortion component (waveform 4, distortion component b) is also an appropriate amount (threshold value: greater than 2Y (W) to less than 2X (W)). The number of operating FETs of the main amplifier is two as an example. If the state of the detected distortion component amount (threshold value: greater than 2Y (W) to less than 2X (W)) is continued, the number of FET operations of the main amplifier remains two, and the idle current of the main amplifier is also 2B. / N (A) is continued.

  The column in FIG. 9A shows the next operation state. The input signal level to the main amplifier is in a reduced state as compared to the above-mentioned level steady description column. At this time, the output of the main amplifier (waveform 2, amplified signal a) is an amplified signal having a predetermined power including a predetermined minute distortion component. The detected distortion component (waveform 4, distortion component b) is a very small amount (threshold value: 2Y (W) or less). Based on this trace distortion component, the number of FET operations of the main amplifier is determined to have a margin in the above-mentioned two operation, and is reduced from two to one as an example. After the reduction, the distortion component amount (threshold: greater than 2Y (W) to less than 2X (W)) is changed to an appropriate amount. Furthermore, the idle current of the main amplifier is reduced to 1 B / N (A).

  The lower column of FIG. 9A shows the next operation state. The input signal level to the main amplifier is in an increased state compared to the level steady state described in the upper column. At this time, the output of the main amplifier (waveform 2, amplified signal a) becomes an amplified signal having a predetermined power including an excessive amount of distortion components. The detected distortion component (waveform 4, distortion component b) increases from (threshold value: more than 2Y (W) to less than 2X (W)) and becomes an excessive amount (threshold value: 2X (W) or more). The number of operation of the FET of the main amplifier is determined that the distortion compensation cannot be normally performed when the two are operated, and increases from two to three as an example. After the increase, the distortion component amount (threshold value: greater than 2Y (W) to less than 2X (W)) is changed to an appropriate amount. Furthermore, although the idle current of the main amplifier increases to 3B / N (A), it is in a reduced state of (N-3) B / N (A) compared to the operation of all FETs.

  In the present invention, the amount of distortion component generated in the amplification process of the amplifier is detected, and based on this, the operating condition of the FET of the amplifier is examined and the number thereof is adjusted. In order to perform this control, the correlation between the amount of detected distortion component and the number of operating FETs is measured in advance, and this is stored in the control unit memory and stored in the memory of the control unit for amplification operation. Read out and use when controlling.

  Corresponding to the number of operating FETs, upper and lower thresholds are set for the strain component amount. When the upper limit is approached, the FET operating number is increased, and when the lower limit is approached, the FET operating number is decreased. (See FIG. 9B).

  This correlation table may be provided with a learning function so as to adapt to the changing elements in operation, and may be constantly updated to a new correlation table.

  The FET to be operated may be appropriately selected in consideration of usage conditions such as the operation time of each FET.

  In this way, the amplifier efficiency at the time of low output is improved by adjusting the number of operating FETs of the main amplifier by changing the distortion component amount.

  The present invention is applied to a radio communication system used for mobile communication, and can be used as an example of a base station apparatus of a mobile phone system.

It is a block diagram of the main amplifier of this invention. It is an output signal spectrum figure of FET amplification element of the present invention. It is a characteristic view of the FET amplifying element of the present invention. It is a block diagram of the amplification device of the present invention. It is a block diagram at the time of all FET operation | movement of this invention. It is a block diagram at the time of 1FET operation | movement of this invention. It is a block diagram at the time of 1FET operation | movement of this invention. It is a block diagram at the time of 2FET operation | movement of this invention. It is the state table | surface and distortion amount determination table | surface at the time of FET increase / decrease operation | movement of this invention. It is a block diagram of the amplifier of a prior art. It is a block diagram of the main amplifier of a prior art.

Explanation of symbols

1, 11, 45, 48, 49 ... terminals 2, 6, 10, 12 ... coupler 3, 7 ... vector adjuster 5, 9 ... delay line, delay unit 4, 40 ... Main amplifier 8 ... Error amplifier 13 ... Detection circuit 14 ... Control unit 41-44 ... FET-1-FET-N
46 ... distributor 47 ... combiner a ... amplified signal b ... distortion component c ... FET ON / OFF signal

Claims (1)

A distributor that distributes an input signal to a plurality of distribution signals and outputs it;
At least two amplifying elements that receive the distribution signal as input, amplify the signal at a predetermined amplification level, and output the respective signals;
A synthesizer that takes each of the outputs as input, combines the inputs into one output signal, and obtains a predetermined signal power;
A control unit for generating a signal for controlling ON / OFF of the amplifying element in accordance with a distortion component amount generated in an amplifying process of the amplifying element;
An amplifier comprising:

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