JP2010026674A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a cycle required for saving and restoring data and reduce throughput deterioration during operation even when a CPU is frequently powered on and off. <P>SOLUTION: Data stored in an address specified by a stack pointer SP and its consecutive address is retrieved from RAM 2 consisting of MRAM, and an instruction code stored in an address specified by a program counter PC is retrieved from ROM 3 and decoded. An ALU-M controlled by the instruction code performs an operation on data retrieved from the RAM 2 and stores the operation result WD in the same address in the RAM 2 as specified by the stack pointer SP. Before being powered off, a CPU 1 stores and save values of the stack pointer SP and program counter PC in a predetermined address in the RAM 2. Upon being powered on, the CPU 1 retrieves the saved values from the RAM 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a non-volatile memory with no rewrite limit.

  A conventional microcomputer has a configuration as shown in FIG. 4 when simply illustrated, and the CPU includes a plurality of general-purpose registers R0 to R6. The ROM stores an instruction code Code, and the instruction code Code is read from an address designated by the program counter PC. Instruction decoder Code dec. Decodes the instruction code Code read from the ROM and outputs a decoded signal C0 [x]. A circuit such as an ALU (arithmetic arithmetic unit) is controlled by the decoded signal C0 [x], and the general-purpose registers R0 to R6 temporarily store the results of operations executed by the circuit such as ALU.

  In addition, in a conventional microcomputer, a nonvolatile memory such as an MRAM (see, for example, Non-Patent Document 1) such as an MRAM (for example, see Non-Patent Document 1) is used as a RAM and a ROM, and the microcomputer consumes less power. In some cases, the CPU power can be turned off when no operation is required.

2004 Symposium on VLSI Circuits Digest of Technical Papers p.450-453, A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture

  Use a CPU with multiple general-purpose registers, such as the conventional example, and a non-volatile memory with no limit on the number of rewrites, such as MRAM, to turn off the CPU power and reduce power consumption when no operation is required. In this case, it is necessary to save the data temporarily stored in the general-purpose register to the nonvolatile memory unit. For this reason, when the CPU power is frequently turned on / off, a problem arises in that the processing capability of the operation to be originally performed decreases due to the cycle required for saving and restoring data.

  The present invention has been made on the basis of recognition of such problems, and its purpose is to provide a cycle required for saving and restoring data even when the CPU power supply is frequently turned on and off. It is an object of the present invention to provide a semiconductor integrated circuit that has a small reduction in processing capacity during operation.

  The subject of the present invention is applied to a microcomputer using a nonvolatile memory in which a data storage area is not limited in the number of rewrites such as MRAM. The ALU-M in the CPU of the microcomputer performs arithmetic processing on the data specified in the stack pointer and the data in the non-volatile memory stored at consecutive addresses, and the calculation result is specified by the stack pointer. Stored at the same address. When the CPU power is turned off, the CPU saves each value of the stack pointer and the program counter to a predetermined address of the nonvolatile memory and then turns off the CPU power. When restarting the process by turning on the CPU power, the CPU reads each value of the stack pointer and the program counter saved at a predetermined address in the nonvolatile memory from the nonvolatile memory, and reads each value from the stack pointer and the program. Load into the counter. As a result, the stack pointer designates the address of the data stored at the address designated by the stack pointer at the cycle when the CPU power is turned off, and the CPU stores the CPU stored at the address. The data when the power is turned off is read from the nonvolatile memory and the arithmetic processing is continued.

  According to the subject matter of the present invention, there is little data to be saved in the nonvolatile memory when the CPU power is turned on / off, and the data is saved and restored even when the CPU power is frequently turned on / off. Therefore, it is possible to reduce the number of cycles required for the operation, and accordingly, it is possible to reduce a decrease in processing capacity during operation.

  Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a circuit configuration of a microcomputer equipped with a semiconductor integrated circuit according to the present embodiment. In the present embodiment, the RAM 2 is composed of MRAM (Data), and the ROM 3 is also composed of MRAM (Code).

  As in the conventional example, the instruction code Q (A + 0) stored at the address A designated by the program counter PC is read from the ROM 3. Similarly to the conventional example, each instruction code Q (A + x) stored at a predetermined number of addresses continuous with the address A is also read from the ROM 3 as needed. In the present embodiment, as an example, it is assumed that a maximum of four instructions Q (A + 0) to Q (A + 3) are simultaneously read from the ROM 3 according to the designation of the address A by the program counter PC. Yes. Similarly to the conventional example, the read instruction code Q (A + x) (x: 0 to 3) is stored in the instruction decoder Code dec. Decoded with Then, a circuit such as an ALU is controlled by the decoded signals C0 [x] to C3 [x], and the instruction code Q (A + x) is executed.

  The data stored in the address A specified by the value of the signal output from the stack pointer SP and a predetermined number of addresses (here, three consecutive addresses) following the address A are stored in the data output terminal Q of the RAM 2. Read from (A + 0) to Q (A + 3). On the other hand, data WD indicating the result calculated by the arithmetic operation unit ALU-M is written into the RAM 2 from the write terminal D (A + 0) of the RAM 2 via the switch shown in FIG.

  The arithmetic operation unit ALU-M controlled in accordance with the instruction code performs a predetermined operation on the data read from the RAM 2. The calculation result WD is input to the write terminal D (A + 0) of the RAM 2 and is written as data at the address A of the RAM 2 specified by the stack pointer SP.

  As shown in FIG. 2, here, the arithmetic operation unit ALU-M is composed of three arithmetic operation circuits ALU (indicated by ●, black square, and ▲), and a maximum of three operations. Can be executed in one cycle. For the sake of simplification, here, the operations that can be executed by the arithmetic operation circuit ALU are the four arithmetic operations (addition +, subtraction-, integration ×, division ÷) of binary operations. As shown in the example in Table 1,

Arithmetic expressions for up to four values of data A, B, C, and D output from the data output terminals Q (A + 0) to Q (A + 3) of the RAM 2 and input to the arithmetic operation unit ALU-M are in reverse Polish notation. Are classified into 8 cases. According to these eight cases, the switches SW1 to SW5 and the arithmetic operation circuit ALU (●, black square, ▲) in FIG. 2 are controlled as shown in Table 1.

  Hereinafter, the operation of the execution cycle will be sequentially described with reference to the timing chart of FIG.

  At time t1 in FIG. 3, it is assumed that the values of the program counter PC and the stack pointer SP in the cycle n are determined, and the respective values are input to the ROM 3 and RAM 2.

  At time t2 in FIG. 3, the CPU 1 sets the read enable signal OE for the ROM 3 and RAM 2 to be enabled, and the instruction code stored at the respective addresses of the ROM 3 and RAM 2 specified by the program counter PC and the stack pointer SP and Read data.

  At time t3 after the read access time elapses, the instruction code and data are read from the terminals Q (A + 0) to Q (A + 3) of the ROM 3 and RAM 2, respectively. Then, according to the read instruction code, the arithmetic operation unit ALU-M performs a predetermined operation on the read data, and after the operation delay time in the arithmetic operation unit ALU-M has elapsed. At time t4, the calculation result is output from the output terminal WD. As described above, this calculation result is also referred to as WD.

  At time t5 in FIG. 3, the CPU 1 enables the write enable signal WE of the RAM 2 and writes the calculation result WD into the RAM 2. At this time, the address of the RAM 2 to be written is the address A specified by the stack pointer SP as described above.

  Finally, at time t6, the CPU 1 updates the values of the program counter PC and the stack pointer SP to the values of the next cycle (n + 1). In this case, the value of the stack pointer SP is generally decremented when the operation target data is “loaded on the stack”, and is incremented by (the number of operation target data minus 1) after the operation is executed.

  When the operation of the CPU 1 is not necessary due to detection of an on / off command of a CPU power supply (not shown) by an external circuit (not shown), the CPU 1 receives the detection result and reduces the power consumption. In order to reduce the power, the CPU power is turned off. At that time, in order to restart the program, the CPU 1 stores the value of the program counter PC at a predetermined address of the RAM 2 and also stores the value of the stack pointer SP at the predetermined address of the RAM 2. After that, the CPU 1 is turned off.

  When the external circuit detects the CPU power-on command and receives the detection result, and the CPU 1 turns on the power and resumes processing, the CPU 1 is stored at the predetermined RAM 2 address. The value of the stack pointer SP is read and loaded onto the stack pointer SP. At the same time, the CPU 1 reads the value of the program counter PC stored at the same predetermined address of the RAM 2 and loads it into the program counter PC.

  As described above, a non-volatile memory with no limit on the number of rewrites is used in the data storage area, and a predetermined operation is performed on the data stored in the RAM address A specified by the stack pointer SP and a predetermined number of addresses consecutive thereto. And the operation result is stored at the same address A designated by the stack pointer SP. Therefore, when the CPU power is turned on / off, it is only necessary to save the values of the stack pointer SP and the program counter PC in the nonvolatile memory, and when the CPU power is frequently turned on / off. However, the number of cycles required for saving and restoring data is small, and the processing capacity during operation is hardly reduced.

  In addition, since the memory for storing data is mainly controlled (addressed) only by the stack pointer SP, there is no need to distribute the memory arrangement, and the magnetic field for writing can be used as a non-volatile memory with no limit on the number of rewrites. An MRAM that requires a current line for generation and a special readout circuit can be used.

(Appendix)
While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

  The present invention is suitable for application to, for example, a microcomputer provided with a non-volatile memory with no rewrite limit.

FIG. 2 is a block diagram illustrating a circuit configuration of a microcomputer that is an example of the first embodiment. It is a block diagram which shows the structure of the arithmetic operation apparatus in CPU of FIG. It is a timing chart which shows the operation | movement of the execution cycle of the microcomputer of FIG. It is a block diagram which shows the circuit structure of the microcomputer based on a prior art.

Explanation of symbols

  SP stack pointer, PC program counter, ALU-M arithmetic operation unit, 1 CPU, 2 RAM, 3 ROM.

Claims (1)

A semiconductor integrated circuit using a non-volatile memory with no limit on the number of rewrites as a calculation data storage area,
A CPU that performs a predetermined operation on a plurality of data in the nonvolatile memory stored at an address specified by the stack pointer and a predetermined number of addresses continuous to the address;
The CPU stores the calculation result of the predetermined calculation at the address specified by the stack pointer, and when the CPU is turned off, first, the stack pointer in the cycle when the CPU is turned off is stored. After saving the value to a predetermined address in the nonvolatile memory, the CPU is powered off.
Semiconductor integrated circuit.

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