JP2010026571A - Image processor and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor and an image processing method for shortening the processing time of generation of a composite image without deteriorating precision of superposition, in image processing for generating a composite image from small images such as partial images. <P>SOLUTION: The superposition lines of the input small images of one frame are greatly thinned out and designated according as they are separated from predicted superposition pixel lines predicted by a prediction means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing apparatus and an image processing method, and more particularly to an image processing apparatus and an image processing method for generating a composite image by superimposing partial images having overlapping portions.

  In a fingerprint authentication device for authenticating a fingerprint of a finger, a sweep type sensor is used for reading the fingerprint, and a small image (that is, a partial image of the fingerprint ( Frames)) are output sequentially. In the fingerprint authentication device, the optimum overlapping pixel line (synthesized pixel line) of the partial image of the fingerprint sequentially output from the sweep type sensor is searched for, and the part is detected by the optimum overlapping pixel line (synthesized pixel line). An image processing apparatus for constructing a fingerprint image by superimposing images is provided. The constructed fingerprint image is stored as a registered image at the time of registration and is stored as an authentication image at the time of authentication, and it is determined whether or not the authentication image and the registered image are the same. Patent Document 1 describes a specific example of a fingerprint authentication device including such an image processing device. Hereinafter, an image processing device described in Patent Document 1 and a fingerprint authentication device including the image processing device will be described with reference to FIGS.

  FIG. 1 is a configuration diagram of a fingerprint authentication device 100 described in Patent Document 1. The fingerprint recognition device 100 includes a sensor 101, an image processing device 102, and an authentication circuit 103. The sensor 101 has an elongated reading unit (not shown) having a vertical width of about 0.5 to 5 mm, and supplies the partial image of the fingerprint read by the reading unit to the image processing apparatus 102 as data. When the composite image of the entire fingerprint is accumulated in the image processing apparatus 102, the authentication circuit 103 performs fingerprint authentication using the composite image of the entire fingerprint.

  The image processing apparatus 102 includes a partial image memory 11, a composite pixel line calculation circuit 12, and a composite image memory 13. The partial image memory 11 is connected to the sensor 101 and accumulates partial images of fingerprints periodically supplied from the sensor 101. The partial image memory 11 is connected to a composite pixel line calculation circuit 12 and a composite image memory 13. The composite pixel line calculation circuit 12 compares the current frame supplied from the partial image memory 11 with the previous frame supplied temporally before the current frame, i.e., the previous frame, for each pixel. The pixel line that starts overlapping with the previous frame in the current frame when is overlapped most similarly is calculated as a composite pixel line. Further, an authentication circuit 103 is connected to the composite image memory 13.

  The composite pixel line calculation circuit 12 includes an overlay circuit 12a, a pixel selection circuit 12b, a pixel comparison circuit 12c, and a pixel line determination circuit 12d. The superposition circuit 12b superimposes the previous frame one frame before the input image and the current frame, which is the current frame, in the vertical direction to extract an image of the overlapped portion. The pixel selection circuit 12b is connected to the superposition circuit 12a and selects a pixel for which a luminance level difference between the previous frame and the current frame is to be taken. The pixel comparison circuit 12c is connected to the superposition circuit 12a and the pixel selection circuit 12b. The pixel comparison circuit 12c calculates the luminance level difference of the pixel selected by the pixel selection circuit 12b, and the luminance level of the pixel in the case where the accumulated value and the superposition pixel line are different. Compare the cumulative value of the differences. The pixel line determination circuit 12d is connected to the pixel comparison circuit 12c, and determines the overlapping pixel line that minimizes the cumulative value of the difference based on the result of the pixel comparison circuit 12c.

  FIG. 2 is a processing flowchart showing the operation of the composite pixel line calculation circuit 12 of FIG. Here, the superimposition processing in the vertical direction of the frame will be described, but the same processing is also performed in the horizontal direction.

  When the process is started, the overlapping pixel line A between the previous frame and the current frame is set to zero (A = 0) (step S1). When the overlapping pixel line A = 0, the previous frame and the current frame are completely overlapped. In addition, when the value of the overlap pixel line A is incremented by 1 (A = A + 1), the overlap pixel line A of the previous frame is moved downward by one pixel line with respect to the current frame. Indicates. When the values are further added, a state in which only one pixel line described above is moved downward is shown as being further moved downward. When the overlapping pixel line A is determined (step S2), the composite pixel line calculation circuit 12 determines whether or not it is a pixel of the current frame for which a luminance level difference should be calculated from the previous frame (step S3). . This is a determination for calculating the pixel brightness level difference for only the pixels in the overlapping portion between the current frame and the previous frame determined in the pixel order of the current frame and determined by the overlapping pixel line A. If it is a pixel that calculates the difference in luminance level, the difference in luminance level is obtained (step S4), and if it is not a pixel that calculates the difference in luminance level, the process proceeds to step S6.

  The composite pixel line calculation circuit 12 adds the obtained luminance level difference to the total (step S5), and further determines whether or not the overlapping portion has been processed (step S6). The composite pixel line calculation circuit 12 returns to step S3 if the overlap portion processing has not been completed, and if the overlap portion processing has been completed, the composite pixel line calculation circuit 13 calculates the calculated total and the past total. The result is compared (step S7). When the calculated total is smaller than the past total result, the composite pixel line calculation circuit 12 updates the superposed pixel line A at that time as a composite pixel line (step S8). If the overlapping pixel line A is M-1 (M: the number of vertical pixels in the frame) when the superposition of the current frame and the previous frame is completed (step S9), the combined pixel line calculation circuit 12 The processing operation is terminated. On the other hand, if the overlapping pixel line A does not reach M-1, the composite pixel line calculation circuit 12 adds 1 to A (step S10), returns to step S2, and goes from step S2 to step S9. Repeat the operation.

  FIG. 3 is an explanatory diagram of the operation of the composite pixel line calculation circuit 12. FIG. 3 shows a case where the frame size is 8 × 8 pixels as an outline of the processing procedure. When the process is started, the composite pixel line calculation circuit 12 sets the overlap pixel line A to zero (A = 0) in the process (1), and sets the luminance level of the pixel in the overlap portion between the previous frame and the current frame. The difference is calculated, and the calculated luminance level difference is accumulated. If the cumulative result at this time is 40, the composite pixel line calculation circuit 12 holds the cumulative result 40 as a past cumulative result.

In the next process (2), the composite pixel line calculation circuit 12 adds 1 to the overlapping pixel line A to A = 1, and the luminance when the overlapping pixel line A = 1 as in the process (1). Calculate the cumulative level difference. If the cumulative result of the luminance level difference at this time is 45, since the current cumulative result (45) is larger than the previous cumulative result (40), the composite pixel line calculation circuit 12 does not update the past cumulative result, The accumulated result of the overlapping pixel line A = 0 is continuously held. Further, the composite pixel line calculation circuit 13 also accumulates the luminance level differences in the same manner in the next process (3). If the cumulative result of the difference in luminance level in the overlapped pixel line A = 2 is 30, it is smaller than the past cumulative result, so the composite pixel line calculation circuit 12 updates this cumulative result (30) as the past cumulative result. At the same time, the overlapping pixel line A = 2 is held as a synthesized pixel line. The composite pixel line calculation circuit 12 repeats the above-described processing up to A = 7 (processing (8)), and the overlapping pixel line A (A = 3 in the case of FIG. 3) in which the minimum cumulative result is held. And output as a composite pixel line of the reconstructed image.
JP 2003-331269 A

  However, the composite pixel line calculation circuit 12 in the image processing apparatus 102 described above totals the difference in luminance level of the pixels in order for all the pixel lines, and compares it with the past cumulative result. For this reason, when the size of the input frame increases, the number of pixels that accumulate the difference increases, the processing amount increases, and the time until the generation of the composite image is increased. It was. Further, in order to shorten the processing time, a method of reducing the number of pixels for which the difference is accumulated is conceivable. However, if the number of pixels is reduced in such a manner, the accuracy of overlaying between frames deteriorates.

  The present invention has been made in view of the above circumstances, and in the image processing for generating a composite image from a small image such as a partial image, the processing for generating the composite image without reducing the accuracy of superposition An image processing apparatus and an image processing method capable of reducing time are provided.

  In order to solve the above-described problems, an image processing apparatus according to the present invention includes a superimposition line designating unit that sequentially designates superposition pixel lines in a small image of one input frame, and a superposition line designating unit. A total calculation means for calculating a total of luminance level differences for each pixel in a superimposed portion between a small image of one frame and a small image of a frame before one frame for each of the overlapping pixel lines designated by Image combining means for combining the small image of one frame and the small image of the previous frame with the overlapping pixel line that minimizes the value of the cumulative result calculated by the cumulative calculation means; Prediction means for designating a predicted overlapping pixel line according to the overlapping pixel line of the composite image generated by the means, and Allowed line designating means, superimposing the pixel line of small image of the next one frame is input, and wherein the specifying thins significantly as the distance from the predicted overlay pixel line is designated by the prediction means.

  In order to solve the above-described problem, an image processing method according to the present invention includes a superposition line designation step for sequentially designating superposition pixel lines in a small image of one input frame, and a superposition line. Cumulative calculation step of calculating the sum of the luminance level differences for each pixel in the overlapping portion between the small image of one frame and the small image of the frame before the one frame for each of the overlapping pixel lines specified in the specifying step And an image synthesis process for generating a synthesized image by synthesizing the small image of one frame and the small image of the previous frame with the overlapping pixel line that minimizes the value of the cumulative result calculated in the cumulative calculation step; Specify the predicted overlap pixel line according to the overlap pixel line of the composite image generated in the image composition step Measurement step, and in the overlay line designation step, the overlap pixel line of the small image of the next inputted one frame is thinned out and specified as the distance from the prediction overlap pixel line designated by the prediction step increases. It is characterized by doing.

  According to the image processing apparatus of the present invention, the composite image can be extracted from the small image by designating the superposed line of the small image of the inputted one frame so as to be farther away from the predicted predicted superposed pixel line. In the image processing to be generated, it is possible to shorten the processing time for generating a composite image without reducing the accuracy of overlay between frames.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a configuration diagram of the fingerprint authentication device 200. The fingerprint authentication 200 includes a sensor 201, an image processing device 202, and an authentication circuit 203. The sensor 201 has an elongated reading unit (not shown) having a vertical width of about 0.5 to 5 mm, and performs image processing using a small image (that is, a fingerprint partial image (frame)) read by the reading unit as data. Input to device 202. When the composite image of the entire fingerprint is accumulated in the image processing apparatus 202, the authentication circuit 203 performs fingerprint authentication using the composite image of the entire fingerprint.

  The image processing apparatus 202 includes a partial image memory 41, a composite pixel line calculation circuit 42, and a composite image memory 43. The partial image memory 41 is connected to the sensor 201 and accumulates partial images of fingerprints periodically input from the sensor 201. The partial image memory 41 is connected to a composite pixel line calculation circuit 42 and a composite image memory 43. The composite pixel line calculation circuit 42 compares the current frame supplied from the partial image memory 41 with the previous frame that is one frame before the current frame for each pixel, and when both frames overlap most similarly. A pixel line that starts overlapping with the previous frame in the current frame is calculated as a combined pixel line (that is, an optimal overlapping pixel line). Further, an authentication circuit 203 is connected to the composite image memory 43.

  The combined pixel line calculation circuit 42 includes an overlay circuit 44, a pixel selection circuit 45, a pixel comparison circuit 46, a pixel line determination circuit 47, and a pixel line prediction circuit 50. The superposition circuit 44 is connected to the partial image memory 41, and superimposes the current frame, which is the current partial image held in the partial image memory 41, and the previous frame, which is a partial image that is temporally past, into a superposed pixel line. Is superimposed according to the initial value INI, and an image of the overlapped portion is extracted. A pixel selection circuit 45 and a pixel comparison circuit 46 are connected to the output terminal of the superposition circuit 44. The pixel selection circuit 46 selects a pixel that should take a difference in luminance level between the previous frame and the current frame. The pixel comparison circuit 46 takes the difference in luminance level for each pixel selected by the pixel selection circuit 45, and compares the accumulated value with the accumulated value of the difference in luminance level for each pixel when the overlapping pixel lines are different. Further, the pixel comparison circuit 46 ends the accumulation process for the superimposed pixel line when the accumulated result of the luminance level difference for each pixel described above exceeds the past accumulated result calculated in the previous superimposed pixel line. To do.

  The pixel line determination circuit 47 is connected to the pixel comparison circuit 46. Based on the result of the pixel comparison circuit 46, the pixel line determination circuit 47 determines the overlapping pixel line that minimizes the cumulative value of the luminance level differences for each pixel. Further, the pixel line determination circuit 47 supplies a valid signal VAL to the pixel line prediction circuit 50 together with the pixel line signal of the determined overlapping pixel line (hereinafter referred to as a predicted combined pixel line LIN). The pixel line determination circuit 47 also supplies the composite pixel line LIN to the composite image memory 43.

  The pixel line prediction circuit 50 is connected to the overlay circuit 44 and the pixel line determination circuit 47. The pixel line prediction circuit 50 predicts the composite pixel line of the current frame from the relative moving speed of the previous frame by detecting the change speed of the composite pixel line LIN. Further, the pixel line prediction circuit 50 supplies the prediction result of the composite pixel line to the superposition circuit 44 as the initial value INI of the superposition pixel line.

  As shown in FIG. 5, the pixel line prediction circuit 50 includes two selectors (SEL) 51 and 52, two registers (REG) 53 and 54, a subtractor 55, an adder 56, and a range. And a determination unit 57. With the configuration shown in FIG. 5, the composite pixel line LIN supplied from the pixel line determination circuit 47 is input to the first input terminal of the selector 51 and further supplied to the register 53 via the selector 51.

  The output terminal of the register 53 is connected to the second input terminal of the selector 51 and the first input terminal of the selector 52. That is, the composite pixel line LIN held by the register 53 is supplied to the register 54 via the selector 52. The output terminal of the register 54 is connected to the second input terminal of the selector 52. The selectors 51 and 52 select the composite pixel line LIN supplied from the first input terminal when the composite signal line LIN is valid by the valid signal VAL supplied from the pixel line determination circuit 47. select. The registers 53 and 54 hold the outputs of the selectors 51 and 52 connected to each other according to the clock signal corresponding to the frame.

  The registers 53 and 54 are connected to the subtractor 55. The register 53 and the subtracter 55 are connected to the adder 56. With this configuration, the subtractor 55 takes the difference between the combined pixel line LIN one frame before held in the register 53 and the combined pixel line LIN held two frames before held in the register 54. Further, the subtraction result of the subtracter 55 and the synthesized pixel line LIN one frame before held by the register 53 are added by the adder 56. A range determination unit is connected to the adder 56. The addition result in the adder 56 is supplied to the range determination unit 57 as a prediction result signal (hereinafter referred to as a prediction value PRE).

  The range determination unit 57 determines whether or not the predicted value PRE output from the adder 56 is a value within the range in the vertical or horizontal direction of the frame. When the predicted value PRE output from the adder 56 is outside the frame range, the range determination unit 57 corrects the predicted value PRE supplied from the adder. The range determination unit 57 uses the predicted value PRE supplied from the adder or a value corrected in accordance with the predicted value PRE as the initial value INI of the overlapping pixel line, and supplies it to the overlapping circuit 44. That is, the initial value INI is a predicted overlapping pixel line (hereinafter also referred to as a predicted combined pixel line) predicted by the pixel line prediction circuit 50. Specifically, when the predicted value PRE is between zero (PRE = 0) and the number of pixels M in the vertical or horizontal direction of the frame to a value of minus 1 (PRE = M−1), the range determination unit 57 The value is supplied to the superposition circuit 44 as an initial value INI. In addition, when the predicted value PRE is negative, the range determination unit 57 outputs zero (INI = 0). Further, when the predicted PRE is M or more, the range determination unit 57 outputs minus 1 (INI = M−1) from the number of frames M.

  The superposition circuit 44 does not perform superposition on all the pixels in order from the predicted composite pixel line predicted by the pixel line prediction circuit 50, and in the vicinity of the predictive composite pixel line as shown in FIG. Performs dense superposition and coarsely superposes as the distance from the predicted composite pixel line increases. That is, as the distance from the predicted synthesized pixel line increases, the overlapped pixel line is sequentially changed and designated, and the current frame and the previous frame are overlapped. Specifically, the superimposing circuit 44 performs superimposing on the predicted synthesized pixel line and the pixel lines separated from the predicted synthesized pixel line by 1, 2, 4, 7, 11, 15 pixels by the pixel line predicting circuit 50. The pixel lines separated by 3, 5, 6, 8, 9, 10, 12, 13, 14 pixels from the predicted synthesized pixel line are not overlapped. That is, the superposition circuit 44 determines pixels to be selectively superposed according to the predicted composite pixel line. Note that the pixel lines on which the superposition is performed are not limited to the pixel lines described above, and can be changed as appropriate. FIG. 6 shows the overlapped pixel lines within 15 pixels from the predicted composite pixel line predicted by the pixel line prediction circuit 50, but the prediction is also performed when the pixel lines are separated from the predicted composite pixel line by 15 pixels. The further away from the synthesized pixel line, the thinner the superimposed pixel line is designated.

  FIG. 7 shows a distribution of pixel lines for performing superposition when the predicted synthesized pixel line is changed pixel by pixel when the frame size is 16 pixels in the vertical direction. The leftmost column in FIG. 7 shows the distribution of overlapping pixel lines when the predicted synthesized pixel line predicted by the pixel line prediction circuit 50 is zero (INI = 0). On the other hand, the rightmost column in FIG. 7 shows the distribution of the superimposed pixel lines when the predicted composite pixel line predicted by the pixel line prediction circuit 50 is 15 (INI = 15). Based on the superposition distribution shown in FIG. 7, the superposition order in each predicted synthesized pixel line is shown in Table 1 below.

  As shown in Table 1, in each prediction synthesis pixel line, the superposition circuit 44 performs the superposition on the prediction synthesis pixel line, and then selects a superposition pixel line A which is a reference for frame superposition. Overlay is performed in ascending order. When the superposed pixel line A reaches minus 1 (M−1) of the number of frames, the superposition circuit 44 changes the superposed pixel line A from the minimum value to the predicted composite pixel line in ascending order and performs superposition. carry out. In other words, the superposition circuit 44 changes the predicted composite pixel line in line order. In Table 1, the overlapping pixel line A is changed in ascending order, but the overlapping pixel line A may be changed in descending order (that is, the reverse order of the above-described line order).

  FIG. 8 shows an actual overlay when the frame size is 16 pixels in the vertical direction and 8 pixels in the horizontal direction, and the predicted synthesis pixel line (initial value) INI = 0, INI = 8, and INI = 15 in Table 1. This shows the state of the frame in which the pixel line on which the evaluation is performed is represented in the (M−1) th frame. As shown in FIG. 8, dense overlapping is performed in the vicinity of the predicted combined pixel line predicted by the pixel line prediction circuit 50, and rough overlapping is performed on the pixel lines that are separated from the predicted combined pixel line. It can be seen that

  When pixel lines to be combined in a frame are predicted by the pixel line prediction circuit 50 and superimposing is performed based on the prediction result, the overlapping pixel lines A are sequentially overlapped from zero (A = 0) as in the past. Compared with the case where the alignment is performed, it is possible to shorten the time until the determination of the composite pixel line and the generation of the composite pixel using the line. However, when the frame size increases and the number of pixels for which the luminance level difference is increased, the processing amount increases, and it may be difficult to shorten the processing time.

  In that respect, in the image processing apparatus 202 in the present embodiment, the overlap pixel line in the overlap circuit 44 is specified by thinning out and specifying as the distance from the predicted composite pixel line predicted by the pixel line prediction circuit 50 increases. The number of pixels to be performed can be reduced. Therefore, in the image processing apparatus 202 in the present embodiment, it is possible to prevent an increase in image processing time while suppressing a decrease in image processing accuracy even when the frame size becomes large.

  Next, the operation of the image processing apparatus 202 in the embodiment of the present invention will be described with reference to the fingerprint authentication flow of FIG.

  When the sensor 201 acquires a fingerprint partial image (step S81), the fingerprint partial image is accumulated in the buffer area (fingerprint partial image memory 41) (step S82). Thereafter, the composite pixel line calculation circuit 42 generates a composite image within a predetermined time by superimposing the accumulated partial images of the fingerprint, and stores the generated composite image in the composite image memory 43 (step S83). If all image acquisition has not been completed (step S84: No), the image processing apparatus 202 returns to step S81 and again generates a composite image from acquisition of a partial image (step S81) (step S83). . On the other hand, if all image acquisition has been completed (step S84: Yes), the image processing device 202 performs fingerprint authentication using the composite image stored in the composite image memory 43 (step S85). .

  Next, the operation of the composite pixel line calculation circuit 42 will be described with reference to FIGS. 10 is a composite pixel line calculation flow showing the operation of the composite pixel line calculation circuit 42, FIG. 11 is an explanatory diagram of the speed calculation method of the composite pixel line LIN, and FIG. 12 is an operation description of the composite pixel line calculation circuit 42. FIG. In the following description, the detection of the composite pixel line LIN in the vertical direction will be described. However, the detection of the composite pixel line in the horizontal direction is also performed in the same process, and thus the description thereof is omitted. The input frame size is 16 × 8 pixels.

  The superimposing circuit 44 is sequentially supplied with partial image signals of fingerprints (hereinafter referred to as frame IN) from the partial image memory 41. Further, when the composite pixel line LIN for one frame IN is determined by the pixel line determination circuit 47, the composite pixel line LIN (that is, the pixel of the pixel) of the determined frame together with the valid signal VAL from the pixel line determination circuit 47. The superposed pixel line A) having the minimum accumulated luminance level difference is supplied to the pixel line prediction circuit 50. Hereinafter, the overlapping pixel line in which the total of the differences in the luminance levels of the pixels is the minimum is referred to as the previous result A1.

  The previous result A1 of the composite result LIN is also supplied from the pixel line determination circuit 47 to the composite image memory 43. The previous result A1 of the synthesis result LIN supplied to the pixel line prediction circuit 50 is held by the register 52. At the same time, the overlapping pixel line A in which the sum of the differences in the luminance levels of the pixels in the overlapping of the previous frame of the previous result A1 is shifted from the register 52 to the register 54 and is held by the register 54. Hereinafter, the overlapped pixel line in which the cumulative total of the differences in the luminance levels of the pixels is the minimum is referred to as the result A2 in the last time. Thereby, in the subtractor 55 and the adder 56 of the pixel line prediction circuit 50, as shown in FIG. 11, it is assumed that the frame IN of the partial image is moving at a constant speed, and the next frame is superimposed. The predicted value PRE of the overlapping pixel line A that is first performed is calculated by the following equation based on the previous result A1 and the previous result A2.

  The predicted value PRE is supplied to the range determination unit 57. If the predicted value PRE is between 0 and the number of pixels 16-1 in the vertical direction of the frame, the range determination unit 57 outputs the value as the initial value INI, and if negative, outputs 0 as the initial value INI. If 16 or more, 15 is output. Further, based on the initial value INI supplied from the range determination unit 57, the superposition circuit 44 sets the superposition pixel line A to be superposed first to this initial value INI (step S101 in FIG. 10). Thereafter, the superimposing circuit 44 determines the superposed pixel line A to be subjected to pixel evaluation and the order thereof based on the supplied initial value INI (step S102). Hereinafter, a case where the predicted prediction synthesized pixel line (initial value) is INI = 8 will be described.

  When the next frame IN (Nth frame) is supplied to the superposition circuit 44, the superposition circuit 44 performs the Nth frame and the (N-1) th frame according to the set superposition pixel line A. Overlay (step S103). Specifically, when INI = 8, the superimposing circuit 44 moves the N−1th frame downward by 8 pixels relative to the Nth frame as shown in FIG. = 8) is performed for the first time and superposition is performed.

  Next, the pixel selection circuit 45 determines whether or not it is a pixel of the current frame for which a luminance level difference is to be calculated from the previous frame (step S104). This is a determination for calculating the pixel brightness level difference for only the pixels in the overlapping portion between the current frame and the previous frame determined in the pixel order of the current frame and determined by the overlapping pixel line A. The pixel comparison circuit 46 calculates a difference in luminance level for the target pixel selected by the pixel selection circuit 45 (step S105), and further calculates the total (step S106). By repeating step S104 to step S106, a difference in luminance level for each pixel is calculated, and a cumulative result of differences for each overlapping pixel line A is obtained.

  Next, the pixel comparison circuit 46 compares the accumulated result with the past accumulated result (step S107). Here, since it is the first total and there is no object to be compared, the process proceeds to step S108, and it is determined by the elementary comparison circuit 48 whether or not the processing of the overlapping portion has been completed (step S108). If the overlapped portion has not been processed, the process returns to step S104, and the process from step S104 to step S108 is performed again. On the other hand, if the processing of the overlapping portion has been completed, the accumulated result is retained as the past accumulated result, and the overlapping pixel line having the smallest accumulated result is retained as the composite pixel line (step S109). Subsequently, if all the superpositions are not completed (step S110: No), the superposition circuit line A is updated to the next superposition pixel line by the superposition circuit 44 (step S111). Specifically, since the overlapping pixel line A predicted by the pixel line prediction circuit 50 is 8 (A = 8), the next overlapping pixel line A is 9 (A = 9). On the other hand, if all the superpositions have been completed (step S110: Yes), the operation of the composite pixel line calculation circuit 42 ends.

  The second difference calculation of the target pixel is performed in the state (A = 9) in which the N−1 frames are further moved downward as shown in the process (2) of FIG. 12 as described above. Similar to the first time (superposed pixel line A = 8), the pixel selection circuit 45 selects whether or not to calculate the difference in the superposed state (step S104), and the selected target pixel is selected. The difference is calculated (step S105), and the total is obtained (step S106).

  Next, the pixel comparison circuit 46 compares the cumulative result of this time (superposed pixel line A = 9) with the cumulative result of the previous time (A = 8) (step S107). If the current cumulative result is smaller than the previous cumulative result, the calculation of the luminance level difference for the remaining target pixels and the cumulative processing are further repeated (from step S104 to step S108). When the difference accumulation processing for all target pixels is completed (step S108: Yes), it is also satisfied that the current accumulation result is smaller than the previous accumulation result (step S107: Yes). Is updated as a past cumulative result. If the current cumulative result is larger than the past cumulative result in step S107, the superposition circuit 44 performs the process on the currently set superposition pixel line A regardless of the presence or absence of the remaining processing pixels. When the process is completed, the process proceeds to the next overlapping pixel line (steps S110 and 111).

  When the above processing is repeated in the order shown in Table 1 and the processing of the overlapping pixel line A = 7 is completed, the valid signal VAL is supplied from the pixel line determination circuit 47 to the pixel line prediction circuit 50. Further, the synthesized pixel line LIN supplied from the pixel line determining circuit 47 to the synthesized image memory 43 and the pixel line predicting circuit 50 is the value of the overlapping pixel line A having the smallest cumulative result.

  Note that the overlapping direction of frames in the composite pixel line calculation circuit 42 can be implemented not only in the vertical and horizontal directions but also in the diagonal direction using the same method.

  As described above, according to the image processing apparatus 202 of the present invention, a small image can be obtained by selecting a superposed pixel line to be superposed based on the predicted composite pixel line predicted by the pixel line prediction circuit 50. In image processing for generating a composite image from a partial image, the processing time for generating a composite image can be shortened without reducing the accuracy of overlaying between frames.

  In the first embodiment, the overlapping pixel lines are changed in ascending order by the superimposing circuit. However, the superimposing circuit 44 sequentially starts from the vicinity of the predicted composite pixel line predicted by the pixel line prediction circuit 50 (that is, predicts). A superposition process may be performed in the order of lines close to the composite pixel line. By adopting such a superposition sequence, the minimum total number of pixels can be calculated earlier, and the image processing can be shortened. Specific examples thereof will be described below with reference to Table 2 and FIG. Since there is no change in the configuration and operation of the image processing apparatus 202, the description of the configuration and operation is omitted.

  Similar to the first embodiment, the following table 2 shows the overlapping order in each prediction synthesized pixel line when the frame size is 16 pixels in the vertical direction.

  As shown in Table 2 and FIG. 13, the superposition circuit 44 performs superposition on the predicted composite pixel line, and then performs superposition by sequentially changing from the vicinity of the predictive composite pixel line. That is, as the distance from the predicted synthesized pixel line increases, the overlapped pixel line is designated by being thinned out, the superimposed image line is sequentially changed from the vicinity of the predicted synthesized pixel line, and the current frame and the previous frame are superimposed. Specifically, when the predicted composite pixel line (initial value) is INI = 8, the overlay circuit 44 moves the N−1th frame downward by 8 pixels relative to the Nth frame. Superposition is performed with the state (A = 8) as the first time (process (1)). Next, the superimposing circuit 44 superimposes the state (A = 9) in which the N−1th frame is moved downward by 9 pixels relative to the Nth frame as the second time (processing (2)). I do. Further, the superimposing circuit 44 superimposes the state (A = 7) in which the N−1th frame is moved downward by 7 pixels relative to the Nth frame for the third time (processing (3)). Do. Thereafter, the superposition circuit 44 performs superposition by changing the superposition pixel line A to 10, 6, 12, 4, 15, 1 (that is, sequentially from the vicinity of the predicted composite pixel line).

  As described above, in the second embodiment, by sequentially performing the superimposition from the vicinity of the predicted composite pixel line predicted by the pixel line prediction circuit 50, it may exist in the vicinity of the predicted composite pixel line. It is possible to find the accumulated value of the minimum pixels having high characteristics at an early stage. In addition, such early discovery of the cumulative value leads to a reduction in the number of computations and a reduction in the processing time of the composite pixel line determination process, so that the power consumption of the image processing apparatus 202 can be reduced.

  In each of the above-described embodiments, the overlapping pixel line is a line extended in the horizontal direction in order to overlap two consecutive frames in the vertical direction, but in the case of overlapping two consecutive frames in the horizontal direction, The overlapping pixel line is a line extended in the horizontal direction. The overlapping pixel line may be an oblique pixel line, and the overlapping state between frames may be specified by combining a vertical pixel line and a horizontal pixel line.

  In each of the above-described embodiments, the current frame and the previous frame are superimposed. However, the current frame and two or more previous frames may be superimposed.

It is a block diagram of the conventional fingerprint authentication apparatus. It is a processing flowchart which shows operation | movement of the synthetic | combination pixel line calculation circuit of the conventional image processing apparatus. It is operation | movement explanatory drawing of the synthetic | combination pixel line calculation circuit of the conventional image processing apparatus. 1 is a configuration diagram of a fingerprint authentication apparatus including an image processing apparatus as a first embodiment of the present invention. It is a block diagram of the synthetic | combination pixel prediction circuit of the image processing apparatus as 1st Example of this invention. It is explanatory drawing of the superimposition pixel line from the prediction prediction synthetic | combination pixel line. It is a distribution map of the pixel line which performs superposition when a prediction synthetic pixel line is moved one pixel at a time. It is explanatory drawing of the overlapping pixel line for every prediction synthetic | combination pixel line. It is a processing flowchart which shows operation | movement of the fingerprint authentication apparatus containing the image processing apparatus as an Example of this invention. It is a processing flowchart which shows operation | movement of the synthetic | combination pixel line calculation circuit of the image processing apparatus as an Example of this invention. It is explanatory drawing of the speed detection method of the image processing apparatus as an Example of this invention. It is explanatory drawing of operation | movement of the synthetic | combination pixel line calculation circuit of the image processing apparatus as 1st Example of this invention. It is explanatory drawing of operation | movement of the synthetic | combination pixel line calculation circuit of the image processing apparatus as 2nd Example of this invention.

Explanation of symbols

41 Partial image memory 42 Composite pixel line calculation circuit 43 Composite image memory 44 Superposition circuit 45 Pixel selection circuit 46 Pixel comparison circuit 47 Pixel line determination circuit 50 Composite pixel prediction circuit 200 Fingerprint authentication device 201 Sensor 202 Image processing device 203 Authentication circuit

Claims (4)

An image processing apparatus that sequentially outputs as frames and generates a composite image by superimposing small images each consisting of a plurality of pixel lines,
Superimposition line designating means for sequentially designating superposed pixel lines in a small image of one input frame;
For each overlapping pixel line designated by the superimposing line designating means, the sum of the differences in luminance level for each pixel in the overlapping portion between the small image of the first frame and the small image of the frame before the one frame. A cumulative calculation means for calculating
Image combining means for generating a composite image by combining the small image of the first frame and the small image of the previous frame with the overlapping pixel line that minimizes the value of the cumulative result calculated by the cumulative calculation means; ,
Predicting means for designating a predicted overlapping pixel line according to the overlapping pixel line of the composite image generated by the image combining means,
The superimposition line designating means designates the superimposition pixel line of the small image of one frame inputted next, as it is largely thinned away from the prediction superimposition pixel line designated by the prediction means. An image processing apparatus.   The superimposition line means designates a superimposition pixel line of a small image of one frame inputted next according to a line order from the prediction superposition pixel line or vice versa. The image processing apparatus according to 1.   2. The image according to claim 1, wherein the superimposition line means designates a superimposition pixel line of a small image of one frame inputted next in order of lines closer to the prediction superimposition pixel line. Processing equipment. An image processing method that sequentially outputs as frames and generates a composite image by superimposing small images each consisting of a plurality of pixel lines,
A superposition line designation step for sequentially changing and design the superposition pixel lines in the input small image of one frame;
For each of the overlapping pixel lines specified in the overlapping line specifying step, the cumulative total of the luminance level differences for each pixel in the overlapping portion between the small image of the first frame and the small image of the frame before the one frame. A cumulative calculation step for calculating
An image synthesis process for generating a synthesized image by synthesizing the small image of the first frame and the small image of the previous frame with the overlapping pixel line that minimizes the value of the cumulative result calculated in the cumulative calculation step; ,
A prediction step of designating a predicted overlapping pixel line according to the overlapping pixel line of the combined image generated in the image combining step,
In the superimposition line designation step, the superimposition pixel line of the small image of one frame inputted next is thinned and designated as the distance from the prediction superimposition pixel line designated in the prediction step increases. Image processing method.

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