JP2010022180A - Circuit for driving motor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique realizing advance angle control or delay angle control for a PWM signal by a configuration different from conventional ones. <P>SOLUTION: The circuit for driving a motor generates a periodic PWM signal as a drive signal for driving the motor based on a periodic positional signal showing the relative locations of the first and second driving members of the motor, and sets a temporal position of the periodic boundary of the PWM signal to a position different from the temporal position of the periodic boundary of the positional signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit of an electric motor.

  Conventionally, as a technique related to a drive circuit of an electric motor, for example, one disclosed in Patent Document 1 is known.

International Publication Number WO2005 / 112230A1

  However, in the past, when the PWM signal was generated, the actual situation was that no sufficient contrivance was made with respect to the advance angle control and the retard angle control.

  The present invention has been made to solve the above-described conventional problems, and it is an object of the present invention to provide a technique that can realize advance angle control and delay angle control of a PWM signal with a configuration different from the conventional one. And

  In order to solve at least a part of the problems described above, the present invention can take the following forms or application examples.

[Application Example 1]
A circuit for driving an electric motor,
Based on a periodic position signal indicating the relative positions of the first and second driving members of the electric motor, a periodic PWM signal is generated as a driving signal for driving the electric motor,
A circuit capable of setting a temporal position of a boundary of a period of the PWM signal to a position different from a temporal position of a boundary of a period of the position signal.
According to the circuit of the application example 1, the time position of the PWM signal cycle boundary can be set to a position different from the time position of the position signal cycle boundary. Angle control can be realized.

[Application Example 2]
A circuit according to application example 1,
An address value setting unit that divides each half cycle of the position signal into a predetermined number of sections and sets an address value that circulates in the predetermined number for each of the divided sections;
A pulse width setting unit for setting a pulse width for performing PWM control for each of the divided sections based on the address value;
A PWM signal generation unit that generates the PWM signal by performing PWM control for each of the divided sections based on the pulse width;
With
The circuit, wherein the address value setting unit sets the address value so that a temporal position where the address value starts to circulate is different from a temporal position of a boundary of the period of the position signal.
In the circuit of Application Example 2, the address value setting unit sets the address value so that the temporal position where the address value starts to circulate is different from the temporal position of the boundary of the period of the position signal. . Therefore, if the pulse width is set based on this address value, it is possible to realize advance angle control and retard angle control of the PWM signal.

[Application Example 3]
The circuit according to application example 2,
An excitation interval setting unit that determines an excitation interval in which the PWM signal is valid as the drive signal based on the address value;
The pulse width setting unit is configured to set the pulse width so that the PWM signal is generated in a section set as the excitation section among the divided sections.
In the circuit of Application Example 3, the pulse width setting unit sets the pulse width so that the PWM signal is generated in the section set as the excitation section among the divided sections. Therefore, since no PWM signal is generated in the sections other than the excitation section, the power consumption of the motor can be reduced.

[Application Example 4]
The circuit according to any one of Application Examples 1 to 3,
The circuit, wherein the pulse width setting unit sets the pulse width so that a minimum value of the pulse width excluding 0 is 50% or less with respect to the maximum value of the pulse width.
According to the circuit of Application Example 4, the electric motor can be driven efficiently.

[Application Example 5]
The circuit according to any one of Application Examples 1 to 3,
The pulse width setting unit sets the pulse width so that an effective waveform of the PWM signal has a shape simulating a sine waveform.
According to the circuit of Application Example 5, the electric motor can be driven efficiently.

[Application Example 6]
The circuit according to any one of Application Examples 1 to 3,
The pulse width setting unit sets the pulse width so that an effective waveform of the PWM signal has a shape simulating a Gaussian waveform.
According to the circuit of Application Example 6, the electric motor can be driven efficiently.

  Note that the present invention can be realized in various modes. For example, the present invention can be realized in the form of an electric motor driving method and driving device, a driving system, an integrated circuit for realizing the functions of the method or device, a computer program, a recording medium on which the computer program is recorded, and the like. The present invention can also be realized in the form of an electric motor including a drive circuit, an electronic device including the electric motor, a projector, a portable device, a robot, a moving body, and the like.

Next, embodiments of the present invention will be described in the following order based on examples.
A. First embodiment:
B. Second embodiment:
C. Third embodiment:
D. Fourth embodiment:
E. Example 5:
F. Variation:

A. First embodiment:
A1. Overview of motor configuration and operation:
1A and 1B are cross-sectional views showing the configuration of a motor body of a single-phase brushless motor as an embodiment of the present invention. The motor body 100 includes a stator portion 10 and a rotor portion 30 whose outer shapes are substantially cylindrical. The stator unit 10 includes four coils 11 to 14 arranged in a substantially cross shape and a magnetic sensor 40 disposed at a central position between the two coils 11 and 12. The magnetic sensor 40 is for detecting the position of the rotor unit 30 (that is, the phase of the motor). Each of the coils 11 to 14 is provided with a magnetic yoke 20 made of a magnetic material. The coils 11 to 14 and the magnetic sensor 40 are fixed on the circuit board 120 (FIG. 1B). The circuit board 120 is fixed to the casing 102. Note that the lid of the casing 102 is not shown.

  The rotor unit 30 has four permanent magnets 31 to 34, and the central axis of the rotor unit 30 constitutes the rotation shaft 112. The rotating shaft 112 is supported by a bearing portion 114 (FIG. 1B). The magnetization direction of each magnet is a direction radially outward from the rotating shaft 112. A magnetic yoke 36 is provided on the outer periphery of the magnets 31 to 34. However, this magnetic yoke 36 may be omitted.

  FIG. 2 is an explanatory diagram showing the positional relationship between the magnet array and the coil array, and the relationship between the magnetic sensor output and the back electromotive force waveform of the coil. As shown in FIG. 2A, the four magnets 31 to 34 are arranged at a constant magnetic pole pitch Pm, and adjacent magnets are magnetized in opposite directions. Moreover, the coils 11-14 are arrange | positioned with the fixed pitch Pc, and adjacent coils are excited by the reverse direction. In this example, the magnetic pole pitch Pm is equal to the coil pitch Pc and corresponds to π in electrical angle. The electrical angle 2π is associated with a mechanical angle or distance that moves when the phase of the drive signal changes by 2π. In this embodiment, when the phase of the drive signal changes by 2π, the rotor unit 30 moves by twice the magnetic pole pitch Pm.

  Of the four coils 11 to 14, the first and third coils 11 and 13 are driven by drive signals having the same phase, and the second and fourth coils 12 and 14 are driven by the first and third coils 11 and 14. Driven by a drive signal whose phase is shifted by 180 degrees (= π) from the 13 drive signals. In normal two-phase driving, the phases of the drive signals of the two phases (A phase and B phase) are shifted by 90 degrees (= π / 2), and there is no case where the phase shift is 180 degrees (= π). In the motor driving method, two drive signals whose phases are shifted by 180 degrees (= π) are often regarded as having the same phase. Therefore, it can be considered that the driving method in the motor of this embodiment is single-phase driving.

  FIG. 2A shows the positional relationship between the magnets 31 to 34 and the coils 11 to 14 when the motor is stopped. In the motor of the present embodiment, the magnetic yoke 20 provided in each of the coils 11 to 14 is provided at a position slightly shifted in the forward rotation direction of the rotor portion 30 from the center of each coil. Therefore, when the motor is stopped, the magnetic yoke 20 of each coil is attracted by the magnets 31 to 34, and the rotor unit 30 stops at a position where the magnetic yoke 20 faces the center of each of the magnets 31 to 34. As a result, the motor stops at the position where the centers of the coils 11 to 14 are shifted from the centers of the magnets 31 to 34. At this time, the magnetic sensor 40 is also slightly displaced from the boundary between adjacent magnets. The phase at this stop position is α. The phase α is not zero, but is a small value close to zero (for example, about 5 to 10 degrees).

  2B shows an example of the waveform of the counter electromotive force generated in the coil, and FIG. 2C shows an example of the output waveform of the magnetic sensor 40. The magnetic sensor 40 can generate a sensor output SSD having a rectangular waveform synchronized with the back electromotive force waveform of the coil during motor operation. However, the output SSD of the magnetic sensor 40 shows a non-zero value even when the motor is stopped (except when the phase is from π to 2π). Note that the counter electromotive force of the coil tends to increase with the number of rotations of the motor, but the waveform shape (sine wave) is kept substantially similar. As the magnetic sensor 40, for example, a Hall IC (digital output) using the Hall effect can be employed. In this example, the sensor output SSD is a rectangular wave, and the back electromotive force Ec is a sine wave or a waveform close to a sine wave. As will be described later, the motor drive control circuit applies a voltage having a waveform substantially similar to the back electromotive force Ec to each of the coils 11 to 14 using the sensor output SSD.

  By the way, the electric motor functions as an energy conversion device that mutually converts mechanical energy and electrical energy. The back electromotive force of the coil is obtained by converting the mechanical energy of the electric motor into electrical energy. Therefore, when the electrical energy applied to the coil is converted into mechanical energy (that is, when the motor is driven), the motor is driven most efficiently by applying a voltage having a waveform similar to the counter electromotive force. Is possible. As described below, “a voltage having a waveform similar to that of the back electromotive force” means a voltage that generates a current in the opposite direction to the back electromotive force.

  FIG. 3 is a schematic diagram showing the relationship between the applied voltage of the coil and the back electromotive force. Here, the coil is simulated by a back electromotive force Ec and a resistance. In this circuit, a voltmeter V is connected in parallel with the applied voltage E1 and the coil. When the voltage E1 is applied to the coil to drive the motor, a back electromotive force Ec is generated in a direction in which a current opposite to the applied voltage E1 flows. When the switch SW is opened while the motor is rotating, the back electromotive force Ec can be measured by the voltmeter V. The polarity of the back electromotive force Ec measured with the switch SW opened is the same polarity as the applied voltage E1 measured with the switch SW closed. In the above description, the phrase “applying a voltage having a waveform similar to that of the back electromotive force” refers to a voltage having a waveform having a substantially similar shape having the same polarity as the back electromotive force Ec measured by the voltmeter V. It means to apply.

  As described above, when the motor is driven, the motor can be driven most efficiently by applying a voltage having a waveform similar to that of the counter electromotive force. Note that the energy conversion efficiency is relatively low near the middle point of the sinusoidal back electromotive force waveform (near voltage 0), and conversely, the energy conversion efficiency is relatively high near the peak of the back electromotive force waveform. it can. When the motor is driven by applying a voltage having a waveform similar to the counter electromotive force, a relatively high voltage is applied during a period of high energy conversion efficiency, so that the motor efficiency is improved. On the other hand, for example, when the motor is driven with a simple rectangular wave, a considerable voltage is applied even in the vicinity of the position where the back electromotive force is almost zero (middle point), so that the motor efficiency decreases. In addition, when a voltage is applied in such a period with low energy conversion efficiency, vibration in a direction other than the rotation direction is caused by an eddy current, thereby causing a problem that noise is generated.

  As can be understood from the above description, when the motor is driven by applying a voltage having a waveform similar to that of the back electromotive force, the motor efficiency can be improved, and vibration and noise can be reduced. .

  FIGS. 4A to 4E are explanatory views showing a state of the forward rotation operation of the motor main body 100. FIG. FIG. 4A shows the positional relationship between the magnets 31 to 34 and the coils 11 to 14 when stopped, and is the same diagram as FIG. When the coils 11 to 14 are excited in the state of FIG. 4A, repulsive forces indicated by broken arrows are generated between the coils 11 to 14 and the magnets 31 to 34. As a result, the rotor unit 30 is started in the forward rotation direction (right direction in the figure).

  FIG. 4B shows a state where the phase has advanced to π / 2. In this state, a suction force (solid arrow) and a repulsive force (broken arrow) are generated to generate a large driving force. FIG. 4C shows a state where the phase has advanced to (π−α). At the timing when the phase becomes π, the excitation direction of the coil is reversed, and the state shown in FIG. When the motor stops in the vicinity of the state of FIG. 4D, the rotor unit 30 stops at the position where the magnetic yoke 20 is attracted to each of the magnets 31 to 34 as shown in FIG. This position is a position where the phase is (π + α). Thus, it can be understood that the motor of this embodiment stops at a position where the phase is α ± nπ (n is an integer).

  FIGS. 5A to 5E are explanatory views showing the reverse operation of the motor body 100. FIG. FIG. 5 (A) shows a state at the time of stop, which is the same as FIG. 4 (A). If the coils 11 to 14 are excited in the direction opposite to that shown in FIG. 4A in order to reverse the state from the stop state, an attractive force (not shown) acts between the magnets 31 to 34 and the coils 11 to 14. become. This suction force acts in a direction in which the rotor unit 30 is reversed. However, since this attractive force is quite weak, there is a case where the rotor unit 30 cannot be reversed by overcoming the attractive force between the magnets 31 to 34 and the magnetic yoke 20.

  In the present embodiment, even when the reverse operation is performed, the motor is operated in the normal rotation direction as shown in FIG. Then, after the rotor unit 30 has rotated by a predetermined amount (for example, when the phase has advanced by about π / 2), the drive signal is inverted as shown in FIG. Thus, once the rotor unit 30 starts to reverse, the first stop position (phase = α) can be passed by the inertia of the rotor unit 30 (FIG. 5C). Thereafter, the excitation direction of the coil is reversed at the timing when the phase becomes zero. FIG. 5D shows a state where the phase is −π / 2, and FIG. 5E shows a state where the phase is −π + α. When the motor stops in the vicinity of the state of FIG. 5E, the rotor unit 30 stops at the position (phase = −π + α) where the magnetic yoke 20 is attracted to each of the magnets 31 to 34.

  FIG. 6 is a flowchart showing a control procedure of the moving direction of the motor. This procedure is executed by a drive control circuit described later. In step S10, first, drive control is started in the positive direction. In step S20, it is determined whether or not the target moving direction is the positive direction. Note that the moving direction is input to the drive control circuit by the operator before step S10. When the target movement direction is the positive direction, the drive control in the positive direction is continued as it is. On the other hand, if the target moving direction is the reverse direction, the process waits at step S30 until a predetermined timing to be reversed is reached. When the timing to reverse is reached, reverse drive control is started in step S40.

  As described above, in the motor of the present embodiment, since the motor stops at a position where the phase is α ± nπ (α is a predetermined value other than zero and nπ, n is an integer), no dead lock point is generated. Therefore, it is possible to always start without requiring a starting coil. Further, in the motor of the present embodiment, it is possible to realize the reverse rotation operation by performing reverse rotation after forward rotation by a predetermined amount from the stopped state.

A2. Configuration of drive control circuit:
FIG. 7 is a block diagram showing the configuration of the drive control circuit of the brushless motor of this embodiment. The drive control circuit 200 includes a CPU 220, a drive signal generation unit 240, and a driver circuit 250. The drive signal generation unit 240 generates single-phase drive signals DRVA1 and DRVA2 based on the output signal SSD of the magnetic sensor 40 in the motor body 100. The driver circuit 250 drives the electromagnetic coils 11 to 14 in the motor main body 100 according to the single-phase drive signals DRVA1 and DRVA2.

  FIG. 8 shows the internal configuration of the driver circuit 250. The driver circuit 250 includes four transistors 251 to 254 that constitute an H-type bridge circuit. Level shifters 311 and 313 are provided in front of the gate electrodes of the upper arm transistors 251 and 253. However, the level shifter may be omitted. The transistors 251 to 254 of the driver circuit 250 are turned on / off according to the drive signals DRVA1 and DRVA2 functioning as switching signals, and as a result, the supply voltage VSUP is intermittently supplied to the electromagnetic coils 11 to 14. Arrows denoted by reference signs IA1 and IA2 indicate directions of currents flowing when the drive signals DRVA1 and DRVA2 are at the H level, respectively. In addition, as a driver circuit, the circuit of the various structure comprised by a some switching element can be utilized.

  FIG. 9 is an explanatory diagram showing another configuration of the driver circuit. The driver circuit includes a first bridge circuit 250 a for the first set of electromagnetic coils 11 and 13 and a second bridge circuit 250 b for the second set of electromagnetic coils 12 and 14. Each of the bridge circuits 250a and 250b includes four transistors 251 to 254, and this configuration is the same as that shown in FIG. Level shifters 311 and 313 are provided in front of the gate electrodes of the transistors 251 and 253. However, the level shifter may be omitted. In the first bridge circuit 250a, the first drive signal DRVA1 is supplied to the transistors 251 and 254, and the second drive signal DRVA2 is supplied to the other transistors 252 and 253. On the other hand, in the second bridge circuit 250b, the first drive signal DRVA1 is supplied to the transistors 252 and 253, and the second drive signal DRVA2 is supplied to the transistors 251 and 254. As a result, as shown in FIGS. 9B and 9C, the operations of the first bridge circuit 250a and the second bridge circuit 250b are reversed. Therefore, the first set of coils 11 and 13 driven by the first bridge circuit 250a and the second set of coils 12 and 14 driven by the second bridge circuit 250b are out of phase with each other by π. Yes. On the other hand, in the circuit shown in FIG. 8, the winding method of the first set of coils 11 and 13 and the winding method of the second set of coils 12 and 14 are reversed. It is shifted by π. As described above, the use of either the driver circuit of FIG. 8 or the driver circuit of FIG. 9 is the same in that the phases of the two sets of coils are shifted from each other by π, and both realize a one-phase motor. There is no change.

  FIG. 10 shows various winding methods of the electromagnetic coils 11 to 14. As in this example, it is possible to always excite adjacent coils in the reverse direction by devising the winding method.

  FIG. 11 is an explanatory diagram showing the internal configuration of the drive signal generator 240 (FIG. 7). The drive signal generation unit 240 includes a control signal generation unit 300, an address formation unit 330, a pulse width setting unit 340, a PWM signal generation unit 350, an excitation interval restriction unit 360, and an excitation interval signal generation unit 370. ing. The control signal generation unit 300, the pulse width setting unit 340, and the excitation interval signal generation unit 370 are connected to the CPU 220 via the bus 400. The control signal generator 300 receives the output signal SSD from the magnetic sensor 40, receives the PWM clock signal CLKpwm, the address clock signal CLKadd, the forward / reverse direction command value signal RI, the address reset signal ADDrst, and the speed signal RRflag. Is output. Further, the control signal generator 300 also outputs the input sensor signal SSD as it is. The address forming unit 330 receives the address reset signal ADDrst, the address clock signal CLKadd, and the sensor signal SSD, and outputs an address value ADD. The pulse width setting unit 340 sets the pulse width WD according to the address value ADD. The PWM signal generator 350 receives the sensor signal SSD, the PWM clock signal CLKpwm, the address clock signal CLKadd, the forward / reverse direction command value signal RI, and the pulse width WD, and receives the first and second PWM signals PWM1. , 2 are output. The excitation interval restriction unit 360 generates the first and second drive signals DRVA1 and 2 based on the first and second PWM signals PWM1 and PWM2 and the excitation interval signal Enb generated by the excitation interval signal generation unit 370. Generate. The excitation interval signal generator 370 generates an excitation interval signal Enb based on the speed signal RRflag and the address value ADD. These operations will be described in detail below.

  FIG. 12A is a block diagram illustrating an internal configuration of the control signal generation unit 300. FIG. 12B is a timing chart showing changes in various signals. The control signal generation unit 300 includes a reference clock signal generation unit 302, a speed signal generation unit 304, an edge detection unit 306, a PLL circuit 307, a second frequency divider 316, a frequency division value storage unit 318, And a reverse direction command value storage unit 320. The reference clock signal generation unit 302 generates a reference clock signal CLKorg having a constant frequency. The reference clock signal CLKorg is supplied to the speed signal generation unit 304. The sensor signal SSD is supplied to the edge detection unit 306 and the PLL circuit 307. The edge detection unit 306 detects a rising edge and a falling edge of the sensor signal SSD and generates an address reset signal ADDrst that generates a pulse in accordance with each edge. The address reset signal ADDrst is supplied to the speed signal generation unit 304 and the address formation unit 330 (FIG. 11). The speed signal generation unit 304 generates a speed signal RRflag indicating the rotation speed of the motor by counting the number of pulses of the reference clock signal CLKorg between two pulses of the address reset signal ADDrst. That is, the larger the number of pulses of the reference clock signal CLKorg counted between the two pulses of the address reset signal ADDrst, the lower the rotation speed of the motor. Conversely, the smaller the number of pulses of the reference clock signal CLKorg counted, The motor speed is high. In this embodiment, the speed signal generation unit 304 determines the threshold value of the number of pulses to be counted so that the speed signal RRflag indicates a four-stage speed from 0 to 3 according to the number of pulses of the reference clock signal CLKorg to be counted. Is set. The speed signal RRflag indicates a higher speed as RRflag = 0 to RRFlag = 3.

  The PLL circuit 307 includes a phase comparator 308, a loop filter (LPF) 310, a voltage controlled oscillator (VCO) 312, and a first frequency divider 314. The first divider 314 divides the input PWM clock signal CLKpwm using the divided value (2 × M × N) stored in the divided value storage unit 318. The sensor signal SSD is input to the phase comparator 308. On the other hand, the frequency-divided signal DVSSD generated by the first frequency divider 314 is input to the phase comparator 308 as a comparison signal. The phase comparator 308 generates an error signal CPS indicating the phase difference between these two signals SSD and DVSSD. The error signal CPS is sent to the loop filter 310 having a built-in charge pump circuit. The loop filter 310 generates and outputs a voltage control signal LPS having a voltage level corresponding to the pulse level and the number of pulses of the error signal CPS.

The voltage control signal LPS is supplied to the voltage control oscillator 312. The voltage controlled oscillator 312 outputs a PWM clock signal CLKpwm having a frequency corresponding to the voltage level of the voltage control signal LPS. The PWM clock signal CLKpwm is frequency-divided by 1 / (2 × M × N) by the first frequency divider 314 to generate a frequency-divided signal DVSSD. As described above, the frequency-divided signal DVSSD is sent to the phase comparator 308 and phase-compared with the sensor signal SSD. As a result, the frequency of the PWM clock signal CLKpwm converges so that the phase difference between the two signals SSD and DVSSD becomes zero. Therefore, the relationship between the frequency fCLKpwm of the PWM clock signal CLKpwm after convergence and the frequency fSDD of the sensor signal SSD is expressed by the following equation (1).
fCLKpwm = fSSD × (2 × M × N) (1)

The PWM clock signal CLKpwm is supplied to the second frequency divider 316 and the PWM signal generator 350 (FIG. 11). The second frequency divider 316 divides the input PWM clock signal CLKpwm using the frequency division value N stored in the frequency division value storage unit 318 to generate an address clock signal CLKadd. Therefore, the relationship between the frequency fCLKadd of the address clock signal CLKadd and the frequency fCLKpwm of the PWM clock signal CLKpwm is expressed by the following equation (2).
fCLKadd = fCLKpwm / N (2)

From the above equations (1) and (2), the relationship between the frequency fSSD of the sensor signal SSD, the frequency fCLKadd of the address clock signal CLKadd, and the frequency fCLKpwm of the PWM clock signal CLKpwm is as follows (3), (4) It becomes an expression.
fCLKadd = fSSD × 2 × M (3)
fCLKpwm = fCLKadd × N (4)
As shown in FIG. 12B, the address clock signal CLKadd is a signal that generates M pulses in each of the high level period and the low level period of the sensor signal SSD. The PWM clock signal CLKpwm is a signal that generates N pulses during one cycle of the address clock signal CLKadd. The frequency dividing values M and N can be rewritten to arbitrary values by the CPU 220.

  The forward / reverse direction command value storage unit 320 stores a forward / reverse direction command value signal RI that instructs the rotation direction of the motor designated by the CPU 220. The forward / reverse direction command value signal RI is a signal indicating a low level when the motor is to be rotated in the forward direction, and indicating a high level when the motor is to be rotated in the reverse direction.

  FIG. 13 is a block diagram showing an internal configuration of the address forming unit 330. 14 and 15 are timing charts showing various signals in the address forming unit 330. The address forming unit 330 (FIG. 13) includes a counter unit 331, a maximum count value storage unit 332, a start address value storage unit 333, an address value calculation unit 334, and a polarity signal generation unit 335. The polarity signal generation unit 335 will be described later. The counter unit 331 counts the number of pulses of the address clock signal CLKadd and supplies the count value COUNT to the address value calculation unit 334. Then, the counter unit 331 resets the count value COUNT to 0 at the rising edge of the address reset signal ADDrst and starts counting again. However, the upper limit value indicated by the count value COUNT is a value smaller by 1 than the maximum count value MAXADD. The maximum count value MAXADD is stored in the maximum count value storage unit 332. The maximum count value MAXADD is preferably set to a value equal to the frequency division value M. In this embodiment, the frequency division value M = the maximum count value MAXADD = 14. Since the maximum count value storage unit 332 is connected to the CPU 220, the maximum count value MAXADD can be rewritten by the CPU 220.

  The address value calculation unit 334 calculates an address value ADD based on the count value COUNT, the maximum count value MAXADD, and the start address value STADD. The start address value STADD is stored in the start address value storage unit 333 and is a value indicating how much the timing when the address value ADD = 0 is shifted with respect to the timing when the count value COUNT = 0. FIG. 14 shows the case where the start address value STADD = 0, and FIG. 15 shows the case where the start address value STADD = 3. Note that since the start address value storage unit 333 is connected to the CPU 220, the start address value STADD can be rewritten by the CPU 220.

The address value calculation unit 334 calculates the address value ADD as follows.
First, the difference value OFAD is calculated by the following equation (5).
OFAD = MAXADD−STADD (5)
When the count value COUNT is smaller than the difference value OFAD, the address value ADD is calculated by the following equation (6).
ADD = COUNT + STADD (6)
When the count value COUNT increases and becomes equal to or greater than the difference value OFAD, the address value ADD is calculated by the following equation (7).
ADD = COUNT-OFAD (7)

  Since the address value ADD is calculated as described above, the timing at which the address value ADD = 0 is shifted earlier in time by the value of the start address value STADD than the timing at which the count value COUNT = 0. Can be made. That is, in FIG. 14, since the start address value STADD = 0, the address value ADD = 0 at the timing when the count value COUNT = 0. On the other hand, in FIG. 15, since the start address value STADD = 3, the address value ADD = 3 at the timing when the count value COUNT = 0.

  As described above, the starting point at which the address value ADD starts to circulate (that is, the timing when the address value ADD = 0) and the temporal positions of the rising edge and the falling edge of the sensor signal SSD (that is, the count value COUNT = By setting the timing to be different), it is possible to realize the advance angle control and the retard angle control of the PWM signal. A method for generating the PWM signal will be described later.

  FIG. 16 is a circuit diagram showing the internal configuration of the polarity signal generator 335. The polarity signal generation unit 335 generates the polarity signal Px based on the sensor signal SSD and the address clock signal CLKadd. The polarity signal Px is a signal for separating one PWM signal (signal S1 described later) into two PWM signals PWM1 and PWM2. The polarity signal generation unit 335 includes an EXOR gate 336, a de-flip flop 337 (hereinafter also referred to as “DFF 337”), an inversion signal generation unit 338, and a permission signal generation unit 339. These operate as follows.

  FIG. 17 is a timing chart showing various signals in the polarity signal generation unit 335. FIG. 17 shows a case where the start address value STADD = 3. The inverted signal generation unit 338 (FIG. 16) receives the start address value STADD and outputs a signal Q1 indicating a high level when the start address value STADD is greater than zero. The EXOR gate 336 outputs a signal Q2 indicating an exclusive OR of the sensor signal SSD and the signal Q1. That is, in FIG. 17, since the signal Q1 indicates a high level, the signal Q2 has a waveform obtained by inverting the sensor signal SSD. The permission signal generation unit 339 receives the address value ADD and outputs a permission signal Q3 indicating a high level when the address value ADD = 0. The DFF 337 receives the signal Q2, the address clock signal CLKadd, and the permission signal Q3, and outputs a polarity signal Px. That is, the signal Q2 is input to the input terminal of the DFF 337, the address clock signal CLKadd is input to the clock terminal, and the permission signal Q3 is input to the enable terminal. By configuring the polarity signal generation unit 335 as described above, the waveform of the polarity signal Px can be a waveform obtained by shifting the sensor signal SSD in the direction earlier in time by the start address value STADD ( FIG. 17).

  FIG. 18A is a block diagram illustrating an internal configuration of the pulse width setting unit 340. FIG. 18B is a timing chart showing changes in various signals. Note that the signal S1 described in FIG. 18B is a signal generated by a down counter unit 352 (FIG. 20), which will be described later, and a signal having a pulse corresponding to the pulse width WD. The pulse width setting unit 340 includes a table selection unit 342 and three table units 344, 346, 348. The table selection unit 342 selects one table unit from among the three table units 344, 346, 348 in accordance with the value of the speed signal RRflag. For example, when RRflag = 1, the table unit 346 is selected. The three table units 344, 346, and 348 store the pulse width WD output according to the address value ADD, and the selected table unit stores the pulse width WD according to the input address value ADD. Is output.

  When RRflag = 0, that is, when the rotational speed of the motor is low, the first table unit 344 is selected. In this specification, the value “Xh” means a hexadecimal number. The selected first table unit 344 always outputs the pulse width WD = Fh. If the pulse width WD is set to the maximum value Fh in this way, a large driving force can be obtained from the start of the motor to the low speed.

  When RRflag = 1 or 2, that is, when the rotational speed of the motor increases, the second table unit 346 is selected. The table unit 346 sets the pulse width WD so that the pulse width WD becomes the maximum value Fh in the address value ADD corresponding to the vicinity of the center of the pulse of the sensor signal SSD. Then, each pulse width WD is set so that the pulse width WD decreases as the address value ADD moves away from the vicinity of the center of the pulse of the sensor signal SSD. If the pulse width WD is set in this way, a PWM signal simulating a counter electromotive force waveform can be generated, and the motor can be driven efficiently. When the speed signal RRflag is 1 or 2, the pulse width WD output from the pulse width setting unit 340 is the same, but excitation intervals described later are set to different values. Further, the maximum value of the pulse width WD is not limited to Fh, and may be a predetermined maximum value corresponding to the value of the frequency division value N or a predetermined maximum value determined arbitrarily.

  When RRflag = 3, that is, when the rotational speed of the motor is further increased, the third table unit 348 is selected. The table unit 348 sets the pulse width WD so that the maximum value Fh is reached at a timing earlier than the center of the pulse of the sensor signal SSD. As a result, it is possible to realize advance angle control that slightly advances the phase of the drive signal DRVA. When the rotation of the motor is low, the effect does not change much depending on the presence / absence of the advance angle control. However, when the motor speed is high, the efficiency can be significantly improved by the advance angle control.

  The pulse width WD stored in the three table units 344, 346, and 348 can be rewritten to an arbitrary value by the CPU 220. Therefore, PWM signals PWM1 and PWM2 having an arbitrary pulse width WD can be generated by a PWM signal generation unit 350 (FIG. 11) described later.

  FIG. 19A is a timing chart showing various signals when RRflag = 1 or 2 and STADD = 0. FIG. 19B is a timing chart showing various signals when RRflag = 1 or 2 and STADD = 3. As shown in FIG. 19A, in the case of STADD = 0, the start point (ADD = 0) of one cycle in which the address value ADD circulates from 0 to 13 coincides with the rising edge of the sensor signal SSD, and the address The end point (ADD = 13) of one cycle of the value ADD coincides with the falling edge of the sensor signal SSD. On the other hand, as shown in FIG. 19B, when STADD = 3, the start point (ADD = 0) and end point (ADD = 13) of one cycle in which the address value ADD circulates from 0 to 13 are Each is shifted to a position earlier in time by the start address value STADD than the rising edge and falling edge of the sensor signal SSD. Therefore, the temporal positions of the rising edge and falling edge of the sensor signal SSD and the boundary of one cycle of the signal S1 (ADD = 0) can be set at different positions. The “time position of the rising edge and the time position of the falling edge” of the sensor signal SSD corresponds to the “time position of the boundary of the period of the position signal” in the present invention. The “boundary” corresponds to “a temporal position of the boundary of the period of the PWM signal” in the present invention.

  FIG. 20 is a block diagram showing the internal configuration of the PWM signal generator 350. The PWM signal generation unit 350 includes a down counter unit 352, a rotation direction control unit 354, and an EXOR circuit 356. These operate as follows.

  FIG. 21 is a timing chart showing changes in various signals during normal rotation of the motor. FIG. 21 shows a case where STADD = 0. Therefore, the polarity signal Px has the same waveform as the sensor signal SSD. FIG. 21 shows a polarity signal Px (= sensor signal SSD), an address reset signal ADDrst, two clock signals CLKadd and CLKpwm, an address value ADD, a pulse width WD, and a count value in the down counter section 352. CM, output S1 of the down counter unit 352, forward / reverse direction command value signal RI, output S2 of the EXOR circuit 356, and output signals PWM1 and PWM2 of the rotation direction control unit are shown. In FIG. 21, for convenience of explanation, the frequency division values M = 5 and N = 5 are illustrated. The down counter unit 352 (FIG. 20) repeats the operation of down-counting the count value CM to 0 in synchronization with the PWM clock signal CLKpwm for each period of the address clock signal CLKadd. The initial value of the count value CM is set to the value of the pulse width WD. The output S1 of the down counter unit 352 is set to a high level when the count value CM is not 0, and falls to a low level when the count value CM becomes 0.

  The EXOR circuit 356 outputs a signal S2 indicating an exclusive OR of the polarity signal Px and the forward / reverse direction command value signal RI. When the motor rotates normally, the forward / reverse direction command value signal RI is at a low level. Therefore, the output S2 of the EXOR circuit 356 is the same signal as the polarity signal Px. The rotation direction control unit 354 generates PWM signals PWM1 and PWM2 from the output S1 of the down counter unit 352 and the output S2 of the EXOR circuit 356. That is, out of the output S1 of the down counter unit 352, the output S1 during the period in which the output S2 of the EXOR circuit 356 indicates the high level is output as the first PWM signal PWM1, and the period in which the output S2 indicates the low level. Is output as the second PWM signal PWM2.

  FIG. 22 is a timing chart showing changes in various signals during reverse rotation of the motor. During reverse rotation of the motor, the forward / reverse direction command value signal RI is set to a high level. As a result, the two drive signals DRVA1 and DRVA2 are interchanged from FIG. 21, and as a result, it can be understood that the motor reverses.

  FIG. 23A is a block diagram showing the internal configuration of the excitation interval restriction unit 360. FIG. 23B is a timing chart showing changes in various signals. The excitation section restriction unit 360 includes two AND circuits 362 and 364. The excitation interval signal Enb is a signal generated by the excitation interval signal generator 370 (FIG. 11), and sets the high level period as the excitation interval EP and sets the low level period as the non-excitation interval NEP. The excitation section EP is a section in which the PWM signals PWM1, 2 are valid as the drive signals DRVA1, 2, and the non-excitation section NEP is a section in which the PWM signals PWM1, 2 are invalid as the drive signals DRVA1,2. That is, the first AND circuit 362 outputs a drive signal DRVA1 indicating a logical product of the excitation interval signal Enb and the PWM signal PWM1, and the second AND circuit 364 is a drive indicating a logical product of the excitation interval signal Enb and the PWM signal PWM2. The signal DRVA2 is output. A method for generating the excitation interval signal Enb will be described later. In FIG. 23B, the excitation interval signal Enb is at the low level in the vicinity where the sensor signal SSD shifts from the high level to the low level and in the vicinity where the sensor signal SSD shifts from the low level to the high level. NEP is set. Accordingly, in this non-excitation interval NEP, none of the drive signals DRVA1, DRVA2 is output and the high impedance state is maintained.

  FIG. 24 is a block diagram illustrating an internal configuration of the excitation interval signal generation unit 370. The excitation interval signal generation unit 370 includes a start value setting unit 371, an end value setting unit 372, and a window comparator 373. The start value setting unit 371 receives the speed signal RRflag and sets a start value ST according to the value of the speed signal RRflag. The start value ST is a value indicating the timing when the excitation interval signal Enb becomes high level. The end value setting unit 372 receives the speed signal RRflag and sets an end value ED according to the value of the speed signal RRflag. The end value ED is a value indicating the timing at which the excitation interval signal Enb falls from the high level to the low level.

  The window comparator 373 receives the address value ADD, the start value ST, and the end value ED, and outputs an excitation interval signal Enb. That is, the window comparator 373 outputs the excitation interval signal Enb as a high level when the address value ADD is not less than the start value ST and not more than the end value ED. On the other hand, the window comparator 373 outputs the excitation interval signal Enb as a low level when the address value ADD is less than the start value ST and when the address value ADD is greater than the end value ED.

  FIG. 25 is a timing chart showing the excitation interval signal Enb when RRflag = 0 and STADD = 0. In FIG. 25, in addition to the excitation interval signal Enb, a sensor signal SSD, an address clock signal CLKadd, a PWM clock signal CLKpwm, and an address value ADD are described for reference. The same applies to FIGS. 26 to 29 described below. In this embodiment, when RRflag = 0, ST = 0 and ED = 13 are set. Therefore, the excitation interval signal Enb shows a high level in all the periods from 0 to 13 of the address value ADD.

  FIG. 26 is a timing chart showing the excitation interval signal Enb when RRflag = 1 and STADD = 0. When RRflag = 1, ST = 2 and ED = 11 are set. Therefore, the excitation interval signal Enb shows a high level during a period in which the address value ADD is from 2 to 11.

  FIG. 27 is a timing chart showing the excitation interval signal Enb when RRflag = 2 and STADD = 0. When RRflag = 2, ST = 3 and ED = 10 are set. Therefore, the excitation interval signal Enb shows a high level during the period in which the address value ADD is from 3 to 10.

  FIG. 28 is a timing chart showing the excitation interval signal Enb when RRflag = 3 and STADD = 0. When RRflag = 3, ST = 2 and ED = 9 are set. Therefore, the excitation interval signal Enb shows a high level during the period from the address value ADD of 2 to 9.

  FIG. 29 is a timing chart showing the excitation interval signal Enb when RRflag = 3 and STADD = 3. When RRflag = 3, ST = 2 and ED = 9 are set. Therefore, the excitation interval signal Enb shows a high level during the period from the address value ADD of 2 to 9. Here, since the start address value STADD is set to 3, the address value ADD is 3 at the rising edge of the sensor signal SSD.

  If the excitation interval signal generation unit 370 is configured as described above, it is possible to realize advance angle control that advances the phase of the excitation interval signal Enb relative to the sensor signal SSD and delay angle control that delays the phase.

  As described above, in the first embodiment, the starting point at which the address value ADD starts to circulate (that is, the timing when the address value ADD = 0) and the temporal positions of the rising edge and the falling edge of the sensor signal SSD (that is, In other words, the advance angle control and the retard angle control of the PWM signals PWM1, 2 and the excitation interval signal Enb can be realized. The address forming unit 330 corresponds to the address value setting unit in the present invention.

B. Second embodiment:
FIG. 30 is an explanatory diagram showing the configuration of the drive signal generator 240b in the second embodiment. The difference from the first embodiment shown in FIG. 11 is that the internal configuration of the excitation interval signal generation unit 370b is different and the second pulse width WD2 in addition to the pulse width WD is different from the PWM signal generation unit 350b. It is only the point supplied and other structures are the same as the first embodiment. The PWM signal generator 350b selects and uses either the pulse width WD or the second pulse width WD2, and generates the PWM signals PWM1, 2 in the same manner as in the first embodiment.

  FIG. 31 is an explanatory diagram showing the internal configuration of the excitation interval signal generator 370b in the second embodiment. The excitation interval signal generation unit 370b includes a start value setting unit 371, an end value setting unit 372, a waveform generation unit 373b, a counter unit 374, and a waveform table unit 375.

  The start value setting unit 371 and the end value setting unit 372 operate in the same manner as in the first embodiment shown in FIG. The waveform generation unit 373b receives the address value ADD, the start value ST, and the end value ED, and generates the excitation interval signal Enb in the same manner as the window comparator 373 (FIG. 24) in the first embodiment. The waveform generator 373b further generates a sub-address reset signal SUBADDrst indicating a high level when the address value ADD is 0, and indicating a low level when the address value ADD is other than 0.

  An address clock signal CLKadd is input to the clock terminal of the counter unit 374, a signal obtained by inverting the subaddress reset signal SUBADDrst is input to the reset terminal, and an excitation interval signal Enb is input to the enable terminal. Has been. That is, the counter unit 374 counts the pulses of the address clock signal CLKadd during the period when the excitation interval signal Enb is at a high level, and outputs the subaddress value SUBADD. The subaddress value SUBADD is reset to 0 at the timing when the inverted signal of the subaddress reset signal SUBADDrst falls to a low level.

  The waveform table unit 375 stores the second pulse width WD2, and outputs the second pulse width WD2 according to the value of the input subaddress value SUBADD. As described above, the second pulse width WD2 is supplied to the PWM signal generator 350b (FIG. 30). The PWM signal generator 350b can generate the PWM signals PWM1 and PWM2 using the second pulse width WD2 instead of the pulse width WD. That is, the waveform table unit 375 functions as a pulse width setting unit. In the second embodiment, the excitation interval restriction unit 360 (FIG. 30) may be omitted.

  FIG. 32 is a timing chart showing various signals in the excitation interval signal generator 370b. FIG. 32 shows a case where RRflag = 1 and STADD = 0. In this embodiment, when RRflag = 1, ST = 2 and ED = 11 are set. Further, since STADD = 0, the temporal position where the address value ADD indicates 0 coincides with the rising edge or falling edge of the sensor signal SSD.

  A signal obtained by inverting the sub address reset signal SUBADDrst indicates a low level when the address value ADD indicates 0, and indicates a high level when the address value ADD indicates a value other than 0. The excitation interval signal Enb indicates a high level during a period in which the address value ADD is from 2 to 11. The value of the subaddress value SUBADD increases in synchronization with the pulse of the address clock signal CLKadd only during the period in which the excitation interval signal Enb shows a high level. The value of the subaddress value SUBADD is reset when a signal obtained by inverting the subaddress reset signal SUBADDrst shows a low level. A value corresponding to the value of the subaddress value SUBADD is output as the value of the second pulse width WD2. Here, WD is set to 0 during the period in which the excitation interval signal Enb indicates a low level. Therefore, the PWM signals PWM1 and PWM2 are generated only during the excitation interval EP, and a reduction in power consumption of the motor can be realized.

  FIG. 33 is a timing chart showing various signals in the excitation interval signal generator 370b. FIG. 33 shows a case where RRflag = 1 and STADD = 3. The difference from the timing chart shown in FIG. 32 is that since STADD = 3, the temporal position where the address value ADD is 0 is shifted from the rising edge or falling edge of the sensor signal SSD. . Therefore, the signal obtained by inverting the sub address reset signal SUBADDrst, the excitation interval signal Enb, the sub address value SUBADD, and the second pulse width WD2 are shifted by the same amount as the amount by which the address value ADD is shifted.

  Even if the excitation interval signal generator 370b is configured as described above, the advance angle control and the retard angle control of the PWM signals PWM1 and PWM2 can be realized as in the first embodiment. In addition, since no PWM signal is generated in the non-excitation section NEP, the power consumption of the motor can be reduced.

  The waveform generation unit 373b (FIG. 31) corresponds to the excitation interval setting unit in the present invention, and the counter unit 374 (FIG. 31) and the waveform table unit 375 (FIG. 31) correspond to the pulse width setting unit in the present invention. To do.

C. Third embodiment:
FIG. 34A is a block diagram showing the internal configuration of the pulse width setting unit 340b in the third embodiment. FIG. 34B is a table showing the results of calculations until the pulse width setting unit 340b calculates the pulse width WD from the address value ADD. The only difference from the first embodiment shown in FIG. 18 is that the generation method of the pulse width WD is different, and the other overall configuration is the same as that of the first embodiment.

The pulse width setting unit 340b includes a normalization unit 382, a calculation unit 384, and a calculation coefficient setting unit 386. The normalizing unit 382 is connected to the divided value storage unit 318. The normalizing unit 382 normalizes the address value ADD into the range of 0 to 1 according to the following equation (8) using the divided value M to obtain the normalized value X.
X = ADD / (M−1) (8)

The calculation coefficient setting unit 386 sets the coefficient K0 used in the calculation unit 384 according to the value of the speed signal RRflag. Note that the value of the coefficient K0 stored in the calculation coefficient setting unit 386 is preferably rewritable by the CPU 220 to an arbitrary value. The calculation unit 384 receives the normalized value X and obtains the pulse width WD according to the following equation (9).
WD = K0 × sin (X · π) (9)
However, in the table shown in FIG. 34B, the calculation is performed with the coefficient K0 = 15. Here, the coefficient K0 is preferably a value that does not exceed the frequency division value N. This is because even if the pulse width WD is set exceeding the resolution of the pulse generated by the PWM signal generation unit 350, the PWM signal generation unit 350 cannot generate a pulse corresponding to the pulse width WD. Further, the pulse width WD output from the calculation unit 384 is a value as an integer obtained by rounding off the value obtained by the above equation (9).

  As described above, the pulse width WD can be calculated by the calculation unit 384 that performs calculation using the sin function.

D. Fourth embodiment:
FIG. 35A is a block diagram showing the internal configuration of the pulse width setting unit 340c in the third embodiment. FIG. 35 (B) is a table showing the results of calculation until the pulse width setting unit 340c calculates the pulse width WD from the address value ADD. The only difference from the second embodiment shown in FIG. 34 is that the number of coefficients used for the calculation and the calculation expression of the calculation unit 384c are different, and the other overall configuration is the same as that of the second embodiment. It is.

The pulse width setting unit 340c includes a normalization unit 382, a calculation unit 384c, and a calculation coefficient setting unit 386c. The calculation coefficient setting unit 386c sets the five coefficients K0, K1, K2, K3, and K4 used in the calculation unit 384c according to the speed signal RRflag. As in the second embodiment, the calculation coefficient setting unit 386c and the CPU 220 are connected, and the values of the five coefficients K0, K1, K2, K3, and K4 stored in the calculation coefficient setting unit 386c are arbitrarily set. It is preferable that the value can be rewritten. The calculation unit 384c receives the normalized value X and obtains the pulse width WD according to the following equation (10).
WD = K0 × (K1 · X ³ + K2 · X ² + K3 · X + K4) (10)
However, in this third embodiment, the coefficients are K0 = 15, K1 = −2.270 × 10 ⁻¹³ , K2 = −4.685, K3 = 4.350, K4 = −3.286 × 10 ^−2. The pulse width WD is obtained using the value of. Note that the pulse width WD output from the calculation unit 384 is a value as an integer obtained by rounding off the value obtained by the above equation (10). If the calculation result of the pulse width WD shows a negative value, the pulse width WD is output as WD = 0.

  As described above, the pulse width WD can be calculated by the calculation unit 384c that performs calculation using a cubic function.

E. Example 5:
FIG. 36 is an explanatory diagram showing the configuration of the PLL circuit 307b realized by a digital circuit. The PLL circuit 307b includes a counter unit 402, a storage unit 404, a calculation unit 406, a storage unit 408, a counter unit 410, a storage unit 412, and a frequency divider 414. The counter unit 402 counts the number of pulses of the reference clock signal CLKorg in the half cycle of the sensor signal SSD. The storage unit 404 stores the number of pulses of the reference clock signal CLKorg in the half cycle of the sensor signal SSD as the count value Cn.

The storage unit 412 stores a coefficient value M and a coefficient value N. This coefficient value N is the same value as the frequency division value N of the frequency divider 414. The calculation unit 406 calculates a calculation value MNx according to the following equation (11).
MNx = int (Cn / MN) (11)
Here, “int” indicates that the integer part of the value is extracted. The storage unit 408 stores the calculated value MNx. The counter unit 410 divides the reference clock signal CLKorg by the calculated value MNx to generate the PWM clock signal CLKpwm. The frequency divider 414 divides the PWM clock signal CLKpwm by the frequency division value N to generate the address clock signal CLKadd.

Therefore, the relationship between the frequency fSSD of the sensor signal SSD, the frequency fCLKadd of the address clock signal CLKadd, and the frequency fCLKpwm of the PWM clock signal CLKpwm is expressed by the following equations (12) and (13).
fCLKadd = fSSD × 2 × M (12)
fCLKpwm = fCLKadd × N (13)

  Thus, instead of the PLL circuit 307 (FIG. 12) shown in the first embodiment, a PLL circuit 307b composed of a digital circuit can be used.

F. Variation:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

F1. Modification 1:
The present invention is applicable to various devices. For example, the present invention can be applied to motors of various devices such as a fan motor, a clock (hand drive), a drum-type washing machine (single rotation), a roller coaster, and a vibration motor. When the present invention is applied to a fan motor, the various effects described above (low power consumption, low vibration, low noise, low rotation unevenness, low heat generation, long life) are particularly remarkable. Such fan motors are, for example, various devices such as digital display devices, in-vehicle devices, fuel cell computers, fuel cell digital cameras, fuel cell video cameras, fuel cell mobile phones, and other fuel cell equipment. It can be used as a fan motor for the device. The motor of the present invention can also be used as a motor for various home appliances and electronic devices. For example, the motor according to the present invention can be used as a spindle motor in an optical storage device, a magnetic storage device, a polygon mirror drive device, or the like. The motor according to the present invention can also be used as a motor for a moving body or a robot.

  FIG. 37 is an explanatory diagram showing a projector using a motor according to an embodiment of the present invention. The projector 3100 includes three light sources 3110R, 3110G, and 3110B that emit red, green, and blue color lights, and three liquid crystal light valves 3140R, 3140G, and 3140B that modulate these three color lights, respectively. A cross dichroic prism 3150 that synthesizes the modulated three-color light, a projection lens system 3160 that projects the combined three-color light onto the screen SC, a cooling fan 3170 for cooling the inside of the projector, and a projector 3100 And a control unit 3180 for controlling the whole. As the motor for driving the cooling fan 3170, the various brushless motors described above can be used.

  FIGS. 38A to 38C are explanatory views showing a fuel cell type mobile phone using a motor according to an embodiment of the present invention. FIG. 38A illustrates an appearance of the mobile phone 3200, and FIG. 38B illustrates an example of an internal configuration. The mobile phone 3200 includes an MPU 3210 that controls the operation of the mobile phone 3200, a fan 3220, and a fuel cell 3230. The fuel cell 3230 supplies power to the MPU 3210 and the fan 3220. The fan 3220 is used to blow air from the outside of the mobile phone 3200 to supply air to the fuel cell 3230 or to discharge moisture generated by the fuel cell 3230 from the inside of the mobile phone 3200 to the outside. It is. Note that the fan 3220 may be disposed on the MPU 3210 as shown in FIG. 38C to cool the MPU 3210. As the motor that drives the fan 3220, the various brushless motors described above can be used.

  FIG. 39 is an explanatory diagram showing an electric bicycle (electrically assisted bicycle) as an example of a moving body using a motor / generator according to an embodiment of the present invention. In this bicycle 3300, a motor 3310 is provided on the front wheel, and a control circuit 3320 and a rechargeable battery 3330 are provided on a frame below the saddle. The motor 3310 assists traveling by driving the front wheels using the electric power from the rechargeable battery 3330. In addition, the electric power regenerated by the motor 3310 is charged in the rechargeable battery 3330 during braking. The control circuit 3320 is a circuit that controls driving and regeneration of the motor. As the motor 3310, the various brushless motors described above can be used.

  FIG. 40 is an explanatory diagram showing an example of a robot using a motor according to an embodiment of the present invention. The robot 3400 includes first and second arms 3410 and 3420 and a motor 3430. The motor 3430 is used when horizontally rotating the second arm 3420 as a driven member. As the motor 3430, the above-described various brushless motors can be used.

  FIG. 41 is an explanatory diagram showing a railway vehicle using a motor according to an embodiment of the present invention. The railway vehicle 3500 has a motor 3510 and wheels 3520. The motor 3510 drives the wheel 3520. Further, the motor 3510 is used as a generator during braking of the railway vehicle 3500, and electric power is regenerated. As the motor 3510, the above-described various brushless motors can be used.

F2. Modification 2:
In the first embodiment, the pulse width WD is set so as to simulate the counter electromotive force waveform. Instead, the pulse width WD is set so as to simulate a sine waveform or a Gaussian waveform. It is also possible to do. Further, when setting the pulse width WD, the pulse width WD may be set so that the minimum value of the pulse width WD except 0 is 50% or less of the maximum value of the pulse width WD. preferable. If the pulse width WD is set in this way, the electric motor can be driven efficiently.

F3. Modification 3:
The circuit in the above embodiment can also be realized by a circuit in which the high level and the low level are inverted.

F4. Modification 4:
In the above-described embodiment, the binary digital output magnetic sensor 40 is used, but an analog output Hall sensor can be used instead. In this case, the analog output is preferably converted into a binary digital output by a comparator.

F5. Modification 5:
In the above embodiment, a single-phase brushless motor has been described, but instead, a two-phase or three-phase or more brushless motor may be mounted with the drive control circuit.

F6. Modification 6:
Although the rotary motor has been described in the above embodiment, a linear motor may be mounted with the drive control circuit instead.

It is sectional drawing which shows the structure of the motor main body of the single phase brushless motor as one Example of this invention. It is explanatory drawing which shows the positional relationship of a magnet row | line | column and a coil row | line | column, and the relationship between a magnetic sensor output and the counter electromotive force waveform of a coil. It is a schematic diagram which shows the relationship between the applied voltage of a coil, and a counter electromotive force. It is explanatory drawing which shows the mode of the normal rotation operation | movement of a motor main body. It is explanatory drawing which shows the mode of reverse rotation operation | movement of a motor main body. It is a flowchart which shows the control procedure of the moving direction of a motor. It is a block diagram which shows the structure of the drive control circuit of the brushless motor of a present Example. The internal structure of a driver circuit is shown. It is explanatory drawing which shows the other structure of a driver circuit. Various winding methods of the electromagnetic coil are shown. It is explanatory drawing which shows the internal structure of a drive signal generation part. 3 is a block diagram showing an internal configuration of a control signal generation unit, and a timing chart showing changes in various signals. FIG. It is a block diagram which shows the internal structure of an address formation part. It is a timing chart which shows the various signals in an address formation part. It is a timing chart which shows the various signals in an address formation part. It is a circuit diagram which shows the internal structure of a polarity signal generation part. It is a timing chart which shows the various signals in a polarity signal generation part. It is a block diagram which shows the internal structure of a pulse width setting part, and a timing chart which shows the change of various signals. 4 is a timing chart showing various signals when STADD = 0, and a timing chart showing various signals when STADD = 3. It is a block diagram which shows the internal structure of a PWM signal generation part. It is a timing chart which shows change of various signals at the time of motor normal rotation. It is a timing chart which shows change of various signals at the time of motor reverse rotation. 5 is a block diagram showing an internal configuration of an excitation interval restriction unit, and timing charts showing changes in various signals. It is a block diagram which shows the internal structure of an excitation area signal generation part. It is a timing chart which shows the excitation area signal Enb in the case of RRflag = 0 and STADD = 0. It is a timing chart which shows the excitation area signal Enb in the case of RRflag = 1 and STADD = 0. It is a timing chart which shows the excitation area signal Enb in the case of RRflag = 2 and STADD = 0. It is a timing chart which shows the excitation area signal Enb in the case of RRflag = 3 and STADD = 0. It is a timing chart which shows the excitation area signal Enb in the case of RRflag = 3 and STADD = 3. It is explanatory drawing which shows the structure of the drive signal generation part in 2nd Example. It is explanatory drawing which shows the internal structure of the excitation area signal generation part in 2nd Example. It is a timing chart which shows the various signals in an excitation area signal generation part. It is a timing chart which shows the various signals in an excitation area signal generation part. It is a block diagram which shows the internal structure of the pulse width setting part in 3rd Example, and the table | surface which shows the result of the calculation until a pulse width setting part calculates pulse width WD from address value ADD. It is a block diagram which shows the internal structure of the pulse width setting part in 4th Example, and the table | surface which shows the result of the calculation until a pulse width setting part calculates pulse width WD from address value ADD. It is explanatory drawing which shows the structure of the PLL circuit implement | achieved with the digital circuit. It is explanatory drawing which shows the projector using the motor by the Example of this invention. It is explanatory drawing which shows the fuel cell type mobile telephone using the motor by the Example of this invention. It is explanatory drawing which shows the electric bicycle (electric assisted bicycle) as an example of the moving body using the motor / generator by the Example of this invention. It is explanatory drawing which shows an example of the robot using the motor by the Example of this invention. It is explanatory drawing which shows the rail vehicle using the motor by the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Stator part 11-14 ... Electromagnetic coil 20 ... Magnetic yoke 30 ... Rotor part 31-34 ... Permanent magnet 36 ... Magnetic yoke 40 ... Magnetic sensor 100 ... Motor main body 102 ... Casing 112 ... Rotating shaft 114 ... Bearing part 120 ... Circuit Substrate 200 ... Drive control circuit 220 ... CPU
240 ... Drive signal generator 240b ... Drive signal generator 250 ... Driver circuit 250a ... First bridge circuit 250b ... Second bridge circuit 251 ... Transistor 252 ... Transistor 300 ... Control signal generator 302 ... Reference clock signal generator 304 ... Speed signal generator 306 ... Edge detector 307 ... PLL circuit 307b ... PLL circuit 308 ... Phase comparator 310 ... Loop filter 311 ... Level shifter 312 ... Voltage controlled oscillator 314 ... First frequency divider 316 ... Second frequency divider 318 ... divided value storage unit 320 ... forward / reverse direction command value storage unit 330 ... address forming unit 331 ... counter unit 332 ... maximum count value storage unit 333 ... start address value storage unit 334 ... address value calculation unit 335 ... polarity signal generation unit 337 ... Dee flip-flop 338 ... Inverted signal Generation unit 339 ... permission signal generation unit 340 ... pulse width setting unit 340b ... pulse width setting unit 340c ... pulse width setting unit 342 ... table selection unit 344 ... first table unit 346 ... second table unit 348 ... third Table unit 350 ... PWM signal generation unit 350b ... PWM signal generation unit 352 ... Down counter unit 354 ... Rotation direction control unit 356 ... EXOR circuit 360 ... Excitation section restriction unit 370 ... Excitation section signal generation section 370b ... Excitation section signal generation section 371 ... start value setting section 372 ... end value setting section 373 ... window comparator 373b ... waveform generation section 374 ... counter section 375 ... waveform table section 382 ... normalization section 384 ... calculation section 384c ... calculation section 386 ... calculation coefficient setting section 386c ... Calculation coefficient setting unit 400... Bus 402. ... storage unit 406 ... calculation unit 408 ... storage unit 410 ... counter unit 412 ... storage unit 414 ... frequency divider 3100 ... projector 3110R ... light source 3140R ... liquid crystal light valve 3150 ... cross dichroic prism 3160 ... projection lens system 3170 ... cooling fan 3180 ... Control unit 3200 ... Mobile phone 3220 ... Fan 3230 ... Fuel cell 3300 ... Bicycle 3310 ... Motor 3320 ... Control circuit 3330 ... Rechargeable battery 3400 ... Robot 3410 ... First arm 3420 ... Second arm 3430 ... Motor 3500 ... Railway vehicle 3510 ... Motor 3520 ... Wheel

Claims (12)

A circuit for driving an electric motor,
Based on a periodic position signal indicating the relative positions of the first and second driving members of the electric motor, a periodic PWM signal is generated as a driving signal for driving the electric motor,
A circuit capable of setting a temporal position of a boundary of a period of the PWM signal to a position different from a temporal position of a boundary of a period of the position signal. The circuit of claim 1, comprising:
An address value setting unit that divides each half cycle of the position signal into a predetermined number of sections and sets an address value that circulates in the predetermined number for each of the divided sections;
A pulse width setting unit for setting a pulse width for performing PWM control for each of the divided sections based on the address value;
A PWM signal generation unit that generates the PWM signal by performing PWM control for each of the divided sections based on the pulse width;
With
The circuit, wherein the address value setting unit sets the address value so that a temporal position where the address value starts to circulate is different from a temporal position of a boundary of the period of the position signal. The circuit of claim 2, further comprising:
An excitation interval setting unit that determines an excitation interval in which the PWM signal is valid as the drive signal based on the address value;
The pulse width setting unit is configured to set the pulse width so that the PWM signal is generated in a section set as the excitation section among the divided sections. A circuit according to any one of claims 1 to 3,
The circuit, wherein the pulse width setting unit sets the pulse width so that a minimum value of the pulse width excluding 0 is 50% or less with respect to the maximum value of the pulse width. A circuit according to any one of claims 1 to 3,
The pulse width setting unit sets the pulse width so that an effective waveform of the PWM signal has a shape simulating a sine waveform. A circuit according to any one of claims 1 to 3,
The pulse width setting unit sets the pulse width so that an effective waveform of the PWM signal has a shape simulating a Gaussian waveform.   An electric motor comprising the circuit according to claim 1.   An apparatus comprising the electric motor according to claim 7. The apparatus according to claim 8, comprising:
The device is an electronic device. The apparatus according to claim 8, comprising:
The device is a projector. The apparatus according to claim 8, comprising:
The device is a moving body. The apparatus according to claim 8, comprising:
The device is a robot.

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