JP2010019983A - Vfd driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a VFD (Vacuum Fluorescent Display) driving device, improving the accuracy of voltage stabilizing control by reducing the processing load of a microcomputer. <P>SOLUTION: Upper limit data and lower limit data for determining an upper limit value and a lower limit value of tolerance are set in an upper limit data register 15U and a lower limit data register 15D, respectively, concerning a target value for controlling the filament voltage of VFD 1. Comparators 14U and 14D compare the voltage data obtained by A-D converting the filament voltage with the upper limit value data and the lower limit data set in the registers 15U and 15D, and a data adjusting computing unit 22 adjusts a data value stored in a DUTY register 20 based on the comparison results of the comparators 14U and 14D. When a PWM (Pulse Width Modulation) signal is generated according to the data value set in the DUTY register 20, a CYC (cycling) register 21 outputs it to a filament of the VFD. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a VFD driving apparatus that performs display by driving a VFD (Vacuum Fluorescent Display) by PWM (Pulse Width Modulation) control.

When display control is performed by driving a VFD (fluorescent display tube) that performs self-luminous display, it is important to stabilize the voltage applied to the filament (cathode electrode) in order to suppress flicker. In this case, how to stabilize the voltage varies depending on the number of filaments to which the voltage is applied, the power consumption of the VFD, and the like, but the influence of the load fluctuation on the voltage stabilization is large. Therefore, generally, the duty of the PWM signal is adjusted by reading the filament voltage value with a microcomputer or the like and performing feedback control (see, for example, Patent Document 1).
JP 2003-5713 A

  In order to improve the accuracy of voltage stabilization, the time resolution in the feedback control may be improved. However, if the microcomputer is controlled by a program as in Patent Document 1, the processing load increases, and the microcomputer (CPU) is connected to the VFD. I have to dedicate myself to drive control. As a result, flexible control that is appropriate to be implemented by a microcomputer program cannot be distributed to other processes.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a VFD driving device capable of reducing the processing load of a microcomputer and improving the accuracy of voltage stabilization control.

  According to the VFD driving device of claim 1, the upper limit data register and the lower limit data register have upper limit data and lower limit data for determining an upper limit value and a lower limit value of an allowable range for a target value for controlling the filament voltage of the VFD, respectively. The upper limit comparator and the lower limit comparator compare the voltage data obtained by A / D converting the VFD filament voltage, and the upper limit data and the lower limit data set in the upper limit data register and the lower limit data register, respectively. Then, the arithmetic unit for data adjustment adjusts the data value stored in the duty register based on the comparison result by the upper limit comparator and the lower limit comparator, and the PWM signal generation means sets the data value set in the duty register to the data value set in the duty register. If a PWM signal is generated accordingly, it is output to the VFD filament. With such a configuration, the feedback control of the filament voltage can be performed by hardware, and the program control by the CPU becomes unnecessary, so that the CPU processing capacity can be largely divided into other functions.

  According to the VFD driving device of the second aspect, the decoding circuit constituting the arithmetic unit decodes the comparison result by the upper limit comparator and the lower limit comparator, and the multiplexer outputs data having different values according to the decoding result. Select and output. The adder adds the data output from the multiplexer and the data in the duty register and outputs the result to the register. That is, the data value of the duty register can be increased or decreased by selectively changing the data output from the multiplexer to the adder according to the comparison result between the A / D conversion data of the filament voltage and the upper limit value data and the lower limit value data. it can.

  Hereinafter, an embodiment of the present invention applied to, for example, a VFD arranged and displayed on an instrument panel of a vehicle will be described with reference to the drawings. FIG. 2 shows a VFD and a peripheral circuit for driving the VFD. The VFD 1 (including the driver) displays a plurality of numbers in, for example, 7 segments. In the present embodiment, the VFD 1 (for example, a driver) that displays by static driving is targeted. When the battery voltage (for example, 12V) of the vehicle is supplied via the power terminal ACC, the power circuit 2 generates and outputs a driving voltage of, for example, 10.8V.

  The filament pulse drive circuit 3 is supplied with the drive voltage and outputs a PWM signal having a carrier frequency of, for example, about 20 kHz to the filament of VFD1 via the terminal F +, and is supplied with the drive voltage of 10.8V. . A terminal F− of the VFD 1 is connected to the ground, and a drive voltage of 10.8V is applied to the terminal G. The VFD driver control ICs 4A and 4B are supplied with the drive voltage and, for example, a drive voltage VDD of 5V. The VFD driver control ICs 4A and 4B convert the display data DATA serially given to the input terminal DIN from the control IC 5 in synchronization with the clock into parallel data and transfer it to the driver of the VFD 1.

  Note that the input terminal DIN of the VFD driver control IC 4B is connected to the output terminal DOUT of the VFD driver control IC 4A, and the display data of the VFD driver control ICs 4A and 4B are collectively output serially by the control IC 5. The control IC 5 outputs a data latch signal LS and a data clear signal CL to the VFD driver control IC 4.

  The control IC 5 outputs a PWM signal from the output terminal FPWM to the filament pulse drive circuit 3 in order to control the display brightness of the VFD 1. The terminal F + of VFD1 is connected to the input terminal FADIN of the control IC 5 through the resistance element R, and the input terminal FADIN is connected to the ground through the capacitor C. That is, when the filament voltage (PWM signal) at the terminal F + is smoothed by the resistance element R and the capacitor C and given to the control IC 5, it is A / D converted as described later. A diode D in the reverse direction is connected between the power supply VDD and the common connection point of the resistance element R and the capacitor C.

  FIG. 1 shows the configuration of the control IC 5 with respect to the part according to the gist of the present invention. The control IC 5 includes a CPU 11 and a display control unit 12 that performs display control of the VFD 1 by hardware. When the A / D converter 13 constituting the display control unit 12 performs A / D conversion on the analog voltage applied to the input terminal FADIN, the converted data is stored in the data register. The data stored in the data register is output to comparators (magnitude comparators) 14U and 14D.

  Comparators 14U, 14D (upper limit comparator, lower limit comparator) are data ADC A / D converted by A / D converter 13, and upper limit data DU, lower limit set in upper limit data register 15U, lower limit data register 15D. The size is compared with the data DD, and the comparison result is output to the decoding circuit 16. The decode circuit 16 decodes the comparison results of the comparators 14U and 14D, and performs switching control of the multiplexers 17 and 18 connected in two stages. Setting data “+1” and “−1” are given to the input terminal of the first stage multiplexer 17, and setting data “0” and output data from the multiplexer 17 are input to the input terminal of the next stage multiplexer 18. And is given.

Here, the logic that the decode circuit 16 controls the multiplexers 17 and 18 is as follows.
ADC <DD → “+1” output to adder 19
ADC> DU → “-1” output to adder 19 DD ≦ ADC ≦ DU → “0” output to adder 19 The output data of multiplexer 18 is applied to one of the input terminals of adder 19, and the output of adder 19 is output. Data is stored in the DUTY register 20. The output data of the DUTY register 20 is supplied to the other input terminal of the adder 19 and is output to the CYC register 21 (PWM signal generating means).

  The CYC register 21 compares a counter that cyclically performs a counting operation corresponding to a PWM carrier period (50 μs) according to a given operation clock, and a value of the counter with a data value output from the DUTY register 20. A comparator and other logic circuits are built in. A high level is output until the counter value matches the data value of the DUTY register 20 from “0”, and when the counter value matches the data value of the DUTY register 20, the output level is changed. A PWM signal is output by inverting it to low. In the above description, the decode circuit 16, the multiplexers 17 and 18, and the adder 19 constitute an arithmetic unit 22.

Next, the operation of the present embodiment will be described with reference to FIG. FIG. 3A is a voltage waveform observed at point A in FIG. 1: input terminal FADIN of the control IC 5, and FIG. 3B is a duty change of the PWM signal output from the output terminal FPWM of the control IC 5. Indicates. First, the CPU 11 sets the duty command value of the PWM signal corresponding to the filament voltage corresponding to the display brightness of the VFD 1 in the DUTY register 20.
This duty command value is set by the user or according to the determination of the time zone by turning on / off the light switch (relatively bright during the day and dark at night). Accordingly, the upper limit data and lower limit data for defining the upper limit value and the lower limit value are set in the upper limit data register 15U and the lower limit data register 15D for the allowable control range of the filament voltage.

Thereafter, the hardware of the display control unit 12 performs all processing without the CPU 11 being interposed. That is, as described above, when the A / D converter 13 A / D converts the filament voltage applied to the input terminal FADIN, the converted data is compared with the upper limit data and the lower limit data in the comparators 14U and 14D, respectively. The comparison result is output to the decode circuit 16.
The decode circuit 16 performs switching control of the multiplexers 17 and 18 according to the above-described logic according to the comparison results of the comparators 14U and 14D. Then, the data value given to the adder 19 changes to “−1”, “0”, “+1”, the data value stored in the DUTY register 20 is adjusted from the initial value, and the duty of the PWM signal is changed. Change.

  FIG. 3 shows a change when the initial value set in the DUTY register 20 is set to a duty of 15%. The control target value of the filament voltage is about 1.5V (calculated with a driving voltage of 10V), the upper limit value of the control range is set to 2.0V, and the lower limit value is set to about 1.0V. Moreover, the area | region of voltage 2.5V or more and the area | region of 0.5V or less are set to the abnormal voltage area | region.

When the control is started, the filament voltage gradually increases from 0V, and the PWM duty increases accordingly until the lower limit voltage is exceeded. The PWM duty does not change from when the filament voltage exceeds the lower limit voltage until it exceeds the upper limit voltage. When the filament voltage exceeds the upper limit voltage, the PWM duty starts to decrease from about 58% indicating the maximum value. The PWM duty does not change during the period between the two (allowable range). From this state, when the upper limit voltage is exceeded again, the PWM duty decreases and finally converges to around 15% of the initial value.
In addition, by preparing corresponding detection hardware separately, when the filament voltage reaches the abnormal voltage region, an abnormal process such as stopping the control is performed.

  As described above, according to this embodiment, the upper limit data register 15U and the lower limit data register 15D store the upper limit data and the lower limit data that define the upper limit value and the lower limit value of the allowable range for the target value for controlling the filament voltage of the VFD 1, respectively. The comparators 14U and 14D compare the voltage data obtained by A / D converting the filament voltage with the upper limit value data and the lower limit value data set in the registers 15U and 15D, respectively. Adjusts the data value stored in the DUTY register 20 based on the comparison results of the comparators 14U and 14D. When the CYC register 21 generates a PWM signal according to the data value set in the DUTY register 20, the VFD1 Output to the filament.

Accordingly, the feedback control of the filament voltage can be performed by the hardware of the display control unit 12 except for the data setting process for each of the registers 15 and 20, and the program control by the CPU 11 becomes almost unnecessary. It becomes possible to largely distribute to other functions.
Then, the decoding circuit 16 constituting the arithmetic unit 22 decodes the comparison results from the comparators 15U and 15D, and the multiplexers 17 and 18 determine the data values “−1”, “0”, “+1” according to the decoding results. "" To output. The adder 19 adds the data output from the multiplexers 17 and 18 and the data in the DUTY register 20 and outputs the result to the register 20. Therefore, the data value of the DUTY register 20 can be increased or decreased by selectively changing the data output from the multiplexers 17 and 18 to the adder 19.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The number of VFD driver control ICs may be one or three or more depending on the size of the VFD.
Data may be set in each register according to the result of the hardware determining the VFD brightness setting condition.
The increase / decrease value of the data selected by the multiplexers 17 and 18 is not limited to “1”, but may be set to a value of “2” or more.
The present invention can be widely applied without being limited to those arranged on the instrument panel of the vehicle.

The figure which is one Example of this invention, and shows the structure of control IC about the part which concerns on the summary of this invention The figure which shows VFD and the peripheral circuit for driving VFD (A) is a voltage waveform observed at point A in FIG. 1, (b) is a diagram showing a duty change of a PWM signal output from the output terminal FPWM of the control IC.

Explanation of symbols

  In the drawings, 1 is a VFD, 5 is a control IC, 11 is a CPU, 12 is a display control unit, 13 is an A / D converter, 14U and 14D are comparators (upper limit comparator and lower limit comparator), and 15U is an upper limit data register. , 15D is a lower limit data register, 16 is a decoding circuit, 17 and 18 are multiplexers, 19 is an adder, 20 is a DUTY register (duty register), 21 is a CYC register (PWM signal generating means), and 22 is an arithmetic unit.

Claims (2)

In a VFD driving device that performs display by driving a VFD (Vacuum Fluorescent Display) by PWM (Pulse Width Modulation) control,
An A / D converter for A / D converting the filament voltage of the VFD;
An upper limit data register and a lower limit data register in which upper limit data and lower limit data for determining an upper limit value and a lower limit value of the allowable range of the filament voltage are set;
An upper limit comparator and a lower limit comparator for comparing the voltage data A / D converted by the A / D converter with the upper limit value and the lower limit value data set in the upper limit data register and the lower limit data register, respectively;
A duty register storing data for setting the duty of the PWM signal;
An arithmetic unit for adjusting a data value stored in the duty register based on a comparison result by the upper limit comparator and the lower limit comparator;
A VFD driving device comprising: PWM signal generating means for generating the PWM signal according to the data value set in the duty register and outputting the PWM signal to the filament of the VFD. The computing unit is
A decoding circuit for decoding a comparison result by the upper limit comparator and the lower limit comparator;
A multiplexer that selects and outputs data of different values according to the decoding result by the decoding circuit,
2. The VFD driving device according to claim 1, comprising an adder that adds the data output from the multiplexer and the data of the duty register and outputs the sum to the duty register.

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