JP2010017067A - Electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To monitor input/output voltages of a regulator with a simple configuration. <P>SOLUTION: The circuit has the regulator 11 controlling an output voltage at a constant value with respect to an input voltage, a reset IC 12 detecting an abnormal input voltage to output a deasserted reset signal, a state output terminal detecting an abnormal output voltage to output a deasserted state signal, and a three-state buffer 13 outputting a deasserted enable signal when at least the deasserted reset or state signal is input. The regulator 11 stops the output in response to the deasserted enable signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic circuit including a regulator.

  In recent years, various portable electronic devices such as mobile phones and notebook computers have become widespread. Since these devices require various power supply voltages to drive the internal circuit, a power supply circuit using a regulator that keeps the power supply voltage at a constant value is used. As a result, various stable power supply voltages are generated, and stable power is supplied to the internal circuit.

  Such a regulator normally includes an overcurrent protection circuit, and the overcurrent protection circuit operates when the input voltage is abnormal (see, for example, Patent Document 1).

JP 2007-136495 A

  However, overcurrent protection circuits (fuses, polyswitches, etc.) are generally built in the primary side of the regulator, and only monitor the input voltage and often do not function effectively. Some use a power control unit such as a CPLD (Complex Programmable Logic Device), but it is not practical because it is expensive.

  The present invention has been proposed in view of such a conventional situation, and provides an electronic circuit capable of monitoring the input / output voltage of a regulator with a simple configuration.

  In order to achieve the above-described object, a potential circuit according to the present invention includes a regulator that controls an output voltage to be constant with respect to an input voltage, a first abnormality detection that detects an abnormality of the input voltage and is deasserted An input abnormality detection circuit that outputs a signal; an output abnormality detection circuit that detects an abnormality in the output voltage and outputs a deasserted second abnormality detection signal; and the deasserted first or second signal. A three-state buffer that outputs an enable signal deasserted in response to at least one of the abnormality detection signals; and a control circuit that controls the regulator to be turned off in response to the deasserted enable signal.

  According to the present invention, by using a three-state buffer that inputs an input voltage and an output voltage abnormality detection signal and outputs an enable signal, the input / output voltage of the regulator is monitored with a simple configuration. Can be turned off automatically.

  Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings. The electronic circuit shown as a specific example of the present invention is a regulator having an overcurrent protection function that monitors the input / output voltage of the regulator with a simple configuration and automatically turns off the power supply when the voltage is abnormal.

  The regulator is a circuit that controls the output voltage / current to be kept constant. Regulators are classified into two types, linear regulators and switching regulators, depending on the degree of power load. The linear regulator can always be controlled to a constant voltage as long as the output voltage is lower than the input voltage, and has a merit that the mechanism is simple and inexpensive. The switching regulator controls the output voltage to be constant by a switching mechanism. While linear regulators are used in relatively lightly loaded circuits, switching regulators are often used in heavily loaded devices such as microprocessors.

[First configuration example]
FIG. 1 is a block diagram showing a first configuration example of a regulator having an overcurrent protection function in an embodiment of the present invention. This electronic circuit includes a regulator 11, a reset IC (Integrated Circuit) 12 with a delay function, and a three-state buffer 13.

  The regulator 11 has an input voltage terminal and an output voltage terminal, and controls the output voltage to be constant. The regulator 11 also has an enable terminal for inputting an enable signal for controlling on / off (operation / standby) of the regulator 11. For this reason, for example, only the standby power supply can be operated during standby, and the main power supply can be turned on during use. Further, the regulator 11 has a state signal output terminal for outputting a state signal of the regulator 11, and outputs a deasserted state signal when a large current exceeding the rating flows in the output, thereby limiting the output current. To do. The deasserted status signal is also output when, for example, heat dissipation is insufficient and the chip temperature exceeds a specified value.

  The reset IC 12 with a delay function has an input voltage terminal and a reset signal output terminal, monitors the input voltage, and when the regulator 11 exceeds a voltage controllable range, the deasserted reset signal Is output to the three-state buffer 13. In addition, when the power is turned on, the reset signal is delayed and output to prevent an unexpected operation of the three-state buffer 13.

  The three-state buffer 13 has an input terminal for inputting a state signal, an enable terminal for inputting a reset signal, and an output terminal for outputting an enable signal. The three-state buffer 13 has a third output state of Hi-Z (high impedance state) in addition to the normal H (high level) and L (low level) output states. In the Z state, the output is neither H nor L, and the output terminal is almost equivalent to the state where the output terminal is disconnected from the internal output circuit. That is, the three-state buffer 13 switches the enable signal to assert (H) or deassert (L, Z) according to the state signal input and the reset signal input.

  Next, the operation of the electronic circuit of the first configuration example will be described with reference to FIG. In general, since the input terminal of the three-state buffer 13 has high internal impedance (high insulation with the power supply circuit), if the input terminal is not connected anywhere, an unexpected voltage due to nearby static electricity or electromagnetic induction May be applied. Therefore, as a precondition, the output delay time Ta of the reset IC 12 with delay function is set to be longer than the time Tb from when the regulator 11 is powered on until the state signal output is asserted.

  When the power is turned on, a specified input voltage is applied to the regulator 11 and the reset IC 12 at time t11, and a specified voltage is output from the regulator 11 (time t12).

  A state signal of the regulator 11 is asserted Tb time after the input voltage is applied to the regulator 11 (time t13). Further, a reset signal of the reset IC 12 is asserted Ta time after the input voltage is applied to the regulator 11 (time t14), and the asserted enable signal is output from the three-state buffer 13. Thereby, the normal operation of the regulator 11 is started.

  Here, when some abnormality occurs in the circuit and the output voltage from the regulator 11 decreases (time t15), the state signal is deasserted (time t16). The three-state buffer 13 deasserts the enable signal in response to the input of the deasserted state signal (time t17). Then, the regulator 11 stops the output in response to the deasserted enable signal (time t18).

  In addition, when an abnormality occurs in the power supply and the input voltage to the regulator 11 decreases and becomes lower than a threshold value at which the regulator 11 can be controlled to a constant value (time t19), the output voltage of the regulator 11 decreases (time). t20). As a result, the reset signal is deasserted (time t21), and the status signal is deasserted (time t22). The three-state buffer 13 deasserts the enable signal in response to the input of the deasserted reset signal and state signal (time t23). Then, the regulator 11 stops the output in response to the deasserted enable signal (time t24).

  By monitoring the input / output voltage of the regulator 11 in this manner, the power supply can be automatically shut down when an abnormality occurs in the input voltage or the output voltage. Further, the input / output voltage can be monitored with an inexpensive configuration without using an expensive power supply control unit such as a CPLD (Complex Programmable Logic Device). Further, by using the regulator 11 having an on / off (operation / standby) function and an output abnormality monitoring function, the mounting area can be made relatively small.

[Second configuration example]
FIG. 3 is a block diagram showing a second configuration example of a regulator having an overcurrent protection function in the embodiment of the present invention. The regulator 11 of the first configuration example has an on / off (operation / standby) function and an output abnormality monitoring function. However, the regulator 21 of the second configuration example does not have an output abnormality monitoring function. . That is, the electronic circuit of the second configuration example includes a regulator 21, a reset IC 12 with a delay function, a three-state buffer 13, and a reset IC 22.

  The regulator 21 has an input voltage terminal and an output voltage terminal, and controls the output voltage to be constant. The regulator 21 also has an enable terminal for inputting an enable signal for controlling ON / OFF (operation / standby) of the regulator 21. For this reason, for example, only the standby power supply can be operated during standby, and the main power supply can be turned on during use.

  The reset IC 12 with a delay function is the same as in the first configuration example, monitors the input voltage, and if the regulator 21 exceeds a range where the voltage can be controlled to be constant, the deasserted reset signal is sent to the three-state buffer 13. Output to. In addition, when the power is turned on, the reset signal is delayed and output to prevent an unexpected operation of the three-state buffer 13.

  The three-state buffer 13 is also similar to the first configuration example, and has an input terminal for inputting a state signal, an enable terminal for inputting a reset signal, and an output terminal for outputting an enable signal.

  The reset IC 22 monitors the output voltage, and outputs a deasserted reset signal to the three-state buffer 13 when the output voltage deviates from a specified value by a threshold value or more.

  Next, the operation of the electronic circuit of the second configuration example will be described with reference to FIG. As a precondition, the output delay time Ta of the reset IC 12 with a delay function is set to be longer than the time Tb from when the regulator 21 is powered on until the output of the reset signal B is asserted.

  When the power is turned on, a specified input voltage is applied to the regulator 21 and the reset IC 12 at time t31, and a specified voltage is output from the regulator 21 (time t32).

  Tb time after the input voltage is applied to the regulator 21, the reset signal B of the reset IC 22 is asserted (time t33). Further, the reset signal A of the reset IC 12 is asserted Ta time after the input voltage is applied to the regulator 21 (time t34), and the asserted enable signal is output from the three-state buffer 13. Thereby, the normal operation of the regulator 21 is started.

  Here, when some abnormality occurs in the circuit and the output voltage from the regulator 11 decreases (time t35), the reset signal B of the reset IC 22 is deasserted (time t36). The three-state buffer 13 deasserts the enable signal in response to the input of the deasserted reset signal B (time t37). Then, the regulator 21 stops the output in response to the deasserted enable signal (time t38).

  In addition, when an abnormality occurs in the power supply and the input voltage to the regulator 21 decreases and the regulator 21 becomes smaller than a threshold that can be controlled to a constant value (time t39), the output voltage of the regulator 21 decreases (time). t40). As a result, the reset signal A is deasserted (time t41), and the reset signal B is deasserted (time t42). The three-state buffer 13 deasserts the enable signal in response to the input of the deasserted reset signal A and reset signal B (time t43). Then, the regulator 21 stops the output in response to the deasserted enable signal (time t44).

  By monitoring the input / output voltage of the regulator 21 in this way, the power supply can be automatically shut down when an abnormality occurs in the input voltage or the output voltage. Also, the input / output voltage can be monitored with an inexpensive configuration without using an expensive power supply control unit such as a CPLD.

[Third configuration example]
FIG. 5 is a block diagram showing a third configuration example of a regulator having an overcurrent protection function in the embodiment of the present invention. The regulator 11 of the first configuration example has an on / off (operation / standby) function and an output abnormality monitoring function. However, the regulator 31 of the third configuration example has an on / off (operation / standby) function. Does not have. That is, the electronic circuit of the second configuration example includes a regulator 31, a reset IC 12 with a delay function, a three-state buffer 13, and a switching element 32.

  The regulator 31 has an input voltage terminal and an output voltage terminal, and controls the output voltage to be constant. Further, the regulator 31 has a state signal output terminal for outputting a state signal of the regulator 11, and outputs a deasserted state signal when a large current exceeding the rating flows in the output, thereby limiting the output current. To do. The deasserted status signal is also output when, for example, heat dissipation is insufficient and the chip temperature exceeds a specified value.

  The reset IC 12 with a delay function is the same as that of the first configuration example. The input voltage is monitored, and when the regulator 31 exceeds a voltage controllable range, the deasserted reset signal is sent to the three-state buffer 13. Output to. In addition, when the power is turned on, the reset signal is delayed and output to prevent an unexpected operation of the three-state buffer 13.

  The three-state buffer 13 is also similar to the first configuration example, and has an input terminal for inputting a state signal, an enable terminal for inputting a reset signal, and an output terminal for outputting an enable signal.

  The switching element 32 is composed of, for example, a field effect transistor including three terminals of a gate, a source, and a drain. Then, an enable signal is input to the gate, and the current between the source and the drain is controlled on and off.

  Next, the operation of the electronic circuit of the third configuration example will be described with reference to FIG. As a precondition, the output delay time Ta of the reset IC 12 with delay function is set to be longer than the time Tb from when the regulator 31 is powered on until the status signal output is asserted.

  When the power is turned on, a specified input voltage is applied to the regulator 31 and the reset IC 12 at time t51, and a specified voltage is output from the regulator 31 (time t52).

  A state signal of the regulator 31 is asserted Tb after the input voltage is applied to the regulator 31 (time t53). Further, after Ta time from the input voltage being applied to the regulator 31, the reset signal of the reset IC 12 is asserted (time t54), and the enable signal asserted from the three-state buffer 13 is output to the switching element 32. As a result, normal operation of the regulator 31 is started.

  Here, when some abnormality occurs in the circuit and the output voltage from the regulator 31 decreases (time t55), the state signal is deasserted (time t56). The three-state buffer 13 deasserts the enable signal in response to the input of the deasserted state signal (time t57). Then, the switching element 32 limits the current between the source and the drain according to the enable signal, and sets the input voltage of the regulator 31 to 0 V (time t58). Thereby, the output from the regulator 31 is stopped (time t59).

  In addition, when an abnormality occurs in the power supply and the input voltage to the regulator 31 decreases and the regulator 31 becomes smaller than a threshold that can be controlled to a constant value (time t60), the output voltage of the regulator 31 decreases (time). t61). As a result, the reset signal is deasserted (time t62), and the status signal is deasserted (time t63). The three-state buffer 13 deasserts the enable signal in response to the input of the deasserted reset signal and state signal (time t64). Then, the switching element 32 limits the current between the source and the drain according to the enable signal, and sets the input voltage of the regulator 31 to 0 V (time t65). Thereby, the output from the regulator 31 is stopped (time t66).

  By monitoring the input / output voltage of the regulator 31 in this manner, the power supply can be automatically shut down when an abnormality occurs in the input voltage or the output voltage. Also, the input / output voltage can be monitored with an inexpensive configuration without using an expensive power supply control unit such as a CPLD.

It is a block diagram which shows the 1st structural example in embodiment of this invention. It is a figure for demonstrating operation | movement of the electronic circuit of the 1st structural example. It is a block diagram which shows the 2nd structural example in embodiment of this invention. It is a figure for demonstrating operation | movement of the electronic circuit of the 2nd structural example. It is a block diagram which shows the 3rd structural example in embodiment of this invention. It is a figure for demonstrating operation | movement of the electronic circuit of a 3rd structural example.

Explanation of symbols

  11 Regulator, 12 Reset IC with Delay Function 13 Three-State Buffer, 21 Regulator, 22 Reset IC, 31 Regulator, 32 Switching Element

Claims (5)

A regulator that controls the output voltage to be constant with respect to the input voltage;
An input abnormality detection circuit that detects an abnormality of the input voltage and outputs a deasserted first abnormality detection signal;
An output abnormality detection circuit that detects an abnormality in the output voltage and outputs a deasserted second abnormality detection signal;
A three-state buffer that outputs an enable signal deasserted in response to an input of at least one of the deasserted first or second abnormality detection signal;
A control circuit that controls the regulator to be turned off in response to the deasserted enable signal.   2. The electronic circuit according to claim 1, wherein the input abnormality detection circuit is a reset IC with a delay function that delays and outputs a reset signal as the first abnormality detection signal when power is turned on.   The electronic circuit according to claim 2, wherein the regulator includes an input terminal to which the enable signal is input and the control circuit.   The electronic circuit according to claim 3, wherein the regulator includes an output terminal that outputs the second abnormality detection signal and the output abnormality detection circuit.   The electronic circuit according to claim 3, wherein the output abnormality detection circuit is a reset IC and outputs a reset signal as the second abnormality detection signal.

Images