JP2010016210A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a MOSFET from shifting in threshold voltage Vt owing to charge-up of a gate electrode. <P>SOLUTION: A capacitor lower electrode 3 is connected to the gate electrode 6a, and a capacitor upper electrode 6b is connected to a P-type ground layer 12 to form a capacitor in parallel to a gate comprising the gate electrode 6a and a gate insulating film 4. In this case, a capacitor insulating film 5 is formed thinner than the gate insulating film 4 and then electric charges charged up on the gate electrode 6a are discharged to the P-type ground layer 12 through the capacitor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention provides a semiconductor device and a method for manufacturing the same that can prevent a shift of the threshold voltage Vt due to charge-up during the wafer process.

  In the MOSFET manufacturing process, processing is often performed in a plasma atmosphere such as a dry etching process. For this reason, when the gate electrode of the MOSFET is charged up and extreme, the gate insulating film may be destroyed. In addition, even if it does not go so far, the gate insulating film is stressed to generate an interface state, or electrons are trapped in the gate insulating film, causing the threshold voltage Vt of the MOSFET to shift. May occur. For this reason, a diode is connected in parallel to the gate wiring to prevent an excessive voltage from being applied to the gate insulating film and to reduce the stress applied to the gate oxide film.

A MOSFET having such a diode for protecting the gate insulating film is described in the following Patent Documents 1 and 2 and the like.
JP 2005-294581 JP-A-7-202181

Conventional gate oxide protection diodes have a breakdown function with a lower electric field strength than the dielectric strength of about 1 × 10 ⁷ v / m, when the gate oxide film is thick. It was fully demonstrated. However, as the miniaturization progresses, the gate insulating film also becomes thinner, and the electric field in the insulating film reaches the dielectric breakdown resistance at a lower voltage, so the impurity concentration of the semiconductor substrate is set so that the protective diode also breaks down at a lower electric field. It is necessary to do. However, the impurity concentration of the semiconductor substrate cannot be adjusted sufficiently from the viewpoints of securing the withstand voltage between the source and drain and adjusting the threshold voltage Vt. As a result, the withstand voltage of the protective diode can be lowered. There may be no cases. On the other hand, a technique for suppressing plasma damage by devising a semiconductor device manufacturing process has been provided (Japanese Patent Laid-Open No. 2000-323582).

  However, if such a contrivance is not made, as a result, the breakdown voltage of the protection diode may be higher than the dielectric breakdown resistance of the gate oxide film, and the gate oxide film is subjected to stress before the protection diode is activated. Will be exposed. In addition, even when an electric field smaller than the dielectric breakdown resistance is applied to the gate insulating film, the gate insulating film is subjected to stress for a relatively long time including during the etching time. The problem is that the threshold voltage Vt shifts due to the implantation into the insulating film.

  As a result, when the threshold voltage Vt of one MOSFET, for example, M3, which constitutes a differential circuit such as the current mirror circuit shown in FIG. 6, is slightly shifted from the threshold voltage Vt of M4, which is the other MOSFET, M3 and Since the same current cannot be supplied to M4 and matching cannot be performed, normal operation is not performed. Therefore, in order to prevent the occurrence of such a problem, an object of the present invention is to provide a MOSFET capable of preventing a threshold voltage Vt shift.

  The method of manufacturing a semiconductor device of the present invention includes a step of forming an element isolation insulating film on the surface of a first conductivity type semiconductor substrate, a step of forming a lower electrode of a capacitor on one surface of the element isolation insulating film, A step of forming an insulating film on the surface of one element forming region and the lower electrode separated by the element isolation insulating film; a step of forming a gate electrode and an upper electrode of a capacitor on the surface of the insulating film; Forming a first conductive type ground layer in another element formation region separated by an element isolation insulating film, wherein the gate electrode, the lower electrode, the upper electrode, and the ground layer are electrically connected to each other. It is characterized by being connected to.

  The semiconductor device of the present invention includes an element isolation insulating film formed on the surface of a first conductivity type semiconductor substrate, a capacitor lower electrode formed on one surface of the element isolation insulating film, and the element isolation. An element forming region separated by an insulating film and an insulating film formed on a surface of the lower electrode; a gate electrode formed on the surface of the insulating film; an upper electrode of a capacitor; and the element separating insulating film. A first conductivity type ground layer formed in another element formation region where the elements are separated, and the gate electrode, the lower electrode, the upper electrode, and the ground layer are electrically connected to each other. It is characterized by.

  According to the present invention, the threshold voltage Vt shift can be prevented because the gate insulating film of the MOSFET is not subjected to stress due to charge-up during the wafer process.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, about embodiment of this invention, NMOSFET which is N channel type MOSFET is employ | adopted as a typical example, and description is advanced. First, as shown in FIG. 1, an element isolation insulating film 2 is formed on the surface of a P-type semiconductor substrate 1 by a predetermined method. Next, a polysilicon film is formed on the entire surface including the element isolation insulating film 2 by LPCVD, and a capacitor lower electrode 3 is formed on one element isolation insulating film 2 through a predetermined photolithography process or the like.

  As shown in FIG. 7, the capacitor lower electrode 3 preferably has a shape having many angular end faces. In addition, it is also considered that the grain boundaries are clarified by forming at a high temperature, or that the surface of the polysilicon film is roughened by etching or sandblasting. It is also desirable that the capacitor lower electrode 3 has a reverse taper shape from the upper surface to the lower surface. These effects will be described later. Next, sacrificial oxidation treatment or the like is performed to form a gate insulating film 4 on the surface of the clean P-type well layer 1 and a capacitor insulating film 5 on the surface of the capacitor lower electrode 3. The capacitor insulating film 5 may be formed thinner than the gate insulating film 4 separately from the gate insulating film 4. In this case, a thin insulating film may be formed by a CVD method without being limited to thermal oxidation.

  Next, as shown in FIG. 2, a conductive film 6 such as polysilicon is deposited on the entire surface of the semiconductor substrate including the gate insulating film 4 and the capacitor insulating film 5 by LPCVD or the like. Thereafter, a portion where the resistance layer is to be formed is covered with a barrier layer 7 made of a silicon nitride film pattern or the like, and then phosphorus diffusion is performed from the surface of the conductive film 6 by a predetermined method to reduce the resistance of the conductive film 6. Next, as shown in FIG. 3, a gate electrode 6a and a capacitor upper electrode 6b are formed through a predetermined photolithography process. Under the barrier layer 7, a resistance layer 6c in which phosphorus is not diffused is formed. The resistance layer 6c is not necessarily formed, and this step can be omitted.

  Next, as shown in FIG. 4, an LDD layer 8 to be a low-concentration drain layer or the like is formed using the gate electrode 6a as a mask, and an oxide film is further deposited on the entire surface of the semiconductor substrate by the LPCVD method. Sidewalls 9 are formed on the side surfaces of the gate electrode 6a by dry etching. Thereafter, an N-type source layer 10 and an N-type drain layer 11 are formed by ion implantation of impurities such as arsenic, and a P-type ground layer 12 is further formed by ion implantation of boron or the like. Further, if necessary, impurities are ion-implanted into the resistance layer 6c in order to adjust the resistance value of the resistance layer 6c.

  Next, as shown in FIG. 5, after the entire surface of the semiconductor substrate is covered with the interlayer insulating film 13 by the LPCVD method, a contact hole 14 is formed through a predetermined photolithography process or the like. Thereafter, an aluminum film or the like is deposited on the entire surface of the interlayer insulating film 13 including the inside of the contact hole 14 by sputtering or the like, and a wiring electrode is formed by predetermined anisotropic dry etching. In FIG. 5, only the wiring electrode 15 connecting the gate electrode 6a and the capacitor lower electrode 3, the capacitor upper electrode 6b and the P-type ground layer 12 necessary for understanding the present invention are displayed, and the N-type source is shown. The wiring layers related to the layer 10 and the N-type drain layer 11 are not shown.

In dry etching of an aluminum film or the like for forming a wiring electrode, etching is difficult as compared with other films, so that a chlorine-based gas is used or a high voltage is applied in a high-density plasma atmosphere. During etching, various ions tend to adhere to the active aluminum film surface. As a result, the gate electrode 6a is charged up by various ions in the plasma. The dielectric breakdown strength of the gate insulating film 4 is slightly higher than Emax = 1 × 10 ⁹ v / m. If the electric field strength E generated in the gate insulating film 4 due to the charge-up of the gate electrode 6a becomes equal to or higher than Emax, the gate insulating film 4 Will cause dielectric breakdown.

Incidentally, the electric field intensity E generated in the gate insulating film 4 is E = q / ε, where q is the charge amount per unit area of the gate electrode 6a when charged up and ε is the dielectric constant of the oxide film. Therefore, when the charge amount when the electric field strength E is the electric field strength Emax when dielectric breakdown of the gate insulating film 4 and _{q max,} the _{q max} = _εEmax. When the charge amount due to charge-up becomes q _max , the gate insulating film 4 causes dielectric breakdown.

However, even before the charge-up amount reaches q _max , an electric field is generated in the gate insulating film 4 due to the charge-up, and the electric field strength gradually increases as the etching time increases. At this stage, the gate insulating film 4 does not cause dielectric breakdown. However, the stress due to the gradually increasing electric field generated in the gate insulating film 4 forms a new interface state at the interface between the gate insulating film 4 and the P-type well layer 1, or the gate insulating film 4 is caused by the strong electric field. The gate threshold voltage Vt fluctuates due to electrons or the like being injected therein.

  In the present invention, a capacitor having a larger area than that of the gate electrode 6a on the gate insulating film 4 is connected in parallel with the gate electrode 6a by a conductive film such as an aluminum layer. Therefore, even when there is a charge-up due to various ions contained in the dry etching atmosphere when the wiring electrode is formed, the charge charged up by the gate electrode 6a portion and the capacitor portion is shared, and the gate electrode 6a The charge-up amount of the part is reduced. Since the area of the capacitor portion is generally larger than the area of the gate portion, the effect is great. As a result, the electric field strength in the gate insulating film 4 is weakened, the stress received by the gate insulating film is reduced, and the shift of the threshold voltage Vt due to charge-up can be prevented.

  However, the charge-up amount further increases, and there are cases where it cannot be shared by the capacitor. In the present invention, assuming such a case, the capacitor insulating film 5 is locally formed with a thin portion. As shown in FIGS. 8A to 8C, the shape of the capacitor lower electrode 3 is made to be a lot of square shapes, the surface of the polysilicon to be the capacitor lower electrode 3 is roughened, and the upper surface is reversed from the lower surface to the lower surface. A portion having a smaller film thickness than the gate insulating film can be locally formed on the surface thereof, for example, in a tapered shape.

  When the capacitor is charged up and the electric field strength in the capacitor insulating film 5 is increased, the charge-up amount that increases with the lapse of the dry etching time gradually becomes a P + type ground layer through a thin portion of the capacitor insulating film 5 due to a tunneling phenomenon. It can be discharged and reduced. As a result, the electric field strength in the gate insulating film 4 can be weakened to prevent the threshold voltage Vt shift and the like. However, when considering the dielectric breakdown of the capacitor insulating film 5, it is necessary to provide a resistance layer 6c as shown in FIG. 3 between the capacitor upper electrode 6b and the P-type ground layer 12 to prevent gate leakage current. is there.

  As another embodiment of the present invention, there is a method in which the gate electrode 6a and the capacitor lower electrode 3 are integrally formed, and a contact electrode for the capacitor upper electrode 6b and the P-type ground layer 12 is also integrally formed. In this case, since the gate electrode 6a and the capacitor lower electrode 3 are integrally formed, it is only necessary to form the wiring electrode only at a portion connected to the gate electrode 6a. Therefore, compared to the wiring electrode 15 in the first embodiment. It becomes a small area. Accordingly, the amount of charge-up as a whole decreases, the amount of charge on the gate insulating film 4 shared with the capacitor portion decreases, and the stress received by the gate insulating film 4 can be reduced.

  Further, the charge up received by the gate electrode 6a from the plasma atmosphere during the anisotropic dry etching when the contact hole 14 is formed before the wiring electrode is formed can also be shared with the capacitor, so that the gate insulating film 4 It is possible to reduce the stress that is received. In the embodiment of the present invention, the lateral NMOSFET has been described as an example. However, the present invention is applied not only to the lateral PMOSFET and lateral CMOSFET but also to the trench MOSFET as long as the inventive concept is the same. Needless to say, you can.

It is sectional drawing which shows the semiconductor device of this invention, and its manufacturing method. It is sectional drawing which shows the semiconductor device of this invention, and its manufacturing method. It is sectional drawing which shows the semiconductor device of this invention, and its manufacturing method. It is sectional drawing which shows the semiconductor device of this invention, and its manufacturing method. It is sectional drawing which shows the semiconductor device of this invention, and its manufacturing method. This is a basic operational amplifier circuit including a current mirror circuit. It is a top view which shows an example of the shape of the capacitor lower electrode of this invention. It is sectional drawing which shows the capacitor lower electrode and capacitor insulating film of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P type well layer or P type semiconductor substrate 2 Element isolation insulating film 3 Capacitor lower electrode 4 Gate insulating film 5 Capacitor insulating film 6 Conductive film 6a Gate electrode 6b Capacitor upper electrode 6c Resistance layer 7 Barrier layer 8 LDD layer 9 Side wall 10 N-type source layer 11 N-type drain layer 12 P-type ground layer 13 Interlayer insulating film 14 Contact hole 15 Wiring electrode 16 Wiring electrode 17 Thin oxide film portion

Claims (4)

Forming an element isolation insulating film on the surface of the first conductivity type semiconductor substrate;
Forming a lower electrode of a capacitor on the surface of one of the element isolation insulating films;
Forming an insulating film on the surface of one element formation region and the lower electrode separated by the element isolation insulating film; and
Forming a gate electrode and an upper electrode of a capacitor on the surface of the insulating film;
Forming a ground layer of a first conductivity type in another element formation region separated by the element isolation insulating film,
A method of manufacturing a semiconductor device, wherein the gate electrode, the lower electrode, the upper electrode, and the ground layer are electrically connected to each other. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the insulating film formed on the surface of the lower electrode is locally thin. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a resistance layer is formed between the upper electrode and the ground layer. An element isolation insulating film formed on the surface of the first conductivity type semiconductor substrate;
A lower electrode of a capacitor formed on the surface of one of the element isolation insulating films;
An element forming region separated by the element isolation insulating film and an insulating film formed on a surface of the lower electrode;
A gate electrode formed on the surface of the insulating film and an upper electrode of the capacitor;
A ground layer of a first conductivity type formed in another element formation region separated by the element isolation insulating film,
The semiconductor device, wherein the gate electrode, the lower electrode, the upper electrode, and the ground layer are electrically connected to each other.