JP2010004284A - Image decoder, and image decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image decoder and an image decoding method which enhance a processing rate by concurrent decoding, and moreover prevent an increase in circuit scale. <P>SOLUTION: An input buffer 103 stores a non-zero coefficient string not containing a zero coefficient. A means for generating parameters generates a plurality of parameters which indicate a zero coefficient inserting position and are divided into a plurality of parts for each predetermined process unit. An output buffer 106 stores a coefficient string containing a zero coefficient. A plurality of tables 108a, 108b are provided for each of a plurality of process units to output the positions of a zero coefficient and a non-zero coefficient and the number of non-zero coefficients at the output buffer in correspondence to the plurality of parameters. A plurality of coefficient selecting circuits 105a, 105b are provided for each of the plurality of process units to determine the indexes of the zero and non-zero coefficients in the coefficient string to be regenerated by outputs of the plurality of tables, transfer the non-zero coefficient to the output buffer, and write the zero coefficient to the output buffer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image decoding apparatus and an image decoding method. The present invention relates to an image decoding apparatus and an image decoding method for decoding CABAC encoded data in H.264.

  In the field of audio-visual (AV) multimedia systems, Advanced Video Coding (AVC) is an H.264 standard. H.264 / AVC.

  H. In H.264 / AVC, syntax element entropy coding (variable length coding), which is information specified to be transmitted in syntax, such as discrete cosine transform (DCT) coefficients and motion vectors. In addition to conversion using a simple table, a highly efficient encoding method is prepared, which is applied when encoding DCT coefficients that require high encoding efficiency.

  As such a highly efficient coding method, there is a method called context adaptive binary arithmetic coding (CABAC).

  The CABAC encoding apparatus includes a normal binary arithmetic encoder and a binary for converting a multilevel signal (for example, a signal of -3 or +6) into a binary signal (a signal of 0 and 1). And a context calculator that calculates / updates the occurrence probability of the binary signal to be encoded according to the surrounding situation. The binarization unit converts the input multi-value syntax element into a variable-length binary symbol string. In the CABAC encoding apparatus, arithmetic encoding is performed for each bit of the binary symbol while adaptively switching the probability model based on the context information.

  In the present specification, the moving image format H.264 is used. A CABAC decoder applied when decoding a pixel data coefficient sequence of a syntax element encoded with a residual block CABAC (residual_block_cabac) on H.264 will be described.

  Movie format In H.264, coeffLevel (coefficient sequence) obtained from syntax elements coeff_abs_level_minus1 [] and coeff_sign_flag [] ([] indicates an index (Index) indicating a number corresponding to each coefficient in the coefficient sequence is an integer of 0 or more). When decoding an index (an index indicating a number corresponding to each coefficient of coeffLevel), the index is determined by significant_coeff_flag [] and last_significant_coeff_flag []. When the index for the coeffLevel is decoded by the order / method described in the standard document, the index of the next coeffLevel is determined after the index of a certain coeffLevel is determined. That is, after determining the index of one coeffLevel, the process proceeds to the process of determining the index of the next coeffLevel.

  As a result, when there are few coefficients in the macroblock (MB), the decoding process ends early, but when there are many coefficients, the decoding process takes time, and in the worst case, the number of coefficients (384 coefficients) cycle + It takes time for latency.

  By the way, when decoding the coefficient sequence in this way, if the index is decoded sequentially, significant_coeff_flag [] and last_significant_coeff_flag [] are processed one symbol at a time, which increases the number of processing cycles and increases the processing time. There's a problem.

  As a method for solving this problem, the present applicant has proposed to speed up the decoding process by simultaneously retrieving (parallelizing) significant_coeff_flag [] and last_significant_coeff_flag [] from a reference table (for example, Patent Document 1). reference).

However, although patent document 1 can improve processing speed, there exists a problem that a reference table becomes large when parallelizing.
JP 2006-166344 A

  Therefore, in view of the above problems, the present invention provides an image decoding apparatus and an image decoding method that can improve processing speed by using parallel processing when decoding and can prevent an increase in circuit scale. It is for the purpose.

  According to one aspect of the present invention, there is provided an image decoding apparatus for inputting a non-zero coefficient sequence that does not include a zero coefficient of a predetermined moving image format, decoding, and reproducing the original coefficient sequence including the zero coefficient, An input side buffer for storing the non-zero coefficient sequence before an index is determined, and a parameter generating means for indicating a position at which a zero coefficient is inserted between the non-zero coefficient sequences, for each predetermined processing unit Means for generating a plurality of parameters used by dividing into a plurality, an output side buffer for storing a coefficient sequence including a zero coefficient for which an index is determined, and provided for each of the plurality of divided processing units. A plurality of tables capable of outputting the positions of the zero and non-zero coefficients and the number of non-zero coefficients in the output buffer in response to a plurality of inputs by a plurality of parameters. Provided for each of the plurality of divided processing units, and determining the zero coefficient and non-zero coefficient indexes of the coefficient sequence to be reproduced according to the output of the plurality of tables, and from the input side buffer to the output side A plurality of coefficient selection circuits for transferring a non-zero coefficient to a buffer and writing the zero coefficient to the output-side buffer, and simultaneously determining an index for a reproduced coefficient sequence including the zero coefficient. An image decoding device is provided.

  According to another aspect of the present invention, there is provided an image decoding method for inputting a non-zero coefficient sequence that does not include a zero coefficient in a predetermined moving image format, and decoding the original coefficient string including the zero coefficient. , A parameter indicating a position where a zero coefficient is inserted between the non-zero coefficient sequences is divided into predetermined processing units, and the non-zero coefficient is applied to a plurality of tables provided for each of the divided processing units. Refer to the table for the storage location of the non-zero coefficient sequence in the input buffer where the column is stored and the storage location of the coefficient sequence in the output buffer after index determination corresponding to the coefficient sequence to be reproduced. There is provided an image decoding method characterized by simultaneously calculating an index corresponding to a reproduced coefficient sequence.

  According to the present invention, it is possible to provide an image decoding apparatus and an image decoding method that can improve the processing speed by using parallel processing when decoding and can prevent an increase in circuit scale.

Embodiments of the invention will be described with reference to the drawings.
Prior to describing the embodiment of the present invention with reference to FIGS. 1 to 6, the related art of the present invention will be described with reference to FIGS.

  The image decoding apparatus 100 illustrated in FIG. 7 receives a non-zero pixel data coefficient sequence (bitstream) transmitted from the outside, and generates input parameters (coeff_abs_level_minus1, coeff_sign_flag, numCoeff, significant_coeff_flag, last_significant_coeff_flag, and maxNumCoeff). A tax decoder 101, a level decoding circuit 102 that decodes the coefficient (level) of the coefficient sequence before the index is determined from the corresponding syntax, and a level buffer 103 that stores the decoded level The last_significant_coeff_flag is reflected in the significant_coeff_flag, the last_significant_coeff_flag circuit 104 that decodes the presence / absence (non-zero, zero) of the level, the selection circuit 105 that determines the Index for each coefficient, the coeff buffer 106 that stores the level at which the Index is determined, Zigzag scan times to perform zigzag scan (ZigZagScan) processing And a 107.

  8A and 8B are schematic diagrams for explaining the decoding method of the related art of FIG. 7, wherein FIG. 8A is a diagram showing a binary coefficient sequence after CABAC decoding, and FIG. 8B is a coefficient sequence parameter A, B, C, D. FIG. 4C is a processing flowchart of the decoding method.

  In such a configuration, the bit stream (bitstream) data of the coefficient sequence of only non-zero coefficients excluding the zero (0) coefficient is transmitted to the syntax decoder 101 from a transmission side (image coding apparatus side) (not shown). . The reason for this stream of only non-zero coefficients is that transmission efficiency is better when only non-zero coefficients excluding zero coefficients are collected and compressed. The transmitted data is stored in the bitstream storage unit 10. The CABAC decoder 11 decodes a binary coefficient sequence as shown in FIG. The binary coefficient string after CABAC decoding is stored in the binary coefficient string storage unit 12.

  FIG. 8B shows the definition of the coefficient sequence parameters A, B, C, and D, which means that A is a value displayed as “1” if it is a non-zero coefficient. If B is the last non-zero coefficient, it means that the value is displayed as “1”. C means that the absolute value of the coefficient minus 1 is displayed. D means that “0” is displayed as a sign of a coefficient, and “1” is displayed as a minus sign.

  When the bit stream of non-zero coefficients is decoded by the CABAC decoder 11, the portion of the C column becomes a numerical value. The C column contains a value obtained by subtracting 1 from the numerical value, and in combination with this, the D column contains a code. It is a sign of + or-. If it is 1 in the D column, it is-, and if it is 0, it is +. Looking at the second column from the top, it is “7”. Since the absolute value of the coefficient −1 is entered in the C column, the true coefficient value is incremented by “8”. Moreover, since the second from the top in the D column is “1”, the value is “−8”. Similarly, since the first of the C column and the D column is “9” and “0”, it becomes “+10”.

  Here, it is assumed that C and D columns have already decoded coefficient values. The problem is how to combine the A column and the B column and put the zero coefficient between the non-zero coefficient columns that do not include the zero coefficient obtained by decoding the C column and the D column. According to the parameters of the A column and the B column, it is possible to know where the zero coefficient should be sandwiched in the non-zero coefficient column, in other words, where to place the non-zero coefficient in the zero coefficient column.

Explain the meaning of terms written in Alphabed.
maxNumCoeff ... Maximum number of residuals (coefficients) to be decoded in the block to be processed. Here, it is used for the presence of coded_block_flag and zero padding of coefficients. In the example of the coefficient string matrix 16 in FIG. 8C, 4 × 4 = 16 is the maximum number of coefficients, and maxNumCoeff = 16.

  significant coeff flag: Flag indicating the presence or absence of non-zero coefficient. In the case of 1, the following can be said. (1) The coefficient at the corresponding position is not zero. (2) Last_significant_coeff_flag with the same Index makes sense.

  last_significant_coeff_flag: Flag indicating that it is the last non-zero coefficient. It only makes sense when the corresponding significant_coeff_flag is 1. When this flag is 1, it becomes the final non-zero coefficient in the processing block. Further, when the final non-zero coefficient = the final index, it may be zero.

  coeffLevel [] ... Coefficient sequence reproduced from ooeff_level_abs_minus1. Also called residual. Only the non-zero coefficient is decoded in the residual itself, and the location of the non-zero coefficient in the processing block is determined by significant_coeff_flag / last_significant_coeff_flag.

  level: Non-zero coefficient sequence in decoding order. It often refers to the state before being sorted into coeffLevel.

  index ... The array index. It is often explained as a subscript of coeffLevel □.

  As shown in FIG. 8 (c), the H.264 from the bitstream stored in the bitstream storage unit 10. When the H.264 coefficient data is extracted and decoded, the CABAC decoder 11 performs CABAC decoding (decoding) of the bit stream to temporarily form a binary coefficient string (bin string string) as shown in FIG. It is stored in the storage unit 12. Further, in the last_significant_coeff_flag decoding circuit 104 connected to the binary coefficient sequence storage unit 12, a parameter (significant_coeff_flag of the A column) indicating whether the binary coefficient sequence after CABAC decoding is a non-zero coefficient is a final non-zero coefficient. The presence / absence of level (non-zero coefficient) is decoded by reflecting it in a parameter (last_significant_coeff_flag in column B) indicating whether or not there is.

  When the selection circuit 105 generates a coefficient sequence (level) including zero (0) coefficients with reference to coeff_flag indicating the presence / absence of level for the non-zero coefficient sequence (level) obtained from the CD sequence 13 In addition, a coefficient sequence including zero coefficients is generated and an index corresponding to the generated coefficient sequence (a number indicating the order necessary to obtain the coefficient sequence matrix 16) is generated (determined).

  From the binary coefficient sequence after CABAC decoding shown in FIG. 8 (a), the data portion (the numerical value of the non-zero coefficient) of the content of the CD sequence 13 is generated. In order to decode the binary coefficient string data and obtain the original coefficient string including the zero coefficient, as shown in FIG. 8 (c), a non-zero coefficient string (zero coefficient coefficient) previously generated based on the CD string 13 is obtained. And a parameter indicating whether or not there is a non-zero coefficient generated based on the AB sequence 14, the coefficient sequence 15 is created, and as a result, the coefficient sequence matrix 16 can be obtained.

  In the video format standard H.264, when the index of the coefficient sequence (coeffLevel) reproduced based on coeff_abs_level_minus1 [] and coeff_sign_flag [] of the CD sequence 13 is decoded, the index is selected by the selection circuit 105 and significant_coeff_flag [ ], Last_significant_coeff_flag []. When the index is decoded for the coefficient sequence (coeffLevel) reproduced in the order / method described in the standard, the index of the next level is determined after the index of a certain level is determined.

  Accordingly, when there are many coefficients (level) in a macroblock (MacroBlock), the processing takes time, and in the worst case, the number of coefficients (for example, 384 coefficients) cycle + latency is required.

  Therefore, in the embodiment of the present invention, when determining the Index with respect to the decoded level (coeffLevel before the Index is determined), the non-zero coefficient sequence is divided into predetermined processing units (for example, 4 pixel units). By providing a plurality of tables for each of the plurality of divided processing units and drawing a plurality of tables at a time with a parameter (significant_coeff_flag reflecting the last_significant_coeff_flag) indicating the position where the zero coefficient is inserted, By determining the index, it is possible to improve the processing speed without increasing the table.

[First Embodiment]
FIG. 1 shows a block diagram of an image decoding apparatus according to the first embodiment of the present invention. As the first embodiment, an example is shown in which processing is performed in units of 8 pixels in total of 4 pixels and 2 parallels.

  The image decoding apparatus 100A illustrated in FIG. 1 receives a non-zero coefficient pixel data coefficient sequence (bitstream) transmitted from the outside, and generates a syntax decoder that generates parameters coeff_abs_level_minus1, coeff_sign_flag, numCoeff, significant_coeff_flag, last_significant_coeff_flag, and maxNumCoeff. 101, a level decoding circuit 102 for decoding a non-zero coefficient (level) before an index (Index) is determined from corresponding syntax data, and an input for storing the decoded non-zero coefficient (level) The level buffer 103 as a side buffer, the parameter last_significant_coeff_flag is reflected in significant_coeff_flag, the presence / absence of level is decoded, the last_significant_coeff_flag decoding circuit 104 that outputs as coeff_flag, and the upper 4 bits of coeff_flag (output of the decoding circuit 104) are referenced, and the coeff buffer Leve for 106 l A table for obtaining the index of the buffer 103 and the number of non-zero coefficients (coeff_num_up), and when processing in units of 8 pixels, the upper coefficient selection table 108a for processing the fourth to seventh pixels, and coeff_flag ( This is a table for obtaining the index of the level buffer 103 with respect to the coeff buffer 106 and the number of non-zero coefficients (coeff_num_lw) with reference to the lower 4 bits of the output of the decoding circuit 104). Calculate the total number of non-zero coefficients by adding the lower-side coefficient selection table 108b that processes the third pixel, the number of non-zero coefficients on the upper side (coeff_num_up) and the number of non-zero coefficients on the lower side (coeff_num_lw) The non-zero coefficient (level) is read from the level buffer 103 in accordance with the adder 109 and the output (index_pattern_up) of the higher coefficient selection table 108a, the index is determined for each coefficient, and the coeff buffer The non-zero coefficient (level) is read from the level buffer 103 in accordance with the output (index_pattern_lw) of the higher-order coefficient selection circuit 105a and the lower-order coefficient selection table 108b to be stored in the fa 106, the Index is determined for each coefficient, and coeff A low-order coefficient selection circuit 105b to be stored in the buffer 106, a buffer for storing a coefficient sequence (level) for which the Index is determined, and a coeff buffer 106 as an output-side buffer having an 8-bank configuration in units of 8 pixels, and an Index A zigzag scan circuit 107 that performs a zigzag scan (ZigZagScan) process on the determined coefficient sequence (level) in the order of Index is provided.

  In the notation in FIG. 1, for example, 8-bit data from 0th to 7th bits is represented as [7: 0]. [7: 4] represents the upper 4 bits of the 4th to 7th bits, and [3: 0] represents the lower 4 bits of the 0th to 3rd bits.

FIG. 2 explains the decoding operation of last_significant_coeff_flag / significant_coeff_flag in the last_significant_coeff_flag decoding circuit 104 of FIG.
First, when receiving significant_coeff_flag, last_significant_coeff_flag, and maxNumCoeff decoded by the syntax decoder 101, the last_significant_coeff_flag decoding circuit 104 generates coeff_flag in which last_significant_coeff_flag is reflected in significant_coeff_flag. In coeff_flag, “1” is stored when there is a non-zero coefficient at the corresponding bit position, and “0” is stored when there is a zero coefficient.

  Since last_significant_coeff_flag is meaningful only when significant_coeff_flag is “1” and last_significant_coeff_flag is “1”, the value of * in FIG. 2 may be an arbitrary number.

  coeff_flag which is the output of the last_significant_coeff_flag decoding circuit 104 is the presence or absence of a non-zero coefficient generated by combining the A column and the B column, that is, the zero coefficient for the coefficient sequence having the maximum number of coefficients including the zero coefficient and the non-zero coefficient. It can be said that indicates the position where the non-zero coefficient exists.

  In the level decoding circuit 102, non-zero coefficient (level) is decoded from coeff_abs_level_minus1 and coeff_sign_flag of the C column and D column output from the syntax decoder 101, and the decoded non-zero coefficient (level) is level. Assume that the data is stored in the buffer 103.

  Next, using coeff_flag indicating the presence / absence of non-zero coefficients, the position in the level buffer 103 for storing non-zero coefficients with respect to the reproduced coefficient sequence (coeffLevel []) and the number of non-zero coefficients are set to the upper side / lower side. The table is looked up by the coefficient selection table 108a / 108b. In this embodiment, since processing is performed in units of 8 pixels in parallel in units of 4 pixels, 8 bits of coeff_flag [7: 0] are converted to 4 bits of upper side (coeff_flag [7: 4]) and 4 bits of lower side ( coeff_flag [3: 0]), and two tables 108a and 108b for four pixels are simultaneously drawn for each. Here, the upper coefficient selection table 108a and the lower coefficient selection table 108b need only have two tables for four pixels having the same configuration. Thus, by using two coefficient selection tables in parallel, it is possible to reduce the scale of the coefficient selection table compared to the case where only one 8-pixel table is used without parallelization. In addition, two small tables having the same configuration may be prepared. Of course, the 8-bit coeff_flag [7: 0] may be divided into four, and the table may be looked up using four coefficient selection tables at a time.

  According to the table, to which position of the coeffLevel [] buffer (coeff buffer 106) which coefficient of the level buffer 103 is applied, to which position of the coeffLevel [] buffer (coeff buffer 106), the zero coefficient is applied, or non-zero to be applied The number of coefficients is determined.

  When the storage positions of the zero coefficient and the non-zero coefficient are determined by the table, the non-zero coefficient is transferred from the level buffer 103 to the coeff buffer 106 by the upper / lower coefficient selection circuit 105a / 105b to the corresponding position. In the case of a zero coefficient, zero writing to the coeff buffer 106 is performed. At this time, the higher-order coefficient selection circuit 105a shifts the position of the bank to be read from the level buffer 103 by the number of non-zero coefficients (level) drawn by the lower-order coefficient selection table 108b.

  Finally, for the next processing, the level buffer 103 is incremented by the number of evaluated (decoded) non-zero coefficients (level) l, and a determination for switching the bank of the output coeff buffer 106 is made.

FIG. 3 shows the upper or lower coefficient selection table 108a or 108b in units of four pixels.
In FIG. 3, reference numeral 20 indicates coeff_flag [7: 4] of the upper 4 bits or the lower 4 bits of the 8-bit output of the last_significant_coeff_flag decoding circuit 104 (coeff_flag indicating the presence / absence of the non-zero coefficient obtained from the AB sequence). Of coeff_flag [3: 0].

  Reference numeral 21 indicates the lower 4 (or higher) Index No. of the coeff buffer 106 (more precisely, the index No. of the bank). Of the 4-bit Index_pattern, the z portion indicated by right-upward hatching represents the zero coefficient, and the portion indicated by right-downward hatching represents the position of the non-zero coefficient (Index No. of the level buffer 103). The coeff buffer 106 stores all 8-bit data to be reproduced (data including zero coefficient and non-zero coefficient) in a bank of 8 bits, and therefore, the bank of 8 bits is not always used. As many banks as the number of non-zero coefficients (the sum of the non-zero coefficients on the lower side and upper side) are used.

  Reference numeral 22 indicates the number of non-zero coefficients among the number of coefficients of 4 bits on the lower side (or higher side).

  The drawing of the coefficient selection table shown in FIG. 3 means that the bank of the level buffer 103 on the input (IN) side and the bank of the coeff buffer 106 on the output (OUT) side are drawn in this table. It means that.

FIG. 4 shows a processing example in which the table in FIG. 3 is drawn with the coeff_flag output from the last_significant_coeff_flag decoding circuit 104 as an input, and the index (Index) of the coefficient sequence to be reproduced is determined.
FIG. 4A shows a decoding output from the last_significant_coeff_flag decoding circuit 104 (1 or 0 data indicating the presence or absence of a non-zero coefficient in which last_significant_coeff_flag is reflected in significant_coeff_flag), for example, 8-bit coeff_flag [7: 0]. .

  FIG. 4B shows the coeff_flag [7: 4] = 0011, coeff_flag [3: 0] = 1101 obtained by dividing the 8-bit coeff_flag [7: 0] of FIG. 3 is the 4-bit index (Index) [3] to [0] of the coeff buffer 106 reproduced including the zero coefficient when the input bits of the coefficient selection tables 108a and 108b in FIG. This is indicated as the index (index_pattern_up, index_pattern_lw) of the bank of the level buffer 103. coeff_num_up and coeff_num_lw indicate the number of non-zero coefficients in index_pattern_up or index_pattern_lw, respectively.

  FIG. 4C shows Index [0] to [7] corresponding to the coefficient sequence (corresponding to the reference numeral 15 in FIG. 8) of the coeff buffer 106 reproduced including the zero coefficient. Zero coefficients are set for Index [1], [6], and [7], and level_buf [0] and [1] corresponding to Index of the level buffer 103 are assigned to Index [0], [2], and [3], respectively. ], [2] means that the coefficient stored in each bank is set.

  Also, the bank of the level buffer 103 used in the upper coeff_buf in FIG. 4C has the number of non-zero coefficients of the lower coeff_buf (here, “3” shown on the lower side in FIG. 4B). It is added as an offset (addition value) for representing the index of the upper level level_buf (the thin solid arrow from (b) to (c) in FIG. 4 indicates this).

  FIG. 5 shows that when the coefficient selection table of FIG. 3 is drawn, when the level buffer 103 is an input side (IN) bank and the coeff buffer 106 is an output side (OUT) bank, the IN and OUT banks are associated. The relationship between IN and OUT will be described with reference to two examples of coeff_flag [7: 0] representing the presence or absence of a non-zero coefficient obtained from the AB sequence. In other words, using the parameter indicating the insertion position of the zero coefficient (or non-zero coefficient) generated based on the AB sequence, the zero coefficient (or non-zero) is determined between the non-zero coefficients decoded from the CD sequence. A description will be given of whether the coefficient is inserted.

FIG. 5A shows the relationship between IN and OUT when coeff_flag [7: 0] = 0011101.
The banks 0 to 7 in the squares of the IN side level buffer 103 contain a to h as non-zero coefficient values that do not include zero. Since the bank 0 to 7 of the □ of the coeff buffer 106 on the OUT side has been described with reference to FIG. 4, as a result of zero coefficient entering the banks 1, 6 and 7 of the coeff buffer 106, , 0, b, c, d, e, 0, 0 are entered, and a coefficient sequence including a zero coefficient is reproduced.

Similarly, FIG. 5B shows the relationship between IN and OUT when coeff_flag [7: 0] = 0011111.
The banks 0 to 7 in the squares of the IN side level buffer 103 contain a to h as non-zero coefficient values that do not include zero. As a result of zero coefficients entering banks 6 and 7 of the coeff buffer 106 on the OUT side, a, b, c, d, e, f, 0, and 0 are entered in the respective banks 0 to 7 of the coeff buffer 106, and zero coefficients are set. The included coefficient sequence is reproduced.

  According to the first embodiment, it is possible to improve the processing speed by using parallel processing when decoding, and to reduce the table and prevent the circuit scale from increasing.

[Second Embodiment]
FIG. 6 shows a block diagram of an image decoding apparatus according to the second embodiment of the present invention. As the second embodiment, an example is shown in which processing is performed in units of 8 pixels in total of 4 pixels and 2 parallels.

  The image decoding apparatus 100B shown in FIG. 6 is different from the circuit configuration of FIG. 1 in that the result of the last_significant_coeff_flag decoding circuit 104 is input and no non-zero coefficient is included in the processing unit (that is, only the zero coefficient is included). If the bypass selection circuit 110 indicates that there is no non-zero coefficient (that is, only the zero coefficient), the processing pixel (processing unit pixel) is zeroed to the coeff buffer. And a zero selection circuit 111 for outputting as follows.

  In such a configuration, the bypass selection circuit 110 receives the result of the last_significant_coeff_flag decoding circuit 104 as an input, and determines that no non-zero coefficient is included in the processing unit (for example, 4 pixels 2 parallel = 8 pixels). (Judgment result is bypath_flag) and output. The zero selection circuit 111 outputs the processing pixel (processing unit, in this case, 8 pixels) as zero to the coeff buffer 106 when the bypath_flag indicates that there is no non-zero coefficient.

  By the addition of the bypass selection circuit 110 and the zero selection circuit 111, the coefficient selection tables 108a and 108b and the coefficient selection circuits 105a and 105b are not activated when a non-zero coefficient is not included in the processing unit.

As a result, the coefficient selection tables 108a and 108b and the coefficient selection circuits 105a and 105b can be stopped when no non-zero coefficient is included in the processing unit (that is, only zero coefficients are included). There is an advantage that power can be reduced.

  According to the second embodiment, when no non-zero coefficient is included in the processing unit, this is determined and the processing power is reduced by stopping the coefficient selection table and the coefficient selection circuit. be able to.

  As described above, according to the present invention, it is possible to realize a reduction in the number of processing cycles by parallelization, a reduction in the number of worst-case cycles, and simplification of control by a fixed latency of processing.

The block diagram which shows the image decoding apparatus of the 1st Embodiment of this invention. The figure explaining the decoding operation | movement of last_significant_coeff_flag / significant_coeff_flag in the last_significant_coeff_flag decoding circuit of FIG. The figure which shows the coefficient selection table of the high-order side or low-order side in a 4-pixel unit. The figure which shows the process example which determines the index of the coefficient row | line | column reproduced by drawing the coefficient selection table of FIG. The figure explaining the relationship between the bank of a level buffer and the bank of a coeff buffer about two examples of the parameter showing the presence or absence of the non-zero coefficient obtained from AB sequence. The block diagram which shows the image decoding apparatus of the 2nd Embodiment of this invention. The block diagram which shows the image decoding apparatus of the related technology of this invention. FIG. 8 is a schematic diagram illustrating a decoding method according to the related technology in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100A, 100B ... Image decoding apparatus 101 ... Syntax decoder 102 ... Level decoding circuit 103 ... Level buffer (input side buffer)
104 ... last_significant_coeff_flag decoding circuit 105a ... upper coefficient selection circuit 105b ... lower coefficient selection circuit 106 ... coeff buffer (output buffer)
DESCRIPTION OF SYMBOLS 107 ... Zigzag scan circuit 108a ... Upper side coefficient selection table 108b ... Lower side coefficient selection table 110 ... Bypass selection circuit 111 ... Zero selection circuit

Claims (5)

An image decoding device that inputs a non-zero coefficient sequence that does not include a zero coefficient of a predetermined video format, decodes, and reproduces the original coefficient sequence including the zero coefficient,
An input buffer for storing the non-zero coefficient sequence before an index is determined;
Means for generating a parameter indicating a position where a zero coefficient is inserted between the non-zero coefficient sequences, and generating a plurality of parameters used by being divided into a plurality for each predetermined processing unit;
An output buffer for storing a coefficient sequence including the zero coefficient whose index is determined;
Provided for each of the plurality of divided processing units, and corresponding to a plurality of inputs by the plurality of divided parameters, outputs the positions of zero coefficients and non-zero coefficients and the number of non-zero coefficients in the output buffer. Multiple tables that can
Provided for each of the plurality of divided processing units, and according to the output of the plurality of tables, determine the zero coefficient and non-zero coefficient indexes of the coefficient sequence to be reproduced, from the input side buffer to the output side buffer A plurality of coefficient selection circuits that transfer non-zero coefficients and write zero coefficients to the output side buffer;
An image decoding apparatus characterized by simultaneously determining an index for a reproduced coefficient sequence including a zero coefficient. A bypass selection circuit that receives the parameter as an input, determines when no non-zero coefficient is included in the processing unit, and outputs a determination signal;
A zero selection circuit that outputs the coefficient sequence of the processing unit as zero to the output side buffer when the determination signal indicates that there is no non-zero coefficient;
The image decoding apparatus according to claim 1, further comprising:   The parameter is generated by using a first flag indicating the presence or absence of a non-zero coefficient and a second flag indicating a final non-zero coefficient, and a first flag reflecting the second flag The image decoding device according to claim 1, wherein the image decoding device is an image decoding device.   The plurality of tables include a first coefficient selection table on the upper bit side and a second coefficient selection table on the lower bit side, and the plurality of coefficient selection circuits include the first coefficient selection circuit on the upper bit side and the lower bit. In the first coefficient selection circuit, the storage position of the input buffer to be read by the value of the non-zero coefficient table-drawn by the second coefficient selection table is set in the first coefficient selection circuit. The image decoding device according to claim 1, wherein the image decoding device is shifted. An image decoding method for inputting a non-zero coefficient sequence that does not include a zero coefficient of a predetermined video format, decoding, and reproducing the original coefficient sequence including the zero coefficient,
Dividing a parameter indicating a position for inserting a zero coefficient between the non-zero coefficient sequences into predetermined processing units;
For the plurality of tables provided for each of the plurality of divided processing units, the storage position of the non-zero coefficient sequence of the input side buffer storing the non-zero coefficient sequence and the index corresponding to the reproduced coefficient sequence Refer to the table for the storage position of the coefficient sequence of the output buffer after the decision,
An image decoding method characterized by simultaneously calculating an index corresponding to a reproduced coefficient sequence including a zero coefficient.

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