JP2010004112A - Communication circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication circuit which can correct the phase of a transmission signal in such a manner that the variation of phase falls within a predetermined range. <P>SOLUTION: A mixer 19 generates a transmission signal, i.e., an RF signal, and a phase detection circuit 31 detects a phase difference between the RF signal and a reference signal, i.e., an LO signal. On the basis of the phase difference detected by the phase detection circuit 31, a phase regulation circuit 32 regulates the phase of the RF signal in such a manner that the phase of the RF signal is equalized to the phase of the LO signal. Consequently, the phase of the RF signal falls within a predetermined range with reference to the LO signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a communication circuit mounted on a wireless communication device such as a mobile phone, and more particularly to a communication circuit including a transmission circuit that outputs a transmission signal representing transmission information to be transmitted.

  A wireless communication LSI (Large Scale Integration) mounted on a wireless communication device such as a cellular phone has a gain variable function for changing the gain of the amplifier, that is, the gain, in order to adjust the transmission output of the transmission signal. . Changing the gain changes the signal phase. When the amount of phase change due to the gain change exceeds a predetermined range, a signal transmitted from a radio communication device on the transmission side (hereinafter also referred to as “transmission side communication device”) is transmitted to a radio communication device on the reception side (hereinafter referred to as “reception side”). In some cases, the phase change amount is limited to a predetermined range in the wireless communication LSI.

  A conventional LSI for wireless communication is provided with a table including a gain and a representative value of a phase corresponding to the gain so that the amount of phase change is within a predetermined range, and is output by referring to the table according to the set gain. A method of correcting the phase of a transmission signal (hereinafter referred to as “table method”) is employed (see, for example, Patent Documents 1 and 2).

JP 2006-345490 A JP 2005-28695 A

  The above-described LSI for wireless communication is configured to hold a representative value of the phase corresponding to the gain and to correct the phase of the transmission signal by a table system using this. Therefore, with respect to the process variation, the power supply voltage (Voltage) variation, and the temperature (Temperature) variation (hereinafter may be collectively referred to as “PVT variation”), it is within a predetermined range based on the representative value of the phase. Therefore, it is necessary to design the circuit so that the phase of the transmission signal is within the range.

  Even if the circuit is designed in this way, if the circuit has a large phase PVT variation, there is a problem that the phase of the transmission signal cannot be corrected and the yield deteriorates. If another circuit configuration is adopted to keep the phase within a predetermined range, other characteristics, such as operating current, are deteriorated. In addition, in a communication standard with a high data rate such as WCDMA (Wideband Code Division Multiple Access), there is a tendency that the allowable range of the phase change amount tends to be narrow, so that the design becomes difficult and the specification cannot be satisfied.

  It is an object of the present invention to provide a communication circuit capable of correcting the phase of a transmission signal so that the amount of change is within a certain allowable range.

  The communication circuit according to the present invention includes a transmission signal generation unit that generates a transmission signal representing transmission information to be transmitted, a phase detection unit that detects a phase difference between the transmission signal and a predetermined reference signal, and the phase detection unit And a phase adjusting means for adjusting the phase of the transmission signal so that the phase of the transmission signal and the phase of the reference signal are equal to each other based on the phase difference detected by.

  According to the communication circuit of the present invention, the transmission signal is generated by the transmission signal generation unit, and the phase difference between the transmission signal and the reference signal is detected by the phase detection unit. Based on the phase difference detected by the phase detection means, the phase of the transmission signal is adjusted by the phase adjustment means so that the phase of the transmission signal is equal to the phase of the reference signal. As a result, the phase of the transmission signal can be kept within a certain range with reference to the reference signal, so even if there are variations such as process variations, power supply voltage variations, temperature variations, and assembly variations, The phase of the signal can be corrected so that the amount of change is within a certain allowable range. Therefore, even if the circuit has a large variation as described above, it is not necessary to consider the phase of the transmission signal, so that the circuit design can be widened. Further, since it is not necessary to sacrifice other performance in order to keep the phase of the transmission signal within a certain range, for example, the circuit can be designed in consideration of productivity, and the yield can be improved.

<Prerequisite technology>
Before describing a communication semiconductor integrated circuit which is an embodiment of a communication circuit of the present invention, a communication semiconductor integrated circuit which is a premise of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a communication semiconductor integrated circuit 1 which is a prerequisite technology of the present invention.

  The communication semiconductor integrated circuit 1 is a radio communication LSI that includes a transmission circuit that is mounted on a radio communication device such as a mobile phone and transmits a signal to a reception side communication device such as a base station. The communication semiconductor integrated circuit 1 includes a table storage unit 11, a phase adjustment circuit 12, a D / A converter (Digital Analog Converter; DAC) 13, a low pass filter (abbreviation: LPF) 14, and a first variable gain. Amplifier (Variable Gain Amplifier; abbreviation: VGA) 15, local oscillator (Local Oscillator) 16, frequency divider 17, local buffer 18, mixer 19, second variable gain amplifier 20 and high power amplifier (abbreviation: HPA) ) 21. The table storage unit 11, the phase adjustment circuit 12, the DAC 13, the LPF 14, the first VGA 15, the local oscillator 16, the frequency divider 17, the local buffer 18, the mixer 19, the second VGA 20, and the HPA 21 function as a transmission circuit.

  In the communication semiconductor integrated circuit 1, a baseband (abbreviation: BB) signal output from a baseband signal generation circuit (not shown) provided in the preceding stage is input to the phase adjustment circuit 12 and gain control (not shown). A gain control (abbreviation: GC) signal output from the signal generation circuit is input to the table storage unit 11. The BB signal is generated based on transmission information to be transmitted.

  The table storage unit 11 stores a phase table in which a GC signal given from the gain control signal generation circuit and a corresponding phase adjustment amount are associated with each other. Based on the GC signal, the table storage unit 11 gives phase information representing the phase corresponding to the gain represented by the GC signal to the phase adjustment circuit 12.

  The phase adjustment circuit 12 changes the delay time of the BB signal based on the BB signal given from the baseband signal generation circuit and the phase information given from the table storage unit 11, so that the first VGA 15 and the local buffer in the subsequent stage are changed. 18. Adjust the phase of the output signal in the second VGA 20 and the HPA 21. The signal whose phase is adjusted by the phase adjustment circuit 12 is input to the DAC 13.

  The DAC 13 converts the signal supplied from the phase adjustment circuit 12 from a digital signal to an analog signal. The signal output from the DAC 13 is input to the LPF 14. The LPF 14 attenuates and cuts off a frequency signal higher than a predetermined threshold value, and allows only a signal having a low frequency below the threshold value to pass. The signal output from the LPF 14 is input to the first VGA 15.

  The first VGA 15, the second VGA 20, and the HPA 21 amplify the input signal with a gain corresponding to a changeable set value. Specifically, the first VGA 15 amplifies and outputs the input voltage of the signal given from the LPF 14 with a gain according to a desired set value. The signal output from the first VGA 15 is input to the mixer 19. The second VGA 20 and HPA 21 will be described later.

  The local oscillator 16 generates a local oscillation signal (hereinafter sometimes referred to as “LO signal”) having a predetermined oscillation frequency, for example, 4 GHz. The LO signal is a carrier wave signal for carrying transmission information and corresponds to a reference signal. The LO signal generated by the local oscillator 16 is supplied to the frequency divider 17. The frequency divider 17 divides the LO signal supplied from the local oscillator 16 by a predetermined frequency division ratio. Here, the frequency division ratio is ½, and the LO signal is divided by ½. That is, the frequency divider 17 divides the 4 GHz LO signal by 1/2 to generate a 2 GHz LO signal. The signal divided by the frequency divider 17 is input to the local buffer 18.

  The local buffer 18 increases the amplitude of the LO signal supplied from the frequency divider 17 and converts the waveform of the LO signal. For example, when the LO signal is a sine wave signal, the sine wave signal is converted into another waveform signal, such as a rectangular wave signal. The signal output from the local buffer 18 is input to the mixer 19.

  The mixer 19 generates a transmission signal representing transmission information. The mixer 19 mixes the signal output from the first VGA 15 with the signal output from the local buffer 18, specifically, multiplies the frequency to convert the signal, thereby generating a radio frequency (abbreviation: RF) as a transmission signal. ) Generate a signal. The RF signal generated by frequency conversion by the mixer 19 is input to the second VGA 20.

  The second VGA 20 amplifies the input voltage of the signal given from the mixer 19 with a gain according to a desired set value and outputs the amplified voltage. The signal output from the second VGA 20 is input to the HPA 21. The HPA 21 amplifies the signal given from the second VGA 20 to a desired output value and outputs the amplified signal. More specifically, the HPA 21 distributes an input signal, amplifies it with a plurality of amplifying elements, and synthesizes and outputs the signals amplified by the amplifying elements. Specifically, the HPA 21 is a high output voltage amplifier that distributes an input signal, amplifies the input voltage of the signal with a plurality of amplification elements, and synthesizes the signals whose voltages are amplified with each amplification element. And output. A signal output from the HPA 21 is transmitted from a transmitting antenna (not shown) to another wireless communication device functioning as a receiving communication device such as a base station.

  Thus, the first VGA 15, the mixer 19, the second VGA 20, and the HPA 21 function as a modulation circuit that modulates the LO signal output from the local oscillator 16 with the BB signal.

  In a modulation circuit in an LSI for wireless communication, the circuit itself generates noise, so that in addition to widening the variable variable range, good noise characteristics are required. In order to widen the variable range of the gain, it is necessary to provide a plurality of amplifiers for changing the gain. However, if the amplifiers are stacked vertically, noise will accumulate. Therefore, in the communication semiconductor integrated circuit 1 of the base technology, in order to realize a wide variable gain range and good noise characteristics, a plurality of Gilbert cell mixers are arranged side by side and connected by a so-called R2R circuit. A modulation circuit is configured.

  In the modulation circuit having such a configuration, the phase of the output signal is likely to change as the gain is changed. When the amount of phase change due to the gain change exceeds a predetermined range, the signal transmitted from the transmitting communication device on which the communication semiconductor integrated circuit 1 is mounted may not be properly received by the receiving communication device such as a base station. is there.

  Therefore, in the communication semiconductor integrated circuit 1 of the base technology, a phase table is stored in the table storage unit 11 and the phase of the BB signal is adjusted by the phase adjustment circuit 12 based on this phase table.

  Since the phase of the output signal of the wireless communication LSI has PVT variations such as process variation, power supply voltage variation, and temperature variation, the wireless communication LSI considers the PVT variation and the phase of the output signal is predetermined. Therefore, it is necessary to design the circuit so as to be within the allowable range.

  As described above, the value held as the phase corresponding to each gain in the phase table is a typical value, and therefore, in a circuit with a large phase PVT variation, even if the phase table is used, the output signal Thus, the phase cannot be corrected within the allowable range, resulting in poor yield.

  Further, if another circuit configuration is employed to keep the phase within an allowable range, other characteristics are sacrificed and the yield is deteriorated. In addition, in a communication standard with a high data rate such as WCDMA, the allowable range of the phase change amount tends to be narrowed, which makes designing difficult.

  Therefore, the communication semiconductor integrated circuit of the present invention employs the configuration shown in FIG.

<First Embodiment>
FIG. 2 is a block diagram showing a configuration of the communication semiconductor integrated circuit 30 according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a specific configuration of the phase detection circuit 31. FIG. 4 is a diagram showing a circuit configuration of the Gilbert cell type phase detector 35.

  The communication semiconductor integrated circuit 30 is a communication circuit. More specifically, like the communication semiconductor integrated circuit 1 shown in FIG. 1, the communication semiconductor integrated circuit 30 is mounted on a wireless communication device such as a cellular phone and receives on the receiving side communication such as a base station. A wireless communication LSI including a transmission circuit that transmits a transmission signal to a device. The configuration of the communication semiconductor integrated circuit 30 shown in FIG. 2 is similar to the configuration of the communication semiconductor integrated circuit 1 shown in FIG. 1, so only the different parts will be described, and the same reference numerals are used for the corresponding parts. In addition, a common description is omitted.

  The communication semiconductor integrated circuit 30 includes a DAC 13, an LPF 14, a first VGA 15, a local oscillator 16, a frequency divider 17, a phase detection circuit 31, a phase adjustment circuit 32, a local buffer 18, a mixer 19, a second VGA 20, and high output amplification means. It is configured with a certain HPA 21. The phase detection circuit 31 includes a phase detector 35, an A / D converter (abbreviation: ADC) 36, and a decoder 37. The first VGA 15, the second VGA 20, and the HPA 21 correspond to variable gain amplification means. The mixer 19 corresponds to transmission signal generation means for generating a transmission signal, and generates an RF signal as the transmission signal.

  In the communication semiconductor integrated circuit 1 shown in FIG. 1, the table storage unit 11 for storing the phase table and the phase adjustment circuit 12 are provided in the preceding stage of the DAC 13, but the communication semiconductor integrated circuit shown in FIG. In the circuit 30, neither the table storage unit 11 nor the phase adjustment circuit 12 is provided upstream of the DAC 13. In the communication semiconductor integrated circuit 30, a phase adjustment circuit 32 is provided after the first VGA 15 and between the frequency divider 17 and the local buffer 18. In the communication semiconductor integrated circuit 30, a phase detection circuit 31 is provided between the frequency divider 17 and the phase adjustment circuit 32. The phase detection circuit 31 corresponds to a phase detection unit, and the phase adjustment circuit 32 corresponds to a phase adjustment unit.

  In the present embodiment, the phase detection circuit 31, the phase adjustment circuit 32, the local buffer 18, the mixer 19 and the second VGA 20 form a loop for adjusting the phase of the transmission signal that is the output signal in the communication semiconductor integrated circuit 30. Yes. This loop functions as a calibration circuit that adjusts the phase of the transmission signal.

  In the present embodiment, the DAC 13, the LPF 14, the first VGA 15, the local oscillator 16, the frequency divider 17, the phase detection circuit 31, the phase adjustment circuit 32, the local buffer 18, the mixer 19, and the second VGA 20 are formed on a semiconductor chip as a semiconductor integrated circuit. The HPA 21 is provided outside the semiconductor chip.

  In the communication semiconductor integrated circuit 30, the BB signal output from a baseband signal generation circuit (not shown) provided in the preceding stage is input to the DAC 13. In this embodiment, the baseband signal generation circuit is provided in a semiconductor chip separate from the semiconductor chip in which the DAC 13 and the like are provided. The BB signal input to the DAC 13 is input to the mixer 19 via the LPF 14 and the first VGA 15 as in the communication semiconductor integrated circuit 1 shown in FIG.

  The local oscillator 16 generates an LO signal. The LO signal generated by the local oscillator 16 is supplied to the frequency divider 17. The LO signal divided by the frequency divider 17 is supplied to the phase detection circuit 31 and the phase adjustment circuit 32.

  The LO signal supplied from the frequency divider 17 and the RF signal output from the second VGA 20 are input to the phase detection circuit 31. More specifically, the LO signal and the RF signal are input to the phase detector 35 constituting the phase detection circuit 31.

  The phase detector 35 detects the difference between the phase of the LO signal and the phase of the RF signal, that is, the phase difference between the LO signal and the RF signal, based on the input LO signal, and the phase of the detected LO signal. A signal representing the difference from the phase of the RF signal (hereinafter also referred to as “phase difference signal”) is applied to the DAC 36.

  The phase detector 35 of the present embodiment is configured by a phase detector (hereinafter referred to as “Gilbert cell type phase detector”) composed of a differential circuit called a Gilbert cell. Hereinafter, when the Gilbert cell type phase detector is shown, the same reference numeral “35” as that of the phase detector is given.

  The Gilbert cell type phase detector 35 includes MOS field effect transistors (hereinafter referred to as “MOSFETs”) Q1, Q11, Q12, Q21, Q22, Q23, Q24 and resistance elements R1, R2. One end of the resistor element R1 and one end of the resistor element R2 are connected to the power supply voltage. The other end of resistance element R1 is connected to the drains of MOSFETs Q21 and Q23, and the other end of resistance element R2 is connected to the drains of MOSFETs Q22 and Q24.

  The LO signal input terminal to which the LO signal is input is connected to the gates of MOSFETs Q21 and Q24. The / LO signal input terminal to which a signal that is 180 degrees out of phase with the LO signal is input is connected to a common connection line to which the gates of the MOSFETs Q22 and Q23 are connected in common.

  The source of MOSFET Q21 and the source of MOSFET Q22 are connected to each other, and the connection point between the sources of MOSFETs Q21 and Q22 is connected to the drain of MOSFET Q11. The source of MOSFET Q23 and the source of MOSFET Q24 are connected to each other, and the connection point between the sources of MOSFETs Q23 and Q24 is connected to the drain of MOSFET Q12.

  The RF signal input terminal to which the RF signal is input is connected to the gate of the MOSFET Q11. A signal whose phase is different from that of the RF signal by 180 degrees is input / RF signal input terminal is connected to the gate of MOSFET Q12.

  A bias voltage input terminal to which the bias voltage V is applied is connected to the gate of the MOSFET Q1. The source of MOSFET Q11 and the source of MOSFET Q12 are connected to each other, and the connection point between the sources of MOSFETs Q11 and Q12 is connected to the drain of MOSFET Q1. The source of the MOSFET Q1 is connected to the ground.

  By inputting the LO signal and / LO signal having a large signal level to the upper stage of the Gilbert cell type phase detector 35 and inputting the RF signal and / RF signal to the lower stage, the Gilbert cell type phase detector 35 has the DC A (Direct Current) signal and a second harmonic signal are output. The DC signal is a phase difference signal corresponding to the phase difference between the RF signal and the LO signal, and outputs a signal level related to the phase between the LO signal and the RF signal. Therefore, by adjusting the phase of the RF signal so that the DC signal is adjusted to a predetermined output level based on the DC signal, the phase of the RF signal that is the output signal can be kept constant.

  The DAC 36 converts the phase difference signal supplied from the phase detector 35 from an analog signal to a digital signal. The phase difference signal output from the ADC 36 is input to the decoder 37. The decoder 37 decodes the phase difference signal given from the ADC 36. The phase difference signal decoded by the decoder 37 is input to the phase adjustment circuit 32.

  The phase adjustment circuit 32 receives the LO signal supplied from the frequency divider 17 and the phase difference signal supplied from the phase detection circuit 31. The phase adjustment circuit 32 makes the phase of the RF signal equal to the phase of the LO signal based on the difference between the phase of the LO signal based on the phase difference signal and the phase of the RF signal, that is, the phase difference between the LO signal and the RF signal. In this way, the phase of the RF signal is adjusted. Specifically, the phase adjustment circuit 32 adjusts the phase of the RF signal by adjusting the phase of the LO signal so that the phase of the RF signal is equal to the phase of the LO signal.

  For example, if the phase of the RF signal output from the second VGA 20 is ahead of the phase of the LO signal output from the frequency divider 17, the phase detection circuit 31 outputs a positive (+) voltage value. . The phase adjustment circuit 32 receives the positive voltage value output from the phase detection circuit 31 and increases the capacitance value added to the output node of the phase adjustment circuit 32. Therefore, the signal output from the phase adjustment circuit 32 has a long delay time, and the phase of the RF signal output from the second VGA 20 is delayed as compared with that before the phase adjustment by the phase adjustment circuit 32. As a result, the phase of the RF signal output from the second VGA approaches the phase of the LO signal output from the frequency divider 17. The LO signal whose phase is adjusted by the phase adjustment circuit 32 is input to the mixer 19 via the local buffer 18.

  The mixer 19 multiplies the signal output from the first VGA 15 by the phase adjustment circuit 32 and the signal output from the local buffer 18 and performs frequency conversion to generate an RF signal that is a transmission signal. . The signal frequency-converted by the mixer 19 is input to the second VGA 20. The second VGA 20 amplifies the input voltage of the signal given from the mixer 19 with a gain according to a desired set value, and outputs an RF signal. The RF signal output from the second VGA 20 is input to the HPA 21 and also input to the phase detection circuit 31.

  As described above, in the present embodiment, the mixer 19 generates an RF signal that is a transmission signal, and this RF signal, specifically, the RF signal amplified by the second VGA 20 and the LO signal that is a reference signal The phase difference is detected by the phase detection circuit 31. Based on the phase difference detected by the phase detection circuit 31, the phase of the RF signal is adjusted by the phase adjustment circuit 32 so that the phase of the RF signal is equal to the phase of the LO signal. As a result, the phase of the RF signal can be kept within a certain range based on the LO signal.

  In particular, in the present embodiment, a loop is formed by the phase detection circuit 31, the phase adjustment circuit 32, the local buffer 18, the mixer 19 and the second VGA 20, and an RF signal output from the second VGA 20 is fed back to the phase detection circuit 31. Thus, when the phase of the output signal of the phase adjustment circuit 32 is changed, the phase of the RF signal is also changed in proportion thereto. Therefore, the phase change of the RF signal can be detected by the phase detection circuit 31, and the phase of the RF signal can be kept constant by adjusting the phase of the output signal of the phase adjustment circuit 32.

  In this way, the phase of the RF signal output from the second VGA 20 can be made the same as the phase of the LO signal by the phase detection circuit 31 and the phase adjustment circuit 32. In this way, the RF signal having the same phase as the LO signal is input to the HPA 21.

  Thereby, even when the gains of the first VGA 15 and the second VGA 20 are changed, the phase of the RF signal can be kept within a certain range with reference to the LO signal. Even when the gain is not changed, it is similarly effective for the change of the phase of the output signal due to the temperature change and the change of the power supply voltage. Specifically, even when there are variations such as process variations, power supply voltage variations, temperature variations, and assembly variations, the phase of the RF signal is corrected so that the amount of change is within a certain allowable range. be able to.

  Therefore, it is not necessary to consider the phase of the RF signal even in a circuit with a large variation as described above, so that the circuit design range can be expanded. Further, since it is not necessary to sacrifice other performance in order to keep the phase of the RF signal within a certain range, for example, a circuit can be designed in consideration of productivity, and the yield can be improved.

  In this embodiment, an LO signal called phase jitter having a small phase noise is used as the reference signal, so that the output phase of the transmission signal can be made constant with high accuracy. Further, since the phase detection circuit 31 and the like can be shared with the phase inversion type carrier leak calibration circuit, it is possible to minimize the addition of the circuit and to minimize the increase in the area of the semiconductor chip. is there.

  The phase detection circuit 31 of the present embodiment can be configured by another phase detection circuit 31A shown in FIG. 5 instead of the configuration shown in FIG. FIG. 5 is a block diagram showing a specific configuration of another phase detection circuit 31A. FIG. 6 is a diagram showing an exclusive OR (XOR) gate 39. The other phase detection circuit 31A includes a limiter amplifier 38, a digital phase detector 39, and a decoder 37. The limiter amplifier 38 receives the LO signal supplied from the frequency divider 17 and the RF signal output from the second VGA 20. The limiter amplifier 38 amplifies the LO signal and the RF signal, converts the amplified signal into a rectangular wave having a predetermined amplitude, and outputs the rectangular wave. The LO signal and the RF signal converted into a rectangular wave by the limiter amplifier 38 are input to the digital type phase detector 39.

  In the present embodiment, the digital phase detector 39 in the phase detection circuit 31A is configured by an exclusive OR (XOR) gate. Hereinafter, the XOR gate is denoted by the same reference numeral “39” as that of the digital type phase detector. The XOR gate 39 performs an XOR operation on the input LO signal converted into the rectangular wave and the RF signal converted into the rectangular wave, and outputs the operation result. A signal representing the result of the XOR operation by the XOR gate 39 is input to the decoder 37. The decoder 37 decodes the phase difference signal which is the operation result given from the XOR gate 39 which is a digital phase detector. The phase difference signal decoded by the decoder 37 is input to the phase adjustment circuit 32.

  Thus, by using the digital type phase detector 39 as the phase detector, that is, by configuring the phase detector with a digital circuit, the phase detection circuit 31A can be simplified, and therefore, in the semiconductor chip of the phase detection circuit 31A Occupied area and current consumption can be reduced.

  Since the LO signal and the RF signal given to the phase detection circuit 31A are analog signals, a limiter amplifier 38 is provided in front of the digital type phase detector 39 in order to configure the phase detector with a digital circuit. Yes. The input level of the RF signal and LO signal input to the digital type phase detector 39 is amplified by the limiter amplifier 38 and adjusted to the logic level, so that it can be handled as a digital signal.

<Second Embodiment>
FIG. 7 is a block diagram showing a configuration of a communication semiconductor integrated circuit 40 according to the second embodiment of the present invention. The communication semiconductor integrated circuit 40 is a communication circuit similar to the communication semiconductor integrated circuit 30 shown in FIG. 2, and more specifically, is mounted on a wireless communication device such as a cellular phone, and receives on the receiving side communication such as a base station. A wireless communication LSI including a transmission circuit that transmits a transmission signal to a device. The configuration of the communication semiconductor integrated circuit 40 shown in FIG. 7 is similar to the configuration of the communication semiconductor integrated circuit 30 shown in FIG. 2, so only the different parts will be described, and the same reference numerals will be given to the corresponding parts. In addition, a common description is omitted.

  The semiconductor integrated circuit for communication 40 includes a DAC 13, an LPF 14, a first VGA 15, a local oscillator 16, a frequency divider 17, a phase detection circuit 31, a phase adjustment circuit 32, a local buffer 18, a mixer 19, a second VGA 20, an HPA 21, and a received signal strength detection. A circuit (Received Signal Strength Indicator; abbreviation: RSSI) 41 and a coupler 42 are provided.

  The communication semiconductor integrated circuit 40 according to the present embodiment is configured to supply the RF signal output from the HPA 21 to the phase detection circuit 31 by electromagnetic coupling via the coupler 42 and to supply the RF signal to the RSSI 41. . The RSSI 41 detects the signal strength of the RF signal output from the HPA 21 and applied via the coupler 42, in other words, the power of the RF signal.

  The phase detection circuit 31 of the present embodiment receives the LO signal supplied from the frequency divider 17 and the RF signal supplied from the HPA 21 via the coupler 42. Therefore, in this embodiment, the phase detection circuit 31, the phase adjustment circuit 32, the local buffer 18, the mixer 19, the second VGA 20 and the HPA 21 form a loop for adjusting the phase of the output signal in the communication semiconductor integrated circuit 40. . The phase detection circuit 31 detects the phase difference between the RF signal amplified by the HPA 21 and the LO signal as the phase difference between the RF signal and the LO signal.

  As described above, in the present embodiment, the phase detection circuit 31 takes in the RF signal output from the HPA 21 via the coupler 42 and detects the phase difference between the RF signal amplified by the HPA 21 and the LO signal.

  When the communication semiconductor integrated circuit 40 is a transceiver LSI, that is, a wireless communication LSI, an HPA 21 that is a high output power amplifier is provided at the final stage of the transmission system. The HPA 21 also has variations, and when the passing phase that is the phase of the RF signal that can pass through the HPA 21 changes due to a temperature change or the like, the phase of the RF signal changes on the time axis. Therefore, the HPA 21 needs to be assigned a phase change amount and have a margin, but this reduces the allowable range of the phase change amount as a whole of the transceiver LSI, so that the specification becomes strict. There's a problem.

  In the present embodiment, since the output signal of the HPA 21 is input to the phase detection circuit 31, the phase of the output signal in the entire transmission system including the HPA 21 can be corrected. Therefore, the specification of the phase change amount can be relaxed and the phase accuracy of the output signal can be improved.

  When the HPA 21 is provided outside the semiconductor chip on which the DAC 13 or the like is provided as in this embodiment, an external signal that is a signal outside the semiconductor chip, specifically, an output signal of the HPA 21 is input into the semiconductor chip. By doing so, it is possible to make the phase of the output signal constant not only for the signal in the semiconductor chip but also for the external signal.

<Third Embodiment>
FIG. 8 is a block diagram showing a configuration of a communication semiconductor integrated circuit 45 according to the third embodiment of the present invention. The communication semiconductor integrated circuit 45 is a communication circuit similar to the communication semiconductor integrated circuit 40 shown in FIG. 7, and more specifically, is mounted on a wireless communication device such as a mobile phone, and receives side communication such as a base station. A wireless communication LSI including a transmission circuit that transmits a transmission signal to a device. Since the configuration of the communication semiconductor integrated circuit 45 shown in FIG. 8 is similar to the configuration of the communication semiconductor integrated circuit 40 shown in FIG. 7, only different portions will be described, and the same reference numerals are used for the corresponding portions. In addition, a common description is omitted.

  The communication semiconductor integrated circuit 45 includes a DAC 13, LPF 14, first VGA 15, local oscillator 16, frequency divider 17, phase detection circuit 31, equalizer 46, local buffer 18, mixer 19, second VGA 20, HPA 21, RSSI 41 and coupler 42. Configured.

  The communication semiconductor integrated circuit 45 includes an equalizer 46 instead of the phase adjustment circuit 32 of the communication semiconductor integrated circuit 40 shown in FIG. The equalizer 46 is connected in parallel with the local buffer 18. The phase difference signal output from the phase detection circuit 31 is input to the equalizer 46. Further, the LO signal output from the frequency divider 17 is input to the equalizer 46.

  The equalizer 46 corresponds to a phase adjusting unit, and based on the difference between the phase of the LO signal and the phase of the RF signal based on the phase difference signal given from the phase detection circuit 31, that is, based on the phase difference between the LO signal and the RF signal, The phase of the RF signal is adjusted so that the phase of the RF signal becomes equal to the phase of the LO signal. Specifically, the equalizer 46 adjusts the phase of the LO signal supplied from the local buffer 18 so that the phase of the RF signal and the phase of the LO signal are equal, and feeds back to the local buffer 18, thereby causing the RF signal to pass through. Adjust the signal phase.

  More specifically, the equalizer 46 has a function of adjusting the frequency characteristics, and the delay time of the LO signal can be changed by adjusting the frequency characteristics. Therefore, the equalizer 46 can adjust the phase of the LO signal in the same manner as the phase adjustment circuit 32 of the communication semiconductor integrated circuit 40 shown in FIG. The LO signal whose phase is adjusted by the equalizer 46 is input to the mixer 19 via the local buffer 18.

  As described above, in this embodiment, an equalizer 46 is provided instead of the phase adjustment circuit 32 of the communication semiconductor integrated circuit 40 shown in FIG. 7, and the phase of the RF signal is adjusted by the equalizer 46. As described above, even when the equalizer 46 is used, the phase of the RF signal can be kept within a certain range based on the LO signal, similarly to the first and second embodiments using the phase adjustment circuit 32. . Therefore, similarly to the first and second embodiments, even when the gain of the first VGA 15, the second VGA 20, or the HPA 21 is changed, or when there is a variation such as process variation, the phase of the RF signal is changed. Since the amount can be corrected so as to be within a certain allowable range, the width of the circuit design can be widened and the yield can be improved.

  In the second and third embodiments described above, the phase detection circuit 31 shown in FIG. 3 is used, but another phase detection circuit 31A shown in FIG. 5 is used instead of the phase detection circuit 31 shown in FIG. May be. In this case, the output signal of the HPA 21 is input to the other phase detection circuit 31A as an RF signal. Since the output level of the HPA 21 is as large as 20 dBm to 30 dBm, that is, 100 mW to 1 W, the input level of the RF signal entering the other phase detection circuit 31A is lowered to the logic level by the coupler 42, the attenuator, etc. It is necessary to adjust. Thus, it can be handled as a digital signal.

  Also in the second and third embodiments, the phase detection circuit can be simplified by using another phase detection circuit 31A and configuring the phase detector with a digital circuit. Occupied area and current consumption can be reduced.

1 is a block diagram showing a configuration of a communication semiconductor integrated circuit 1 which is a prerequisite technology of the present invention. 1 is a block diagram showing a configuration of a communication semiconductor integrated circuit 30 according to a first embodiment of the present invention. 3 is a block diagram showing a specific configuration of a phase detection circuit 31. FIG. 3 is a diagram showing a circuit configuration of a Gilbert cell type phase detector 35. FIG. It is a block diagram which shows the specific structure of 31 A of other phase detection circuits. FIG. 3 is a diagram showing an exclusive OR (XOR) gate 39. It is a block diagram which shows the structure of the semiconductor integrated circuit for communication 40 which is the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit 45 for communication which is the 3rd Embodiment of this invention.

Explanation of symbols

  1, 30, 40, 45 Communication semiconductor integrated circuit, 11 Table storage unit, 12, 32 Phase adjustment circuit, 13 DAC, 14 LPF, 15 First variable gain amplifier, 16 Local oscillator, 17 Divider, 18 Local buffer , 19 mixer, 20 second variable gain amplifier, 21 high power amplifier, 31, 31A phase detection circuit, 35 phase detector, 36 ADC, 37 decoder, 38 limiter amplifier, 39 digital type phase detector, 41 RSSI, 42 coupler 46 Equalizer.

Claims (6)

Transmission signal generating means for generating a transmission signal representing transmission information to be transmitted;
Phase detection means for detecting a phase difference between the transmission signal and a predetermined reference signal;
Phase adjustment means for adjusting the phase of the transmission signal so that the phase of the transmission signal is equal to the phase of the reference signal based on the phase difference detected by the phase detection means. Communication circuit. The transmission signal generation means generates the transmission signal by mixing a baseband signal generated based on the transmission information and a carrier wave signal for carrying the transmission information,
The reference signal is the carrier signal;
The phase adjusting means adjusts the phase of the transmission signal by adjusting the phase of the carrier signal so that the phase of the transmission signal is equal to the phase of the carrier signal. The communication circuit according to 1. Variable gain amplifying means for amplifying the transmission signal generated by the transmission signal generating means with a gain according to a changeable set value;
The communication circuit according to claim 1, wherein the phase detection unit detects a phase difference between the transmission signal amplified by the variable gain amplification unit and the reference signal as the phase difference. . High-power amplification means for amplifying and outputting the transmission signal generated by the transmission signal generation means,
The communication circuit according to claim 1, wherein the phase detection unit detects a phase difference between the transmission signal amplified by the high output amplification unit and the reference signal as the phase difference. . The phase detection means includes a Gilbert cell type phase detector that outputs a phase difference signal corresponding to a phase difference between the transmission signal and the reference signal,
The said phase adjustment means adjusts the phase of the said transmission signal based on the said phase difference signal output from the said Gilbert cell type | mold phase detector, It is any one of Claims 1-4 characterized by the above-mentioned. Communication circuit. The transmission signal and the reference signal are analog signals,
The phase detection means includes
A converter for converting the transmission signal and the reference signal into a digital signal;
A digital phase detector that outputs a phase difference signal corresponding to a phase difference between the transmission signal converted by the conversion unit and the reference signal converted by the conversion unit;
The said phase adjustment means adjusts the phase of the said transmission signal based on the said phase difference signal output from the said digital type | mold phase detector, It is any one of Claims 1-4 characterized by the above-mentioned. Communication circuit.

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