JP2010003137A - Cache memory system, cpu core, and cache memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cache memory system capable of reducing the overhead of memory access, improving the utilization efficiency of a memory, a CPU, an external device for supplying data to the memory and the like, and improving the performance of the entire system, and to provide a CPU core, and a cache memory control method. <P>SOLUTION: A higher-order memory data storage 24 reads updated data from a lower-order memory hierarchy 12 when data referred to by the CPU core 11 are the updated data, and stores the data in a higher-order memory hierarchy 15. When the higher-order memory storage section 24 stores data in the higher-order memory hierarchy 15, a memory lock device 23 locks the higher-order memory hierarchy 15. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a cache memory system.

FIG. 9 shows a conventional cache memory system as a premise of the present invention.
In the cache memory system 100 a of FIG. 9, an upper memory hierarchy (cache memory) 102 is provided between the CPU 101 and the lower memory hierarchy 103 in order to improve memory access performance. The upper memory hierarchy 102 has a faster access speed than the lower memory hierarchy 103, but has a smaller memory capacity than the lower memory hierarchy 103.

  In the cache memory system 100a having such a configuration, the data A output from the external device 104 such as an accelerator is placed in the lower memory hierarchy 103, and the CPU 101 refers to the data A output from the external device 104 and performs some operation. Think of a case.

  In this case, the data A is kept in the lower memory hierarchy 103 until the CPU 101 finishes all the processes for the data A, and when the CPU 101 finishes the process for the data A, the CPU 101 has the upper memory hierarchy 102 and the lower memory hierarchy. After invalidating the data 103, the external device 104 is started to write the next data B into the lower memory hierarchy 103. Therefore, a waiting time occurs in the external device 104, and processing efficiency is poor.

Since the overall system performance does not improve with the method shown in FIG. 9, a configuration of a cache memory system 100b in which the lower memory hierarchy 103 is a double buffer is often adopted.
FIG. 10 shows a configuration of a cache memory system 100b in which the lower memory hierarchy is a double buffer.

  In the double buffer cache memory system 100b, the next data is overlapped in the area where the data moved in the upper memory hierarchy 102 on the lower memory hierarchy 103 was recorded.

  As shown in FIG. 10, when the lower memory hierarchy 103 has a double buffer configuration, the processing of data A and the processing of data B can be overlapped, so that the overall throughput is improved as compared with the cache memory system of FIG. To do.

  Various configurations of cache memory systems have been proposed. As an example, Patent Document 1 discloses a cache memory system in advance in order to shorten the data processing time, regardless of the presence or absence of instructions from the processor. A cache memory system that reads data into a memory is disclosed.

  Patent Document 2 discloses a cache memory system in which the upper cache memory and the lower cache memory do not have the same data at the same time so that the memory capacity is effectively utilized.

Further, in the cache memory system disclosed in Patent Document 3, a priority attribute indicating the type of data to be preferentially stored is held for each of a plurality of ways including a plurality of entries holding data and tags. As a result, a way is secured for data having a priority attribute, and at the same time, empty entries in the way store data having other attributes, so that the cache memory can be used effectively.
JP-A-9-128296 Japanese Patent Laid-Open No. 5-127997 JP 2005-346268 A

  In the conventional cache memory system, depending on the execution state of the program, there is a possibility that data in the upper memory hierarchy may be expelled to the lower memory hierarchy. Therefore, until the program completes use of the first data, The second data could not be placed.

In order to avoid this, the processing of the first data overlaps the processing of the next second data by adopting a double buffer configuration in the lower memory hierarchy.
However, in the cache memory system using the double buffer shown in FIG. 10, when there is data in the lower memory hierarchy 103 that is known to be used by the CPU 101, the lower memory is not used until the CPU 101 actually uses the data. Since data is read from the hierarchy 103, the read latency becomes long. And this point becomes a bottleneck, and improvement in performance cannot be expected.

  Therefore, the present invention reduces a memory access overhead, improves the utilization efficiency of a memory, a CPU, an external device for supplying data to the memory, and the like, and improves the performance of the entire system, a CPU core, and a cache It is an object to provide a memory control method.

  The cache memory system according to the present invention includes a CPU and a memory hierarchy including at least two upper memory hierarchies and lower memory hierarchies, and the CPU does not rewrite data supplied to the lower memory hierarchies. , An area storage unit, an upper memory data storage unit, and a memory lock unit.

The area storage unit stores an address of data to be updated on the lower memory hierarchy.
The upper memory data storage unit compares the address of the data referred to by the CPU with the address in the area storage unit, and when the data referred to by the CPU is the data to be updated, Read from the memory hierarchy and store data in the upper memory hierarchy.

The memory lock unit locks the upper memory hierarchy after the upper memory storage unit stores data in the upper memory hierarchy.
The CPU core according to the present invention is a CPU core connected to a lower memory hierarchy in which data is sequentially updated, an upper memory hierarchy that is faster than the lower memory hierarchy, and an instruction execution that reads and processes data from the memory. The address of the data to be updated on the lower memory hierarchy, the address of the data referenced by the instruction execution unit and the address in the area storage unit, and the data referenced by the CPU Is the data in the lower memory hierarchy, the data is read from the lower memory hierarchy and stored in the upper memory hierarchy, and the instruction execution unit is set in advance when referring to the memory. A condition completion notifying unit for instructing update of data on the lower memory hierarchy if a predetermined condition is satisfied. To.

Furthermore, a cache memory control method according to the present invention is a cache memory control method by a CPU core connected to a lower memory hierarchy in which data is sequentially updated, the address of data referred to by an instruction execution unit that executes an instruction, The address of the data to be updated on the lower memory hierarchy is compared, and when the data referenced by the CPU is the data of the lower memory hierarchy, the data is read from the lower memory hierarchy, and the higher-speed memory faster than the lower memory hierarchy Data is stored in a hierarchy, and when the instruction execution unit refers to a memory, if a preset condition is satisfied, an instruction to update data on the lower memory hierarchy is given.

  According to the cache memory system, it is possible to reduce the overhead of memory access, improve the utilization efficiency of the memory, the external device, and the CPU, and improve the performance of the entire system.

  Further, the lower memory hierarchy can be made smaller than that of the conventional system, and the entire system can be reduced and the cost can be reduced.

An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is an image diagram of a system premised on the cache memory system of the present embodiment.

  In the cache memory system 1 of this embodiment, a CPU core 11, a lower memory hierarchy 12, and an external device 13 such as a hardware accelerator that writes a large amount of data continuously to the lower memory hierarchy 12 are connected via a bus 14. It has a configuration. The CPU core 11 includes an upper memory hierarchy 15 therein.

  As long as data is sequentially written in the lower memory hierarchy 12, the one that supplies data to the lower memory hierarchy 12 is not limited to the external device 13, and the external device is included in the cache memory system 1. 13 may not be provided.

  In the cache memory system 1 of FIG. 1, the external device 13 sequentially writes data to the lower memory hierarchy 12, and the CPU core 11 refers to this data via the upper memory hierarchy 15. Note that the CPU core 11 only refers to data and does not modify it.

In the following description, a case where the cache memory system 1 is used in a system that performs video decoding processing will be described as an example.
In this case, the external device 13 is a DMAC, which periodically acquires a moving image stream from a network or the like and transfers it to the main memory which is the lower memory hierarchy 12, and the CPU core 11 having a cache memory which is the upper memory hierarchy 15 It is assumed that the moving picture stream is captured and decoded to output image data.

Next, the operation of the cache memory system 1 of this embodiment will be described.
FIG. 2 is a diagram for explaining the operation of the cache memory system 1 of the present embodiment.
In the figure, the CPU core 11 includes an upper memory release device 21, a condition completion notification device 22, an upper memory lock device 23, an upper memory data storage device 24 and an area storage device 25 in order to control the operation of the cache memory system 1. I have.

The upper memory release device 21 releases the upper memory hierarchy 15 locked by the upper memory lock device 23 based on an instruction from the CPU core 11. The condition completion notification device 22 notifies the CPU core 11 when a preset condition is satisfied. Upon receiving this notification, the CPU core 11 instructs the external device 13 to perform the next data processing. The upper memory lock device 23 locks the data stored in the upper memory hierarchy 15 so that it is not evicted. The upper memory data storage device 24 reads the specified area from the lower memory hierarchy 12 at a time and stores the data in the upper memory hierarchy 15. The area storage device 25 stores the start address and end address of the memory area updated by the external device 13.

  In such a configuration, the external device 13 first writes data to the lower memory hierarchy 12 and updates the data (1). Next, the external device 13 notifies the CPU core 11 that the update of the lower memory hierarchy 12 has been completed (2).

  The CPU core 11 tries to refer to the data written by the external device 13 in the lower memory hierarchy 12 in (1) (3). At this time, the upper memory data storage device 24 of the CPU core 11 compares the address in the area storage device 25 with the address of the reference data, and the data of the area that the CPU core 11 is trying to reference is updated in (1). If the data is determined to be data, all the data in the corresponding area is read from the lower memory hierarchy 12 at a time and stored in the upper memory hierarchy 15 (4). Further, the upper memory lock device 23 locks the data stored in the upper memory hierarchy 15 in (4) so as not to be evicted to the lower memory hierarchy 12 (5).

  The condition completion notification device 22 notifies the CPU core 11 when the CPU core 11 satisfies a preset condition such as referring to data of a specific address or referring to data of a specific value. Upon receiving this notification, the CPU core 11 instructs the external device 13 to perform the next data processing while performing processing using the data in the corresponding area (6).

  When the CPU core 11 finishes using the data in the corresponding area, the upper memory release device 21 releases the lock of the upper memory hierarchy 15 performed in (5), and performs the invalidation process of the upper memory hierarchy 15.

  FIG. 3 is a sequence diagram showing data exchange among the CPU core 11, the upper memory hierarchy 15, the lower memory hierarchy 12, and the external device 13 of the cache memory system 1 of the present embodiment.

  In the figure, the external device 13 first writes data into the lower memory hierarchy 12 and updates the data (1). When the data update is completed, the external device 13 notifies the CPU core 11 that the data update is completed (2).

  In response to this, the CPU core 11 tries to refer to the data updated in (1) (3). Since this data is not yet in the upper memory hierarchy 15, the CPU core 11 refers to the data for the lower memory hierarchy 12. With this reference, the data updated in (1) is read from the lower memory hierarchy 12 to the upper memory hierarchy 15 all at once (4). When this reading is completed, the upper memory hierarchy 15 is locked so that the data in the upper memory hierarchy 15 is not ejected (5). Thereafter, the CPU core 11 performs processing with reference to data on the upper memory hierarchy 15.

  While the CPU core 11 performs processing with reference to the data on the upper memory hierarchy 15, a predetermined condition set in advance, for example, a condition such as the CPU core 11 referring to data at a specific address is set. When the condition is satisfied, the condition completion notification device 22 notifies the CPU core 11 of this, and the CPU core 11 instructs the external device 13 to start the next data update process (6).

In response to this, the external device 13 writes the next data in the lower memory hierarchy 12. At this time, in parallel, the CPU core 11 continues the processing while referring to the data on the upper memory hierarchy 15 (7). During this time, a portion 31 where no coherency is obtained occurs between the upper memory hierarchy 15 and the lower memory hierarchy 12.

When the processing is completed, the CPU core 11 unlocks the upper memory hierarchy 15 (8).
Thereafter, the processes (3) to (8) are repeated, and the data updated by the external device 13 is sequentially processed.

  As described above, in the cache memory system 1 of the present embodiment, since the data referred to by the CPU core 11 is always in the upper memory hierarchy 15, the CPU core 11 can perform processing at high speed. Further, the processing while referring to the data by the CPU core 11 and the data update processing by the external device 13 are performed in parallel, so that the entire system can be increased in speed and performance can be improved.

  Compared with the conventional cache memory system of FIG. 9, high throughput can be realized in the entire system. Furthermore, the capacity of the lower memory hierarchy can be reduced as compared with the double buffer configuration of FIG.

Next, a case where the size of data written to the lower memory hierarchy 12 by the external device 13 is larger than the capacity of the upper memory hierarchy 15 will be described.
When the size of the data written to the lower memory hierarchy 12 by the external device 13 is larger than the capacity of the upper memory hierarchy 15, the cache memory system 1 of this embodiment reads data into the upper memory hierarchy 15 in a plurality of times.

  FIG. 4 is a diagram for explaining the operation of the cache memory system 1 according to the present embodiment when the size of data written to the lower memory hierarchy 12 by the external device 13 is larger than the capacity of the upper memory hierarchy 15.

  In the figure, the external device 13 first writes data to the lower memory hierarchy 12 and updates the data (1). Next, the external device 13 notifies the CPU core 11 that the update of the lower memory hierarchy 12 has been completed (2).

  The CPU core 11 tries to refer to the data written by the external device 13 in the lower memory hierarchy 12 in (1) (3). At this time, the upper memory data storage device 24 of the CPU core 11 compares the address in the area storage device 25 with the address of the reference data, and the data of the area in which the data that the CPU core 11 is trying to reference is updated in (1). If it is determined, the data in the corresponding area is read from the lower memory hierarchy 12 by the capacity of the upper memory hierarchy 15 at a time and stored in the upper memory hierarchy 15 (4). Further, the upper memory lock device 23 locks the data stored in the upper memory hierarchy 15 in (4) so as not to be evicted to the lower memory hierarchy 12 (5).

The processes from (1) to (5) are basically the same as those in FIG.
Next, when the CPU core 11 finishes using the data on the upper memory hierarchy 15, the upper memory release device 21 releases the lock on the upper memory hierarchy 15 performed in (5), and the upper memory hierarchy 15 An invalidation process is performed (6).

  Then, when the CPU core 11 tries to refer to the data written by the external device 13 to the lower memory hierarchy 12 in (1) outside the upper memory hierarchy 15, the data on the lower memory hierarchy 12 is transferred to the upper memory hierarchy 15. Stores the capacity of the memory hierarchy 15. The upper memory lock device 23 locks the data stored in the upper memory hierarchy 15 so that the data is not evicted to the lower memory hierarchy 12. When the CPU core 11 has finished using the data on the upper memory hierarchy 15, the upper memory release device 21 releases the lock on the upper memory hierarchy 15 and performs the invalidation process of the upper memory hierarchy 15 (7). .

The process (7) is repeated until the CPU core 11 performs all the data updated by the external device 13 in (1).
In (7), while the CPU core 11 is performing processing while referring to the data on the upper memory hierarchy 15, the CPU core 11 satisfies a preset condition such as referring to data at a specific address. Then, the condition completion notification device 22 notifies the CPU core 11 of this. Upon receiving this notification, the CPU core 11 instructs the external device 13 to perform the next data processing (8). In response to this instruction, the external device 13 transfers the next data to the lower memory hierarchy 12.

  When the data reference to the condition completion notification device 22 in (7) is completed, the CPU core 11 releases the lock on the upper memory hierarchy 15 (9).

  FIG. 5 illustrates the CPU core 11, the upper memory hierarchy 15, and the lower memory hierarchy of the cache memory system 1 according to the present embodiment when the size of data written to the lower memory hierarchy 12 by the external device 13 is larger than the capacity of the upper memory hierarchy 15. 12 is a sequence diagram showing exchange of data between 12 and an external device 13. FIG.

  In the figure, the external device 13 first writes data into the lower memory hierarchy 12 and updates the data (1). When the data update is completed, the external device 13 notifies the CPU core 11 that the data update is completed (2).

  In response to this, the CPU core 11 tries to refer to the data updated in (1) (3). Since this data is not yet in the upper memory hierarchy 15, the CPU core 11 refers to the data for the lower memory hierarchy 12. With this reference, the data updated in (1) is read from the lower memory hierarchy 12 into the upper memory hierarchy 15 for the capacity of the upper memory lock device 23 at a time (4). When this reading is completed, the upper memory hierarchy 15 is locked so that the data in the upper memory hierarchy 15 is not ejected (5). Thereafter, the CPU core 11 performs processing with reference to data on the upper memory hierarchy 15.

The processes from (1) to (5) are basically the same as those in FIG.
Next, when the CPU core 11 finishes using the data on the upper memory hierarchy 15, the lock on the upper memory hierarchy 15 performed in (5) is released (6).

  Then, when the CPU core 11 tries to refer to the data written by the external device 13 to the lower memory hierarchy 12 in (1) outside the upper memory hierarchy 15, the data on the lower memory hierarchy 12 is transferred to the upper memory hierarchy 15. Stores the capacity of the memory hierarchy 15. Further, the data stored in the upper memory hierarchy 15 is locked so as not to be evicted to the lower memory hierarchy 12. When the CPU core 11 has finished using the data on the upper memory hierarchy 15, the lock on the upper memory hierarchy 15 is released (7).

  While the CPU core 11 performs processing by referring to the data on the upper memory hierarchy 15 in (7), a specific condition set in advance, for example, the CPU core 11 refers to data at a specific address. If the above conditions are satisfied, the CPU core 11 instructs the external device 13 to start the next data update process (8).

  In response to this, the external device 13 writes the next data in the lower memory hierarchy 12. At this time, in parallel, the CPU core 11 continues the processing while referring to the data on the upper memory hierarchy 15 (9).

When the processing is completed, the CPU core 11 unlocks the upper memory hierarchy 15 (10).
Thereafter, the processes (3) to (10) are repeated, and the data updated by the external device 13 is sequentially processed.

  As described above, the cache memory system 1 according to the present embodiment can cope with the case where the amount of data transferred from the external device 13 to the lower memory hierarchy 12 is larger than the capacity of the upper memory hierarchy 15.

Next, an example in which the data update amount for updating data on the upper memory hierarchy 15 is set will be shown.
When this data update amount is set, when the upper memory layer 15 transfers data from the lower memory layer 12, a data amount of the data update amount is always transferred.

FIG. 6 is a diagram for explaining the operation of the cache memory system 1 of the present embodiment when the data update amount is set.
In the figure, the data update amount is set in the area storage device 25.

  In FIG. 6, the external device 13 first writes data to the lower memory hierarchy 12 and updates the data (1). Next, the external device 13 notifies the CPU core 11 that the update of the lower memory hierarchy 12 has been completed (2).

  The CPU core 11 tries to refer to the data written by the external device 13 in the lower memory hierarchy 12 in (1) (3). At this time, the upper memory data storage device 24 of the CPU core 11 uses the address stored in the region storage device 25 and the address of the reference data, in the region where the data that the CPU core 11 tried to reference is updated in (1). If the data is determined to be data, the data in the corresponding area is read from the lower memory hierarchy 12 by the capacity of the upper memory hierarchy 15 and stored in the upper memory hierarchy 15 (4). At this time, the amount of data read into the upper memory hierarchy 15 is a data update amount preset in the area storage device 25.

Further, the upper memory lock device 23 locks the data stored in the upper memory hierarchy 15 in (4) so as not to be evicted to the lower memory hierarchy 12 (5).
The CPU core 11 proceeds with processing while referring to the upper memory hierarchy 15. During this time, if a specific condition is satisfied, for example, the CPU core 11 refers to data at a specific address, the condition completion notification device 22 invalidates the corresponding area in the lower memory hierarchy 12 (6 ). As a result, the external device 13 transfers the next data to the lower memory hierarchy 12 in the lower memory hierarchy 12.

  When the CPU core 11 finishes referring to the data on the upper memory hierarchy 15 and tries to refer to the next data, the upper memory release device 21 recognizes this and locks the upper memory hierarchy 15 performed in (3). The invalidation processing is performed (7).

  When the upper memory hierarchy 15 is invalidated in (7), the above-described processes (4) to (7) are repeated, and the data reference process by the CPU core 11 and the external device 13 to the lower memory hierarchy 12 are repeated. Data transfer is performed in parallel.

  FIG. 7 is a sequence diagram showing data exchange among the CPU core 11, the upper memory hierarchy 15, the lower memory hierarchy 12, and the external device 13 of the cache memory system 1 of this embodiment when the data update amount is set. .

  In the figure, first, the external device 13 writes data in the lower memory hierarchy 12 and updates the data (1). When the data update is completed, the external device 13 notifies the CPU core 11 that the data update is completed (2).

  In response to this, the CPU core 11 tries to refer to the data updated in (1) (3). Since this data is not yet in the upper memory hierarchy 15, the CPU core 11 refers to the data for the lower memory hierarchy 12. By this reference, the data updated in (1) is read from the lower memory hierarchy 12 to the upper memory hierarchy 15 (4). At this time, the size of the data read into the upper memory hierarchy 15 is the size set in the area storage device 25.

  When the reading of (4) is completed, the upper memory hierarchy 15 is locked so that the data in the upper memory hierarchy 15 is not ejected (5). Thereafter, the CPU core 11 performs processing with reference to data on the upper memory hierarchy 15.

  Next, when the CPU core 11 finishes using the data on the upper memory hierarchy 15, the lock on the upper memory hierarchy 15 performed in (5) is released (6). As a result, the data on the upper memory hierarchy 15 becomes invalid.

  Then, when the CPU core 11 tries to refer to the data written by the external device 13 to the lower memory hierarchy 12 in (1) outside the upper memory hierarchy 15, the data on the lower memory hierarchy 12 is transferred to the upper memory hierarchy 15. Stores the capacity of the memory hierarchy 15. Further, the data stored in the upper memory hierarchy 15 is locked so as not to be evicted to the lower memory hierarchy 12. When the CPU core 11 has finished using the data on the upper memory hierarchy 15, the lock on the upper memory hierarchy 15 is released (7).

  While the CPU core 11 performs processing by referring to the data on the upper memory hierarchy 15 in (7), a specific condition set in advance, for example, the CPU core 11 refers to data at a specific address. If the above conditions are satisfied, the CPU core 11 instructs the external device 13 to start the next data update process (8).

  In response to this, the external device 13 writes the next data in the lower memory hierarchy 12. At this time, in parallel, the CPU core 11 continues the processing while referring to the data on the upper memory hierarchy 15 (9).

When the processing is completed, the CPU core 11 unlocks the upper memory hierarchy 15 (10).
Thereafter, the processes (3) to (10) are repeated, and the data updated by the external device 13 is sequentially processed.

  As described above, in the cache memory system 1 according to the present embodiment, even when the amount of data transferred from the external device 13 to the lower memory hierarchy 12 is larger than the capacity of the upper memory hierarchy 15, the lower memory hierarchy 12 moves to the upper memory hierarchy 15. This can be realized by dividing the data transfer into a plurality of times. In addition, the data transfer amount when transferring data from the lower memory hierarchy 12 to the upper memory hierarchy 15 can be changed in advance.

FIG. 8 is a diagram showing a detailed configuration of the cache memory related to the CPU core of the cache memory system of this embodiment.
In the figure, the configuration related to the cache memory system 1 includes a tag RAM 41, in addition to the above-described upper memory release device 21, condition completion notification device 22, upper memory lock device 23, upper memory data storage device 24 and area storage device 25. A cache RAM 42, an XOR circuit 43, and a cache fill device 44 are provided.

  The tag RAM 41 and the cache RAM 42 are memories constituting the upper memory hierarchy 15. The tag RAM 41 has tag information for determining whether the address of the data requested from the instruction execution unit 50 has hit / missed in the cache. The cache RAM 42 stores data corresponding to the tag information. Further, the tag RAM 41 has an area for storing a lock bit, and when this log bit is set, the data in the upper memory hierarchy 15 corresponding thereto (that is, the data in the cache RAM 42) is locked.

  The XOR circuit 43 performs an XOR operation on the address of the data requested from the instruction execution unit 50 and the output of the tag RAM 41 and outputs a cache hit / miss. The cache fill device 44 requests the lower memory hierarchy 12 for data of a specific size including data at the address requested by the instruction execution unit 50 based on an instruction from the upper memory data storage device 24.

  In the cache memory system 1 of the present embodiment having such a configuration, when the instruction execution unit 50 issues a request address, this is compared with the tag in the tag RAM 41, and if hit, the data is read from the cache RAM 42 and the instruction is executed. Is output to the unit 50. If a cache miss occurs, the cache fill device 44 requests data from the lower memory hierarchy 12 based on an instruction from the upper memory data storage device 24, and new data is stored in the tag RAM 41 and the cache RAM 42.

  As described above, in the cache memory system 1 of the present embodiment, the data referred to by the CPU core 11 is always in the upper memory hierarchy 15, so that the processing of the CPU core 11 becomes faster. For example, when performing moving image decoding processing, stream data for one frame is always in the cache, so that the moving image decoding processing of the CPU core 11 becomes faster.

In addition, since the processing by the CPU core 11 and the data transfer to the lower memory hierarchy 12 can be performed in parallel, the throughput of the entire system can be improved. For example, when performing moving image decoding processing, stream data of the next frame can be acquired while performing moving image decoding processing of the previous frame.
Furthermore, the capacity of the lower memory hierarchy 12 can be made smaller than that of the double buffer configuration. Therefore, it is possible to reduce the size and price of the entire system.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
In a cache memory system including a CPU and a memory hierarchy including at least two upper and lower memory hierarchies, and the CPU does not rewrite data supplied to the lower memory hierarchy,
An area storage unit for storing addresses of data to be updated on the lower memory hierarchy;
The address of the data referred to by the CPU is compared with the address in the area storage unit, and when the data referred to by the CPU is the updated data, the updated data is read from the lower memory hierarchy, An upper memory data storage unit for storing data in the memory hierarchy;
A memory lock unit for locking the upper memory hierarchy after the upper memory storage unit stores data in the upper memory hierarchy;
A cache memory system comprising:
(Appendix 2)
The CPU further includes a condition completion notifying unit for notifying the CPU when a predetermined condition is satisfied when referring to the upper memory hierarchy,
The cache memory system according to appendix 1, wherein the CPU instructs data transfer to the lower memory hierarchy in response to the notification to the CPU by the condition completion notification unit.
(Appendix 3)
An upper memory release unit for releasing the lock on the upper memory hierarchy;
Further comprising
The cache memory system according to appendix 1, wherein the upper memory release unit releases the lock of the upper memory hierarchy after the CPU finishes referring to data on the upper memory hierarchy.
(Appendix 4)
The area storage unit stores the size of data that the upper memory data storage unit stores from the lower memory hierarchy to the upper memory hierarchy,
2. The cache memory system according to appendix 1, wherein when the upper memory data storage unit stores data from the lower memory hierarchy to the upper memory hierarchy, the upper memory data storage unit stores the size of the data at a time.
(Appendix 5)
The cache memory system according to appendix 4, wherein the data size is a maximum capacity of the upper memory hierarchy.
(Appendix 6)
After the CPU finishes referring to the data on the upper memory hierarchy, the upper memory data storage unit stores data corresponding to the size of the data from the lower memory hierarchy to the upper memory hierarchy. The cache memory system according to appendix 4.
(Appendix 7)
The cache memory system according to appendix 1, further comprising an external device unit that updates data on the lower memory hierarchy.
(Appendix 8)
The cache memory system according to appendix 7, wherein the external device unit notifies the CPU of completion of update of data in the lower memory hierarchy.
(Appendix 9)
In a CPU core connected to a lower memory hierarchy in which data is sequentially updated, an upper memory hierarchy that is faster than the lower memory hierarchy;
An instruction execution unit that reads and processes data from the memory;
An area storage unit for storing addresses of data to be updated on the lower memory hierarchy;
The address of the data referenced by the instruction execution unit is compared with the address in the area storage unit. When the data referenced by the CPU is data in the lower memory hierarchy, the data is read from the lower memory hierarchy, and the upper memory An upper memory data storage unit for storing data in a hierarchy;
When the instruction execution unit refers to the memory, a condition completion notification unit that instructs to update data on the lower memory hierarchy if a preset condition is satisfied;
A CPU core comprising:
(Appendix 10)
The supplementary note 9 is characterized in that the upper memory data storage unit further comprises an upper memory lock unit that reads data from the lower memory hierarchy, stores the data in the upper memory hierarchy, and locks the upper memory hierarchy. The CPU core described.
(Appendix 11)
The CPU core according to appendix 10, further comprising an upper memory release unit that releases the lock of the upper memory hierarchy when the instruction execution unit has finished referring to the data on the upper memory hierarchy.
(Appendix 10)
In a cache memory control method by a CPU core connected to a lower memory hierarchy in which data is sequentially updated,
The address of the data referenced by the instruction execution unit that executes the instruction is compared with the address of the data to be updated on the lower memory hierarchy, and when the data referred to by the CPU is data of the lower memory hierarchy, Read data from the memory hierarchy, store the data in the upper memory hierarchy faster than the lower memory hierarchy,
When the instruction execution unit refers to the memory, if a preset condition is satisfied, an instruction to update data on the lower memory hierarchy is given.

It is an image figure of the system which the cache memory system of this embodiment assumes. It is a figure explaining operation | movement of the cache memory system of this embodiment. It is a sequence diagram which shows exchange of data of the cache memory system of this embodiment. It is a figure explaining operation | movement of the cache memory system of this embodiment when the magnitude | size of the data which an external device writes in a lower memory hierarchy is larger than the capacity | capacitance of an upper memory hierarchy. FIG. 11 is a sequence diagram showing data exchange in the cache memory system of the present embodiment when the size of data written to the lower memory hierarchy by the external device is larger than the capacity of the upper memory hierarchy. It is a figure explaining operation | movement of the cache memory system of this embodiment when a data update amount is set. It is a sequence diagram which shows exchange of data of the cache memory system of this embodiment when a data update amount is set. It is a figure which shows the detailed structure regarding the cache memory of the CPU core of the cache memory system of this embodiment. 1 is a diagram illustrating a conventional cache memory system. It is a figure which shows the structure of the cache memory system which used the lower memory hierarchy as the double buffer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Cache memory system 11 CPU core 12 Lower memory hierarchy 13 External device 14 Bus 15 Upper memory hierarchy 21 Upper memory release apparatus 22 Condition completion notification apparatus 23 Upper memory lock apparatus 24 Upper memory data storage apparatus 25 Area storage apparatus 41 Tag RAM
42 Cache RAM
43 XOR circuit 44 Cash fill device

Claims (5)

In a cache memory system including a CPU and a memory hierarchy including at least two upper and lower memory hierarchies, and the CPU does not rewrite data supplied to the lower memory hierarchy,
An area storage unit for storing addresses of data to be updated on the lower memory hierarchy;
The address of the data referred to by the CPU is compared with the address in the area storage unit, and when the data referred to by the CPU is the updated data, the updated data is read from the lower memory hierarchy, An upper memory data storage unit for storing data in the memory hierarchy;
A memory lock unit for locking the upper memory hierarchy after the upper memory storage unit stores data in the upper memory hierarchy;
A cache memory system comprising: The CPU further includes a condition completion notifying unit for notifying the CPU when a predetermined condition is satisfied when referring to the upper memory hierarchy,
2. The cache memory system according to claim 1, wherein the CPU instructs data transfer to the lower memory hierarchy in response to the notification to the CPU by the condition completion notification unit. The area storage unit stores the size of data that the upper memory data storage unit stores from the lower memory hierarchy to the upper memory hierarchy,
2. The cache memory system according to claim 1, wherein when the upper memory data storage unit stores data from the lower memory hierarchy to the upper memory hierarchy, the cache memory system stores the size of the data at a time. In a CPU core connected to a lower memory hierarchy in which data is sequentially updated, an upper memory hierarchy that is faster than the lower memory hierarchy;
An instruction execution unit that reads and processes data from the memory;
An area storage unit for storing addresses of data to be updated on the lower memory hierarchy;
The address of the data referred to by the instruction execution unit is compared with the address in the area storage unit, and when the data referred to by the CPU is data of the lower memory hierarchy, the data is read from the lower memory hierarchy, and the upper memory An upper memory data storage unit for storing data in a hierarchy;
When the instruction execution unit refers to the memory, a condition completion notification unit that instructs to update data on the lower memory hierarchy if a preset condition is satisfied;
A CPU core comprising: In a cache memory control method by a CPU core connected to a lower memory hierarchy in which data is sequentially updated,
The address of the data referenced by the instruction execution unit that executes the instruction is compared with the address of the data to be updated on the lower memory hierarchy, and when the data referred to by the CPU is data of the lower memory hierarchy, Read data from the memory hierarchy, store the data in the upper memory hierarchy faster than the lower memory hierarchy,
When the instruction execution unit refers to the memory, if the preset condition is satisfied, an instruction to update data on the lower memory hierarchy is given.