JP2009508351A - Ferroelectric memory device and manufacturing method thereof - Google Patents

Abstract

A ferroelectric memory device that is easy to manufacture, operates under a low voltage and has excellent data retention time, and a method for manufacturing the same are provided. In the present invention, a ferroelectric layer (60) is formed on a portion of the silicon substrate 1 corresponding to the channel region (4). The ferroelectric layer (60) is made of an organic material such as PVDF. This organic ferroelectric layer (60) exhibits a polarization characteristic under a low voltage of 1 V or less, and this polarization characteristic does not vary with time and is maintained for a certain time or more. Therefore, a ferroelectric memory device that can operate under a low voltage and can be manufactured with a simple structure and manufacturing method is realized.
[Selection] Figure 6

Description

  The present invention relates to a nonvolatile memory device using a ferroelectric, and particularly relates to a ferroelectric memory device that is easy to manufacture, operates under a low voltage, and has an excellent data retention period, and a method for manufacturing the same.

  Currently, researches are being actively conducted to realize a transistor or a memory device using a ferroelectric substance. FIG. 1 is a cross-sectional view showing a typical structure of an MFS (Metal-Ferroelectric-Semiconductor) type memory device using a ferroelectric.

In FIG. 1, a source region 2 and a drain region 3 are formed in a predetermined region of a silicon substrate 1, and a ferroelectric film or a ferroelectric layer 5 is formed on a channel region 4 between the source region 2 and the drain region 3. Is formed. At this time, as the ferroelectric layer 5, for example, strong such as PZT (PbZr _x Ti _1-x O ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ), BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ), etc. An inorganic material having dielectric characteristics is used. A source electrode 6, a drain electrode 7, and a gate electrode 8 made of a metal material are formed on the source region 2, the drain region 3, and the ferroelectric layer 5, respectively.

  In the ferroelectric memory having the above-described structure, the ferroelectric layer 5 exhibits polarization characteristics due to the voltage applied through the gate electrode 8, and conduction between the source region 2 and the drain region 3 is caused by such polarization characteristics. A channel is formed, and a current flows between the source electrode 6 and the drain electrode 7. In particular, in the structure described above, the polarization characteristics of the ferroelectric layer 5 can be maintained even after the voltage applied through the gate electrode 8 is cut off. Therefore, the above-described structure is attracting attention as a structure that can form a non-volatile memory with only one transistor without providing another capacitor.

  However, the ferroelectric memory having the above-described structure has the following problems. That is, if the ferroelectric layer 5 is formed directly on the silicon substrate 1, a low-quality transition layer is formed at the boundary surface between the ferroelectric layer 5 and the silicon substrate 1 when the ferroelectric layer 5 is formed. When elements such as Pb and Bi in the dielectric layer 5 diffuse into the silicon substrate 1, it is difficult to form a high-quality ferroelectric layer. Therefore, there arises a problem that the polarization characteristic of the ferroelectric layer 5, in other words, the data retention time of the ferroelectric memory is extremely shortened.

  Therefore, considering the above-described problems, a buffer layer 20 mainly made of an oxide is formed between the silicon substrate 1 and the ferroelectric layer 5 as shown in FIG. A Metal-Ferroelectric-Insulator-Semiconductor structure has been proposed.

  However, the above-described MFIS type ferroelectric memory first requires an additional manufacturing process for generating the buffer layer 20, and its data retention effect is not so great. Even in the case of the result, the actual situation is that the data retention time does not exceed 30 days.

  The present invention has been made in view of the above-described circumstances, and its object is to provide a ferroelectric memory device that has a simple structure and manufacturing process and can dramatically increase data retention time. is there.

  Another object of the present invention is to provide a ferroelectric memory device that can operate under a low voltage of 1V or less.

  Still another object of the present invention is to provide a method of manufacturing a ferroelectric memory device having the above-described characteristics.

  In order to achieve the above object, a ferroelectric memory device according to a first aspect of the present invention is formed between a source region and a drain region formed in a predetermined region of a semiconductor substrate and between the source region and the drain region. Channel region, an organic ferroelectric layer formed in a portion corresponding to the channel region on the semiconductor substrate, and a source electrode and a drain electrode formed on the source region, the drain region, and the organic ferroelectric layer, respectively. And the organic ferroelectric layer is bonded to the semiconductor substrate through one of van der Waals bonds and hydrogen bonds.

The organic ferroelectric layer is a PVDF layer.
The organic ferroelectric layer is made of polyvinylidene fluoride (PVDF), a polymer containing PVDF, a PVDF copolymer, or a PVDF terpolymer, an odd-numbered nylon, a cyano-polymer, a polymer thereof, And at least one of these copolymers.
The organic ferroelectric layer has a β phase crystal.
The ferroelectric layer has a thickness of 1 μm or less.

  A manufacturing method of a ferroelectric memory device according to a second aspect of the present invention includes a first step of forming a source region and a drain region in a predetermined region of a semiconductor substrate, and a channel region between the source region and the drain region. A second step of forming, a third step of forming an organic ferroelectric layer having a thickness of 1 μm or less in the channel region portion on the semiconductor substrate, and the source and drain regions and the organic ferroelectric And a fourth step of forming an electrode on the layer.

The third step includes a surface treatment step of treating the semiconductor substrate with a predetermined surface treatment solution and a ferroelectric layer formation step of applying an organic ferroelectric layer on the semiconductor substrate.
The surface treatment solution generates H groups on the surface of a semiconductor substrate.
The surface treatment solution may be silane, aki-silane, aryl-silane, fluorinated alkyl-silane, perfluorinated triethoxysilane. silane), and at least one solution of heptadecafluorodecyl triethoxysilane (heptadeca-fluordecyl trisilane).
The surface treatment solution generates OH groups on the surface of a semiconductor substrate.
The surface treatment solution is a solution in which KOH is saturated in a 2-propanol solution.
The surface treatment solution is a solution obtained by mixing H ₂ SO ₄ and H ₂ O ₂ .
The ferroelectric layer includes a ferroelectric layer phase transition step for setting the crystal structure of the ferroelectric layer to a β phase.
The ferroelectric layer phase transition step includes a temperature increase step for increasing the temperature of the ferroelectric layer to a temperature higher than that for forming a β-phase crystal, and a monotonically decreasing temperature for the ferroelectric material between the β-phase crystal temperatures. It is characterized by comprising a first temperature drop step and a second temperature drop step to rapidly drop the temperature of the ferroelectric layer.
The phase transition stage of the ferroelectric layer includes a temperature increasing stage for increasing the temperature of the ferroelectric layer to a temperature forming a β-phase crystal, and a temperature decreasing stage for rapidly decreasing the temperature of the ferroelectric layer, It is characterized by comprising.

  As described above, according to the present invention, a nonvolatile memory is implemented with one simple transistor structure. Therefore, there is an advantage that the manufacturing cost of the nonvolatile memory can be reduced and the manufacturing process can be greatly simplified.

  In addition, according to the present invention, since the polarization characteristic of the organic ferroelectric layer is determined to be 1 V or less, a nonvolatile memory that operates under an extremely low voltage can be realized.

  In addition, according to the present invention, a ferroelectric transistor that operates under an extremely low voltage can be implemented through the same method and structure.

  Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

First, the basic concept of the present invention will be described.
As described above, the ferroelectric substance currently used in the ferroelectric memory is an inorganic substance such as PZT, SBT, or BLT. However, such an inorganic substance tends to cause deterioration of polarity (polarization) characteristics with the passage of time, and basically has a problem in setting a long data retention time. Further, such inorganic ferroelectrics are expensive, and there are problems such as high temperature treatment required for thin film formation and expensive equipment required for film formation.

  In addition to the inorganic materials described above, various types of organic materials having ferroelectric properties are known. Typical examples include polyvinylidene fluoride (PVDF), polymers containing this PVDF, PVDF copolymers, or PVDF terpolymers, and other odd-numbered nylons and cyano polymers (cyano-polymers). , Polyacrylonitrile), these polymers, and copolymers thereof. Among the ferroelectric organic materials described above, PVDF and its polymers, copolymers, and ternary copolymers have been extensively studied as materials for organic semiconductors.

  In general, in order to use a ferroelectric organic material as a material of a memory device, the organic material should have a hysteresis characteristic with respect to voltage. However, in the case of the PVDF described above, the capacitance monotonously increases or decreases depending on the applied voltage as shown in FIG. 3, and does not have a hysteresis characteristic suitable for use in a memory device.

  According to the inventor's research, PVDF has four types of crystal structures of α, β, γ, and δ. Of these, β phase crystal structure has good hysteresis polarity characteristics. confirmed. At this time, in order to determine the phase crystal of PVDF as the β phase, the phase transition of PVDF into the β phase occurs, for example, at a temperature of 60 to 70 ° C., preferably approximately 65 ° C., or a temperature at which PVDF exhibits the β phase. PVDF can be determined to be β phase by a method of rapidly cooling PVDF.

  FIG. 4 is a graph showing the polarization characteristics of the PVDF thin film produced according to the present invention with respect to voltage, after forming a PVDF thin film having a β phase on a silicon substrate and forming an upper electrode on the PVDF thin film. This is a result of measurement by applying a predetermined voltage between the silicon substrate and the upper electrode. In particular, FIG. 4A shows a case where the thickness of the PVDF thin film is approximately 10 nm, and FIG. 4B shows a case where the thickness of the PVDF thin film is approximately 60 nm. These thin films are, for example, 3,000 rpm or less. After a PVDF thin film having a predetermined thickness is formed through a spin coating method and an annealing process at 120 ° C. or higher, the temperature of the PVDF thin film is monotonously reduced on a hot plate, and then the PVDF thin film is formed at a temperature of 65 ° C., for example. Was formed through a rapid cooling method.

  As can be seen from FIG. 4, the PVDF thin film produced according to the present invention has a capacitance value that decreases between approximately 0 and 1V when the applied voltage is increased, and approximately 0 to -1V when the applied voltage is decreased again. It has a good hysteresis characteristic that the capacitance value increases.

FIG. 5 is a graph obtained by measuring the degree to which the capacitance value of the PVDF thin film produced as described above changes over time. FIGS. 5 (a) and 5 (b) are FIGS. 4 (a) and 4 (b), respectively. This corresponds to 4 (b).
As can be seen from FIG. 5, it was confirmed that the PVDF thin film produced according to the present invention did not change its capacity value over time and was kept constant for a certain time or more.

  Therefore, as confirmed from FIGS. 4 and 5, the PVDF thin film according to the present invention has the following characteristics.

  First, the PVDF thin film according to the present invention exhibits a capacitance value above a certain level at 0V. This means that the polarization value of the PVDF thin film is maintained unchanged even at 0 V where no voltage is applied from the outside. That is, the PVDF thin film according to the present invention can be usefully used as a material for a nonvolatile memory.

  Second, the PVDF thin film according to the present invention exhibits memory characteristics even within a range of 1 V or less. That is, data recording and deletion can be performed at an extremely low voltage. That is, the PVDF thin film according to the present invention can be usefully used to implement a memory device that operates at a low voltage.

  Third, the PVDF thin film according to the present invention has a characteristic that its capacitance value does not change with time and is kept constant. That is, the PVDF thin film according to the present invention has an excellent data retention characteristic that retains a data value once recorded for a predetermined time or more.

Next, a structure of a ferroelectric memory device according to the present invention and a method for manufacturing the same will be described with reference to FIGS.
FIG. 6 is a sectional view showing the structure of a ferroelectric memory device according to the present invention.

  In the memory device according to the present invention, a source region 2 and a drain region 3 are formed in a predetermined region of a silicon substrate 1 as in the conventional device shown in FIG. 1, and a channel between the source region 2 and the drain region 3 is formed. A ferroelectric thin film or a ferroelectric layer 60 is formed on the region 4. Here, as the ferroelectric layer 60, a ferroelectric organic material is used as described above. At this time, as the ferroelectric organic material, polyvinylidene fluoride (PVDF), a polymer containing PVDF, a PVDF copolymer, a PVDF terpolymer, and other odd-numbered nylons, cyano polymers, and polymers thereof are used. And copolymers can be used. A source electrode 6, a drain electrode 7, and a gate electrode 8 made of a metal material or a conductive organic material are formed on the source region 2, the drain region 3, and the ferroelectric layer 60, respectively.

  In the structure shown in FIG. 6, unlike the MFIS structure of FIG. 3, the buffer layer 20 is removed. Accordingly, since the ferroelectric layer 60 and the various electrodes 6, 7, and 8 need only be formed immediately on the silicon substrate 1, the structure of the ferroelectric memory device becomes extremely simple like the structure of a general transistor.

On the other hand, FIG. 7 is a flowchart showing a process for manufacturing the ferroelectric memory device shown in FIG.
In FIG. 7, first, a source region 2, a drain region 3, and a channel region 4 are formed in a predetermined region of the silicon substrate 1 through a normal method (step ST1).

  Next, the silicon substrate 1 is treated with a predetermined surface treatment solution (step ST2). Generally, when manufacturing a semiconductor device, a semiconductor substrate such as silicon or GaAs is used. These semiconductor substrates are usually used after cutting the semiconductor substrate with a predetermined thickness from an ingot and then mirror-treating the cut semiconductor substrate. However, the dangling bonds on the semiconductor substrate are cut and removed at the stage of mirror-finishing the semiconductor substrate in this way, so that the bonding force of the organic substance to the semiconductor substrate is significantly reduced. That is, there arises a problem that a material such as an organic substance is not adhered and laminated on the semiconductor substrate.

  When the bonding force of the organic substance to the semiconductor substrate becomes low, a thin film having a certain thickness or less cannot be formed on the semiconductor substrate. That is, the film thickness of the organic material layer is inevitably increased. A ferroelectric memory is a non-volatile memory implemented using the polarization characteristics of a ferroelectric layer. However, when the organic material layer stacked on the semiconductor substrate becomes thick as described above, a high voltage must be applied to the organic material layer in order to obtain the polarization characteristics of the organic material layer. That is, there is a problem that a high voltage is required for driving the memory device.

Therefore, in order to realize an organic ferroelectric memory that can operate under a low voltage below a certain level, it is always necessary to form a ferroelectric organic layer with a thin film having a thickness below a certain level, preferably 1 μm or less.
According to the inventor's research, it has been confirmed that van der Waals bonds and hydrogen bonds can be extremely useful means for bonding organic substances to semiconductor substrates. For the van der Waals bond or hydrogen bond described above, it is desirable to form H groups or OH groups on the surface of the semiconductor substrate.

The inventor conducted various experiments to generate H groups and OH groups on a semiconductor substrate. As a result, for the generation of H groups and OH groups, for example, silane, KOH, or H ₂ SO It was confirmed that a mixture of ₄ and H ₂ O ₂ could be used. More specifically, for the generation of H group, silane (siliane), acryl-silane (aki-silane, alkyl-silane, allyl-silane), allylsilane (aryl-silane), fluorinated alkylsilane (fluorineated alkyl-silane) , Perfluorinated triethoxysilane, heptadecafluorodecyl triethoxysilane, and the like can be used, and 2-OH can be generated for the production of OH groups. (2-propanol) solution and saturated with KOH _solution, be used a solution in which the H 2 SO ₄ and _H 2 _{O 2} were mixed at a predetermined ratio Kill. Of course, as such a surface treatment solution, in addition to the above solution, any solution capable of generating H groups and OH groups on the semiconductor substrate may be used.

  After the surface of the silicon substrate 1 is treated with the above-described surface treatment solution, the silicon substrate is dried using, for example, an air gun using nitrogen. Then, after applying an organic ferroelectric on the substrate 1 using, for example, a spin coating method, a vacuum deposition method, a screen printing method, a jet printing method, or an LB (Langmuir-Blodgett) method, for example, hydrofluoric acid (HF) Unnecessary portions except for the gate region are removed using an etching solution such as a diluted solution to form the ferroelectric layer 60 (ST3).

  In particular, after the ferroelectric layer 60 is formed, the substrate 1 is placed on a hot plate, and heat is applied so that the temperature of the substrate 1 rises above a predetermined temperature. At this time, the temperature of the hot plate is set to be equal to or higher than the temperature at which the crystal structure of the ferroelectric layer 60 forms the β phase.

  Next, the temperature of the substrate 1 is monotonously decreased by controlling the hot plate, and the temperature of the substrate 1, more precisely, the temperature of the ferroelectric layer 60 is, for example, 60 to 70 ° C., preferably 65 ° C. When the temperature at which β forms a β phase is reached, the crystal structure of the ferroelectric layer 60 is fixed to the β phase by rapidly cooling the temperature of the substrate 1.

  Thereafter, the drain electrode 6, the source electrode 7 and the gate electrode 8 are formed on the resultant structure to constitute a memory device (ST4).

  The embodiments according to the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical scope of the present invention.

  That is, for example, in the above embodiment, after the ferroelectric layer 60, that is, the PVDF layer is formed on the substrate 1, the crystal structure of the PVDF layer is formed by rapidly cooling the substrate 1 at a temperature at which the PVDF layer exhibits a β phase. The β phase was determined.

  However, when a memory device is manufactured by such a method, the ferroelectric layer 60 is generated by the heat applied to the substrate 1 when the ferroelectric layer 60 is formed and then the various electrodes 6, 7, 8 are formed thereon again. There is a risk of changing the crystal structure of.

  Therefore, after the ferroelectric layer 60 is formed, the crystal structure of the ferroelectric layer 60 is not set immediately, and after the source electrode 6, the drain electrode 7 and the gate electrode 8 are formed and all the memory manufacturing steps are completed. A method of setting the crystal structure of the ferroelectric layer 60 is desirable.

In the above-described embodiments, the use of silane, KOH, or a mixed solution of H ₂ SO ₄ and H ₂ O ₂ to form H groups and OH groups on the substrate 1 has been described. However, in the present invention, any surface treatment solution capable of forming van der Waals bonds or hydrogen bonds between the substrate and the organic substance can be used.

  Also, as a method for laminating the organic layer on the substrate 1, all currently available laminating methods can be used in addition to vapor deposition, sputtering, and spin coating.

  Further, the substrate 1 to which the present invention is applied is not limited to a silicon substrate, and any substrate used for manufacturing a GaAs substrate or other semiconductor devices may be used.

  The invention is not limited to the embodiments disclosed above, but rather covers arrangements equivalent to various modifications that fall within the spirit and scope of the claims.

It is sectional drawing which shows the structure of the conventional MFS type ferroelectric memory device. It is sectional drawing which showed the structure of the conventional MFIS type ferroelectric memory device. It is the characteristic graph which showed the applied voltage-capacitance characteristic of the general organic substance. (A), (b) is the characteristic graph which showed the applied voltage-capacitance characteristic at the time of changing the PVDF film thickness of the ferroelectric organic substance applied to this invention. (A), (b) is the characteristic graph which showed the elapsed time-capacitance characteristic at the time of changing the PVDF film thickness of the ferroelectric organic material applied to this invention. 1 is a cross-sectional view illustrating a structure of a ferroelectric memory device according to an embodiment of the present invention. 3 is a flowchart for explaining a method of manufacturing a ferroelectric memory according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Source region 3 Drain region 4 Channel region 5 Ferroelectric layer 6 Source electrode 7 Drain electrode 8 Gate electrode 20 Buffer layer 60 Ferroelectric thin film (ferroelectric layer) made of a ferroelectric organic material

Claims (15)

A source region and a drain region formed in a predetermined region of the semiconductor substrate;
A channel region formed between the source region and the drain region;
An organic ferroelectric layer formed in a portion corresponding to the channel region on the semiconductor substrate;
A source electrode, a drain electrode and a gate electrode respectively formed on the source region, the drain region and the organic ferroelectric layer;
The ferroelectric memory device according to claim 1, wherein the organic ferroelectric layer is bonded to the semiconductor substrate through one of van der Waals bonding and hydrogen bonding.   2. The ferroelectric memory device according to claim 1, wherein the organic ferroelectric layer is a PVDF layer.   The organic ferroelectric layer is made of polyvinylidene fluoride (PVDF), a polymer containing PVDF, a PVDF copolymer, a PVDF terpolymer, an odd nylon, a cyano polymer, a polymer thereof, and The ferroelectric memory device according to claim 1, comprising at least one of these copolymers.   4. The ferroelectric memory device according to claim 2, wherein the organic ferroelectric layer has a β phase crystal.   2. The ferroelectric memory device according to claim 1, wherein the ferroelectric layer has a thickness of 1 [mu] m or less. Forming a source region and a drain region in a predetermined region of the semiconductor substrate;
A second step of forming a channel region between the source region and the drain region;
A third step of forming an organic ferroelectric layer having a thickness of 1 μm or less on the channel region portion on the semiconductor substrate;
4. A method of manufacturing a ferroelectric memory device, comprising: a fourth step of forming electrodes on the source and drain regions and the organic ferroelectric layer. The third step includes a surface treatment step of treating the semiconductor substrate with a predetermined surface treatment solution;
7. The method of manufacturing a ferroelectric memory device according to claim 6, further comprising a ferroelectric layer forming step of applying an organic ferroelectric layer on the semiconductor substrate.   8. The method of manufacturing a ferroelectric memory device according to claim 7, wherein the surface treatment solution generates H groups on the surface of the semiconductor substrate.   The surface treatment solution includes silane, aki-silane, aryl-silane, fluorinated alkyl-silane, and perfluorinated triethoxysilane. 9. The method of manufacturing a ferroelectric memory according to claim 8, comprising at least one of a solution of (silane) and heptadecafluorodecyl triethoxysilane (heptadeca-fluordecyl trisilane).   8. The method of manufacturing a ferroelectric memory device according to claim 7, wherein the surface treatment solution generates OH groups on the surface of the semiconductor substrate.   11. The method of manufacturing a ferroelectric memory device according to claim 10, wherein the surface treatment solution is a solution obtained by saturating 2-propanol (2-propanol) with KOH. The method of manufacturing a ferroelectric memory device according to claim 10, wherein the surface treatment solution is a solution in which H ₂ SO ₄ and H ₂ O ₂ are mixed.   7. The method of manufacturing a ferroelectric memory device according to claim 6, further comprising a ferroelectric layer phase transition step of setting a crystal structure of the ferroelectric layer to a β phase. The ferroelectric layer phase transition stage includes a temperature rise stage for raising the temperature of the ferroelectric layer to a temperature higher than that of forming a β-phase crystal,
A first temperature drop step for monotonically decreasing the temperature of the ferroelectric layer to the β-phase crystal temperature;
14. The method of manufacturing a ferroelectric memory device using an organic material according to claim 13, further comprising a second temperature drop step of rapidly lowering the temperature of the ferroelectric layer. The phase transition stage of the ferroelectric layer is a temperature rise stage for raising the temperature of the ferroelectric layer to a temperature forming a β-phase crystal,
14. The method of manufacturing a ferroelectric memory device according to claim 13, further comprising a temperature lowering step of rapidly lowering the temperature of the ferroelectric layer.

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