JP2009505198A - 電子回路設計 - Google Patents

電子回路設計 Download PDF

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Publication number
JP2009505198A
JP2009505198A JP2008525640A JP2008525640A JP2009505198A JP 2009505198 A JP2009505198 A JP 2009505198A JP 2008525640 A JP2008525640 A JP 2008525640A JP 2008525640 A JP2008525640 A JP 2008525640A JP 2009505198 A JP2009505198 A JP 2009505198A
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Japan
Prior art keywords
optimization
circuit
scenario
scenarios
electronic circuit
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Ceased
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JP2008525640A
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English (en)
Japanese (ja)
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JP2009505198A5 (enExample
Inventor
トンプソン・エイドリアン・ドミニク
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University of Sussex
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University of Sussex
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Publication of JP2009505198A publication Critical patent/JP2009505198A/ja
Publication of JP2009505198A5 publication Critical patent/JP2009505198A5/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/12—Computing arrangements based on biological models using genetic models
    • G06N3/126—Evolutionary algorithms, e.g. genetic algorithms or genetic programming

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Biophysics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Biology (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Computer Hardware Design (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Genetics & Genomics (AREA)
  • Artificial Intelligence (AREA)
  • Geometry (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Physiology (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Mobile Radio Communication Systems (AREA)
JP2008525640A 2005-08-12 2006-08-11 電子回路設計 Ceased JP2009505198A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0516634.3A GB0516634D0 (en) 2005-08-12 2005-08-12 Electronic circuit design
PCT/GB2006/002994 WO2007020391A1 (en) 2005-08-12 2006-08-11 Electronic circuit design

Publications (2)

Publication Number Publication Date
JP2009505198A true JP2009505198A (ja) 2009-02-05
JP2009505198A5 JP2009505198A5 (enExample) 2009-09-24

Family

ID=35098253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008525640A Ceased JP2009505198A (ja) 2005-08-12 2006-08-11 電子回路設計

Country Status (6)

Country Link
US (1) US20100162185A1 (enExample)
EP (1) EP1920367A1 (enExample)
JP (1) JP2009505198A (enExample)
CN (1) CN101356531A (enExample)
GB (1) GB0516634D0 (enExample)
WO (1) WO2007020391A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8595674B2 (en) 2007-07-23 2013-11-26 Synopsys, Inc. Architectural physical synthesis
US8819608B2 (en) 2007-07-23 2014-08-26 Synopsys, Inc. Architectural physical synthesis
US8307315B2 (en) 2009-01-30 2012-11-06 Synopsys, Inc. Methods and apparatuses for circuit design and optimization
CN102024067B (zh) * 2009-09-09 2012-08-22 中国科学院微电子研究所 一种模拟电路工艺移植的方法
US10354032B2 (en) * 2016-10-17 2019-07-16 Synopsys, Inc. Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus
US20200410153A1 (en) * 2019-05-30 2020-12-31 Celera, Inc. Automated circuit generation
US11636245B2 (en) * 2021-08-11 2023-04-25 International Business Machines Corporation Methods and systems for leveraging computer-aided design variability in synthesis tuning

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940604A (en) * 1996-11-19 1999-08-17 Unisys Corporation Method and apparatus for monitoring the performance of a circuit optimization tool
US6145117A (en) * 1998-01-30 2000-11-07 Tera Systems Incorporated Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
US6678644B1 (en) * 1999-09-13 2004-01-13 Synopsys, Inc. Integrated circuit models having associated timing exception information therewith for use with electronic design automation
US6539536B1 (en) * 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
GB2365155A (en) * 2000-07-24 2002-02-13 Motorola Inc Generation of test scripts from a system specification model
JP4723740B2 (ja) * 2001-03-14 2011-07-13 富士通株式会社 密度一様化配置問題の最適解探索方法および密度一様化配置問題の最適解探索プログラム
US7530047B2 (en) * 2003-09-19 2009-05-05 Cadence Design Systems, Inc. Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass
US20050257178A1 (en) * 2004-05-14 2005-11-17 Daems Walter Pol M Method and apparatus for designing electronic circuits
US7350164B2 (en) * 2004-06-04 2008-03-25 Carnegie Mellon University Optimization and design method for configurable analog circuits and devices
US7721069B2 (en) * 2004-07-13 2010-05-18 3Plus1 Technology, Inc Low power, high performance, heterogeneous, scalable processor architecture
US7500216B1 (en) * 2007-02-07 2009-03-03 Altera Corporation Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines

Also Published As

Publication number Publication date
CN101356531A (zh) 2009-01-28
US20100162185A1 (en) 2010-06-24
EP1920367A1 (en) 2008-05-14
GB0516634D0 (en) 2005-09-21
WO2007020391A1 (en) 2007-02-22

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