JP2009505181A - 少なくとも２つの処理ユニットと、データおよび／または指令のための少なくとも１つの第１のメモリもしくはメモリ領域とを有する計算機システム内で指令および／またはデータを記憶するための方法および装置 - Google Patents

少なくとも２つの処理ユニットと、データおよび／または指令のための少なくとも１つの第１のメモリもしくはメモリ領域とを有する計算機システム内で指令および／またはデータを記憶するための方法および装置 Download PDF

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Publication number
JP2009505181A
JP2009505181A JP2008525519A JP2008525519A JP2009505181A JP 2009505181 A JP2009505181 A JP 2009505181A JP 2008525519 A JP2008525519 A JP 2008525519A JP 2008525519 A JP2008525519 A JP 2008525519A JP 2009505181 A JP2009505181 A JP 2009505181A
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Prior art keywords
memory
data
access
cache
signal
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Pending
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JP2008525519A
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English (en)
Japanese (ja)
Inventor
ヴァイバール、ラインハルト
ミュラー、ベルント
ベール、エバーハルト
コラーニ、ヨルク
グメーリヒ、ライナー
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Robert Bosch GmbH
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Robert Bosch GmbH
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Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of JP2009505181A publication Critical patent/JP2009505181A/ja
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0853—Cache with multiport tag or data arrays

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
JP2008525519A 2005-08-08 2006-07-26 少なくとも２つの処理ユニットと、データおよび／または指令のための少なくとも１つの第１のメモリもしくはメモリ領域とを有する計算機システム内で指令および／またはデータを記憶するための方法および装置 Pending JP2009505181A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005037215A DE102005037215A1 (de) 2005-08-08 2005-08-08 Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle
PCT/EP2006/064661 WO2007017376A1 (fr) 2005-08-08 2006-07-26 Procede et dispositif pour enregistrer des donnees et/ou des ordres dans un systeme informatique comprenant au moins deux unites de traitement et au moins une premiere memoire ou zone de memoire pour des donnees et/ou des ordres

Publications (1)

Publication Number Publication Date
JP2009505181A true JP2009505181A (ja) 2009-02-05

Family

ID=37192655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008525519A Pending JP2009505181A (ja) 2005-08-08 2006-07-26 少なくとも２つの処理ユニットと、データおよび／または指令のための少なくとも１つの第１のメモリもしくはメモリ領域とを有する計算機システム内で指令および／またはデータを記憶するための方法および装置

Country Status (5)

Country Link
EP (1) EP1915695A1 (fr)
JP (1) JP2009505181A (fr)
CN (1) CN101243415A (fr)
DE (1) DE102005037215A1 (fr)
WO (1) WO2007017376A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103345910B (zh) * 2013-06-09 2015-11-18 苏州国芯科技有限公司 单端口调色板sram控制器及其控制方法
US11269777B2 (en) * 2019-09-25 2022-03-08 Facebook Technologies, Llc. Systems and methods for efficient data buffering

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JPH0973436A (ja) * 1995-09-05 1997-03-18 Mitsubishi Electric Corp 多重化計算機における動作モード切替方式
US6101589A (en) * 1998-04-01 2000-08-08 International Business Machines Corporation High performance shared cache
WO2005003962A2 (fr) * 2003-06-24 2005-01-13 Robert Bosch Gmbh Procede de commutation entre au moins deux modes de fonctionnement d'une unite centrale et unite centrale correspondante

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10332700A1 (de) 2003-06-24 2005-01-13 Robert Bosch Gmbh Verfahren zur Umschaltung zwischen wenigstens zwei Betriebsmodi einer Prozessoreinheit sowie entsprechende Prozessoreinheit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JPH0973436A (ja) * 1995-09-05 1997-03-18 Mitsubishi Electric Corp 多重化計算機における動作モード切替方式
US6101589A (en) * 1998-04-01 2000-08-08 International Business Machines Corporation High performance shared cache
WO2005003962A2 (fr) * 2003-06-24 2005-01-13 Robert Bosch Gmbh Procede de commutation entre au moins deux modes de fonctionnement d'une unite centrale et unite centrale correspondante

Also Published As

Publication number Publication date
CN101243415A (zh) 2008-08-13
EP1915695A1 (fr) 2008-04-30
DE102005037215A1 (de) 2007-02-15
WO2007017376A1 (fr) 2007-02-15

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