JP2009303032A - Encryption operation unit, and method and program of encryption operation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve safety against a DFA attack while suppressing an increase in circuit scale and operation time resulting from error detection or error correction. <P>SOLUTION: An encryption operation unit defines a W-bit string starting from a "Wä(R+1)×c+r}+1" bit of a round key K<SB>n-1</SB>(E*)ä0, 1}<SP>L</SP>having a bit length of L=W×(C+1)×(R+1) of the (n-1)-th round to a Wä(R+1)×c+r+1} bit as BIS<SB>n-1, r, c</SB>, and executes round key generation processing such as an exclusive-OR operation by using each of bit strings BIS<SB>n-1, r, 0</SB>, BIS<SB>n-1, r, 1</SB>, ..., BIS<SB>n-1, r, c</SB>corresponding to each r as a processing unit. (E*) is a symbol representing "belong to". <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an arithmetic technique for performing a cryptographic operation using a round key, and more particularly to an arithmetic technique with a DFA attack countermeasure.

  A differential failure utilization analysis attack that causes a failure during cryptographic computation of a cryptographic computation device such as an IC card and illegally obtains a secret key using the difference between the correct computation result and the computation result when the failure occurs ( A DFA attack (Differential Fault Analysis) is known (for example, see Non-Patent Document 1). In particular, in recent years, a DFA attack on the extended key generation unit of the common key encryption method AES (Advanced Encryption Standard) has been proposed (for example, see Non-Patent Document 2).

  In the AES encryption process, 128-bit (16-byte) plaintext data is encrypted using a 128-bit secret key. The encryption process consists of multiple rounds. For each round, the extended key (round key) is updated based on the private key in the extended key generation unit, and the SubBytes (per byte) of the encryption target data in the cryptographic operation unit ) Processing, ShiftRows processing, MixColumns processing, and AddRoundKey processing (exclusive OR with a round key) are performed. The decryption process is a process for executing the encryption process in the reverse direction.

FIG. 1 is a diagram for explaining processing of a conventional extended key generation unit. FIG. 2 is a diagram for explaining the processing of the conventional extended key generation unit when a failure occurs in the ninth round. 1 and 2, BIS _{n-1, r, c} (n is an integer from 1 to 11 and c and r are integers from 0 to 3) is the round key K _n− of the (n−1) -th round. ₁ ∈ {0, 1} ¹²⁸ (round key K ₀ is a secret key) means 8 (4 · c + r) +1 bit to 8 (4 · c + r + 1) bit sequence of 8 bits (1 byte) . Rcon _n-1 is a 32-bit constant.

As shown in FIG. 1, the conventional extended key generation unit performs a total of 10 rounds by dividing a key having a key length of 128 bits into 4 blocks each having 32 bits in succession, and has 11 128-bit round keys. K ₀ ,..., K ₁₀ are generated. For example, in the processing of the _n-th round, the bit string BIS _n−1,0,3 ,..., BIS _n−1,3,3 which is the block of the fourth column of the round key K _n−1 is rotated in units of bytes (RotWord ), and it performs the exclusive OR of the substituted in bytes (SubWord) bit stream and the constant Rcon _n, bit strings BIS _n-1 is a result of the operation and the round key K _n-1 of the first column of the block _{, 0,0, ..., BIS n-} 1,3,0 bit sequence XOR is a block of the first column of the round key _{K n} with _{BIS n, 0,0, ..., BIS} n, 3,0 And The bit sequence BIS _{n−1,0, c + 1} ,..., BIS _{n−1,3, c + 1,} which is the block in the c + 1 column of the round key K _{n−1, and} the c column block of the round key K _n. bit string _{BIS n, 0, c, ...} , BIS n, 3, the exclusive OR is _c, the bit string is c + 1 column of the block of the round key _{K n BIS n, 0, c} + 1, ..., BIS n, 3 _{, C + 1} .

Here, as shown in FIG. 2, the fault that caused intentionally at some point attacker bit string _BIS 9,0,0 constituting the 0 row 32-bit block of 9 round, ..., BIS _{9 , 3} and ₀ have errors. This failure includes one that occurs in the middle of calculation and one that occurs in the storage unit in which the calculation result is stored. In the case of the conventional algorithm, this error propagates to all the bit strings from the first column to the third column of the round key of the ninth round, and also to all the bit strings from the 0th column to the third column in the tenth round. Propagate. As a result, all the bit strings of the round keys K ₉ and K _{10 in} the _ninth and _tenth rounds are affected by a failure that is intentionally generated by the attacker. As a result, the attacker intentionally generated all bit strings obtained as a result of AddRoundKey (exclusive OR with round keys) processing performed using round keys K ₉ and K ₁₀ in the _ninth and _tenth rounds. It is affected by the failure. The attacker can obtain the processing result of the 10th round of AddRoundKey as ciphertext. In the DFA attack, the ciphertext when the attacker causes a failure and the ciphertext when the failure does not occur are obtained, and the difference between them is used to obtain information on the common key corresponding to the byte position where the difference has occurred. get. In the conventional configuration, since the influence of a fault intentionally generated at a certain point in time reaches the calculation result of all bit strings calculated thereafter, the DFA attack gives a lot of information to the attacker.

As a conventional means to counter such attacks, a processing unit that generates an error detection code is provided in addition to the cryptographic operation unit, and the presence or absence of an error during the cryptographic operation is determined using the cryptographic operation result and the error detection code. Or error correction (for example, see Non-Patent Documents 3 and 4).
E. Biham and A. Shamir, "Differential Fault Analysis of Secret Key Cryptosystems," Advances in Cryptology, CRYPTO'97, LNCS 1294, Springer-Verlag, pp. 513-525, 1997. J. Takahashi, T. Fukunaga and K. Yamakoshi, "DFA Mechanism on the AES Key Schedule", Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography-FDTC 2007. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Error analysis and detection procedures for a hardware implementation of the advanced encryption standard", IEEE Transactions on Computers, Vol. 52, No. 4, 2003. M. Karpovsky, KJ Kulikowski and A. Taubin, "Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard", International Conference on Dependable Systems and Networks-DSN'04.

  However, in the conventional countermeasure method against the DFA attack, it is necessary to perform error detection and error correction separately from the cryptographic calculation. Therefore, when the cryptographic calculation is implemented in hardware, the scale of the cryptographic circuit increases, and software When implemented, there is a problem that the cryptographic operation processing time increases. Such a problem is not limited to AES with a key length of 128 bits, but the round key is divided into a plurality of blocks each consisting of a continuous bit string, and the round key is updated by performing an exclusive OR operation on a block-by-block basis. It is a problem common to the method of performing.

  The present invention has been made in view of these points, and provides a technology capable of improving the safety against DFA attacks while suppressing an increase in circuit scale and calculation time associated with error detection and error correction. The purpose is to do.

In the present invention, in order to solve the above-described problem, a cryptographic operation apparatus that performs a cryptographic operation using a round key, wherein R, C, and W are integer constants of 1 or more, and n is an integer variable of 1 or more. And a storage unit for storing the round key K _n-1 ε {0, 1} ^L of L = W · (C + 1) · (R + 1) bits in the ( _n-1 ) _th round, and an integer of 0 to R a selection unit that selects r, and c is an integer variable between 0 and C, and the upper W {(R + 1) · c + r} +1 bit to W {(R + 1) · c + r + 1} bit of the round key K _n−1 a bit string of W bits consisting of up to a _{BIS n-1, r, c} , BIS n-1, r (0) = BIS n-1, r, 0 | BIS n-1, r, 1 | ... | BIS n _{-1, r,} in the case where it is _C, and the i is 0 or C-1 following each integer, And Tsu preparative column _{BIS n-1, r (i} ) bit string _{BIS n-1} was W-bit shift to the lower and right-shift unit for generating r (i + 1), each corresponding to each of 0 or more C or less j A first exclusive OR operation unit for obtaining a bit string XORBIS _{n−1, r} (C) which is an exclusive OR of the bit string BIS _{n−1, r} (j), and k is an integer constant between −R and R And the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the storage unit is defined as CBIS _{n−1, r, C,} and the bit string BIS _{n−1, (r + k) mod (R + 1), C} , XORBIS _{n−1, r (C) = XORBIS n-} 1, r, 0 | XORBIS n-1, r, 1 | ... | XORBIS n-1, r, XORBIS each bit string of W bits which satisfies the _{C n-1, r,} in case of the _c, CBIS _{n- , R, C} and _{XORBIS n-1, r,} the exclusive OR of the _c was calculated for each c, the round key for each operation result n round corresponding to c _{K n} ∈ ^{{0,1} L} A second exclusive OR operation unit that outputs as a bit string BIS _{n, r, c} from the upper W {(R + 1) · c + r} +1 bit to the W {(R + 1) · c + r + 1} bit, and 0 to R Until each bit string BIS _{n, r, c} of the round key K _n is obtained for all integers r of the selection unit, the right shift unit, the first exclusive OR operation unit, and the second exclusive OR operation unit. A cryptographic operation device is provided that includes a control unit that repeatedly executes each process.

  Here, each process of the right shift unit, the first exclusive OR operation unit, and the second exclusive OR operation unit is not executed in block units in the column direction (vertical direction) composed of continuous bit strings. , Block unit in the row direction (horizontal direction) composed of the bit string (c = 0,..., C) from the upper W {(R + 1) · c + r} +1 bit to the W {(R + 1) · c + r + 1} bit of the round key Is executed. For this reason, even if an attacker intentionally causes a failure at a certain point in time, the influence only affects the same row as the bit string that caused the failure. Therefore, the information that can be obtained by the attacker by the DFA attack is limited to the portion corresponding to the same row as the bit string that caused the failure. As a result, security against DFA attacks is improved.

  In the present invention, the selection unit preferably selects a random integer r of 0 or more and R or less. Here, by setting the integer r to a random value, selection of the block unit in the row direction in which each process of the right shift unit, the first exclusive OR operation unit, and the second exclusive OR operation unit is executed can be performed. Random. As a result, it is difficult for an attacker to predict a round key generation procedure, and it is difficult to intentionally cause a failure in a desired calculation result during the round key generation procedure. As a result, security against DFA attacks is further improved.

When the integer r is a random value and the bit string BIS _{n, r, c} for the integer r selected by the selection unit has already been obtained, the right shift unit corresponding to the integer r, The selection unit may be configured to select a new random integer r without repeatedly executing the processes of the 1 exclusive OR operation unit and the second exclusive OR operation unit. Accordingly, it is possible to prevent the calculation corresponding to the same row from being performed repeatedly in the round key generation process, thereby improving the calculation efficiency.

Further, when the integer r is a random value, the right shift unit corresponding to the integer r regardless of whether the bit string BIS _{n, r, c} for the integer r selected by the selection unit has already been obtained. The first exclusive OR operation unit and the second exclusive OR operation unit may be configured to execute each process. In this case, since the presence or absence of the repetitive processing does not change according to the value of the integer r, it is possible to prevent information such as the calculation order from leaking to the attacker due to a change in power consumption accompanying a change in calculation contents. As a result, safety is improved.

Further, in the present embodiment, there is further provided a replacement unit that generates the bit string CBIS _{n−1, r, C} from the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the storage unit according to a predetermined rule. The control unit repeatedly executes each process in the order of selection unit processing, replacement unit processing, right shift unit processing, first exclusive OR operation unit processing, and second exclusive OR operation unit processing. The bit string BIS _{n, r, c} output from the second exclusive OR operation unit may be overwritten on the area where the bit string BIS _{n-1, r, c} of the storage unit is stored. In this case, k is set to 1 or −1, and each time the selection unit, replacement unit, right shift unit, first exclusive OR operation unit, and second exclusive OR operation unit are repeated, the selection unit Preferably, (r + k) mod (R + 1) is selected as a new integer r. In such a case, the replacement unit bit string _{BIS n-1, (r +} k) mod (R + 1), bit string from _{C CBIS n-1, r,} the time to generate the _C, the bit string _{BIS n-1, (r +} k) _The situation _{where mod (R + 1), C} is overwritten by the bit string BIS _{n, (r + k) mod (R + 1), C} can be made only once. Therefore, the number of bit strings BIS _{n−1, (r + k) mod (R + 1), C} to be copied to another area for processing in the replacement unit can be reduced to one, which is necessary for the calculation. Storage area can be reduced.

  In the present invention, it is possible to improve the safety against a DFA attack while suppressing an increase in circuit scale and calculation time accompanying error detection and error correction.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Definition of symbols)
First, symbols used in the embodiment of the present invention are defined.
α | β: Bit combination of α and β.
α (+) β: Exclusive OR of α and β.
R: An integer constant of 1 or more set in advance. The maximum line number of the round key. In the AES example, R = 3.
C: A preset integer constant of 1 or more. Maximum value of the round key column number. In the AES example, C = 3.
W: An integer constant of 1 or more set in advance. Bit length that is the unit of arithmetic processing. In the AES example, W = 8.
N: A preset number of rounds. In the example of AES, N = 10.
r: An integer from 0 to R.
c: An integer variable of 0 to C.
n: An integer variable of 1 to N.
k: an integer constant set in advance from −R to R. Supports rotation direction and rotation amount of RotWord. In the AES example, k = 1.

p: Each integer from 0 to R excluding r + k mod (R + 1).
K _n−1 ε {0,1} ^L : Round key for the (n−1) th round.
L: Bit length of the round key L = W · (C + 1) · (R + 1). In the example of AES, L = 128.
BIS _{n−1, r, c} : W bit string consisting of the upper W {(R + 1) · c + r} +1 bit to W {(R + 1) · c + r + 1} bit of the round key K _n−1 .
BIS _{n-1, r} (0): BIS _{n-1, r, 0} | BIS _{n-1, r, 1} | ... | A bit string composed of BIS _{n-1, r, C.}
BIS _{n-1, r} (i + 1): A bit string obtained by shifting the bit string BIS _{n-1, r} (i) by W bits downward.

i: Each integer from 0 to C-1.
XORBIS _{n-1, r} (i + 1): Exclusive OR value of XORBIS _{n-1, r} (i) and bit string BIS _{n-1, r} (i + 1). XORBIS _{n-1, r} (0) = BIS _{n-1, r} (0).
CBIS _{n−1, r, C} : Bit string BIS _{n−1, (r + k) mod (R + 1),} a W-bit bit string generated according to a predetermined rule. CBIS _{n-1, r, C} and BIS _{n-1, (r + k) mod (R + 1), C} have a one-to-one correspondence.
XORBIS _{n-1, r, c} : XORBIS _{n-1, r} (C) = XORBIS _{n-1, r, 0} | XORBIS _{n-1, r, 1} | ... | XORBIS _{n-1, r, C} Each bit string of W bits to fill.

[First Embodiment]
Next, a first embodiment of the present invention will be described. In the present embodiment, the cryptographic operation of this embodiment is implemented by causing the CPU to execute software in which the cryptographic operation is described.
<Configuration>
FIG. 3A is a block diagram for explaining a hardware configuration of the cryptographic operation apparatus 10 according to the first embodiment.

As shown in FIG. 3A, the cryptographic operation device 10 of this embodiment includes a central processing unit (CPU) 11, a random-access memory (RAM) 12, a read-only memory (ROM) 13, an EEPROM 14, A random number generator 15, an input interface (IF) 16, an output interface (IF) 17, and a data bus 18. Here, the random number generator 15 may be an integrated circuit that generates a true random number, or may be constructed by executing, in hardware, software in which a pseudo-random number generation algorithm is described. The EEPROM 14 stores a predetermined program and a round key K ₀ ε {0, 1} ^{L for the} _0th round. Each of these programs and the round key K ₀ is written in the RAM 12, and the CPU 11 executes the program written in the RAM 12 and performs a cryptographic calculation process using the round key K ₀ , whereby the cryptographic calculation device 10 of the present embodiment. Is built.

FIG. 3B shows the functional configuration of the cryptographic operation device 10 constructed by the CPU 11 of FIG. 3A executing the program written in the RAM 12 and performing cryptographic operation processing using the round key K _0. It is a block diagram for demonstrating.

  As shown in FIG. 3B, the functional configuration of the cryptographic operation device 10 according to the present embodiment includes a storage unit 10a, a temporary storage unit 10b, a control unit 10c, an input unit 10d, an output unit 10e, and a selection unit. 10f, right shift unit 10g, exclusive OR operation unit 10h (first exclusive OR operation unit), replacement unit 10i, exclusive OR operation unit 10j (second exclusive OR operation unit) And a cryptographic operation unit 10k. The storage unit 10a is a storage area configured by, for example, the RAM 12, the EEPROM 14, or a register, and the temporary storage unit 10b is a storage area configured by, for example, a register or a cache memory. Further, the control unit 10c, the right shift unit 10g, the exclusive OR operation unit 10h, the replacement unit 10i, the exclusive OR operation unit 10j, and the cryptographic operation unit 10k are configured by, for example, a predetermined program being read by the CPU 11 Processing means. The selection unit 10f is a processing unit configured by, for example, the random number generator 15 or the CPU 11 into which a predetermined program is read. The input unit 10d and the output unit 10e are configured by an input IF 16 and an output IF 17. Further, the cryptographic operation apparatus 10 according to the present embodiment executes each process under the control of the control unit 10c. Each data necessary for each calculation is read from the storage unit 10a and then stored in the temporary storage unit 10b. The calculation result is stored in the temporary storage unit 10b and then stored in the storage unit 10a. . However, the description thereof is omitted below.

<Processing>
Next, the processing of this embodiment will be described. In the following, after generalizing the processing of this embodiment, the processing when this embodiment is applied to AES will be specifically exemplified. In the following, a case will be described in which the cryptographic operation device 10 is an encryption device and the cryptographic operation unit 10k performs encryption using a round key. However, the round key generation process is the same when encryption is performed and when decryption is performed. In the following explanation, the cryptographic operation device 10 is the decryption device, and the cryptographic operation unit 10k performs decryption using the round key. It is easy to extend when doing.

[Generalized processing contents]
4 and 5 are flowcharts for explaining round key generation processing in the n-th round according to the first embodiment. Hereinafter, generalized processing of this embodiment will be described with reference to these drawings.

First, L = W · (C + 1) · (R + 1) bits of plaintext M input to the input unit 10d is stored in the area 10aa of the storage unit 10a. In addition, the round key K _n−1 ∈ {0, 1} ^L having the length L = W · (C + 1) · (R + 1) bits in the ( _n−1 ) _th round is stored in the area 10aa of the storage unit 10a (step S1). . That is, the W bit bit sequence BIS _{n−1, r, c} consisting of the upper W {(R + 1) · c + r} +1 bit to the W {(R + 1) · c + r + 1} bit of the round key K _n−1 is 0. All integers r above R and below and all integers c above 0 and below C are stored in the area 10aa. Further, the control unit 10c duplicates this round key K _n-1 and stores it in the area 10ab of the storage unit 10a (step S2). Next, the selection unit 10f selects a random integer r of 0 or more and R or less (Step S3). This selection may be selected based on a random number or pseudo-random number generated each time, or may be selected from a random number table generated or set in advance. The selected integer r is stored in the temporary storage unit 10b and thereafter read out to each processing unit as necessary. Next, the control unit 10c reads each bit string BIS _{n−1, p, C} corresponding to each integer p not less than 0 and not more than R except r + k mod (R + 1) from the area 10aa, and duplicates them to read R · W Store in the bit area 10ac (step S4).

Next, the replacement unit 10i converts the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the area 10aa or the area 10ac into a W-bit bit string CBIS _{n−1, r, C} according to a predetermined rule. The region 10aa or the region 10ac is updated with the generated bit string CBIS _{n-1, r, C} (step S5). The predetermined rule refers to a rule for replacing the bit string BIS _{n−1, (r + k) mod (R + 1), C} with the bit string CBIS _{n−1, r, C} corresponding to the one-to-one correspondence therewith. That is, the bit string CBIS _{n−1, r, C} is uniquely determined with respect to the bit string BIS _{n−1, (r + k) mod (R + 1), C.} An example of a specific process of the replacement unit 10i is a process of replacing the bit string BIS _{n−1, (r + k) mod (R + 1), C} with the bit string CBIS _{n−1, r, C} according to a preset replacement table. Alternatively, the bit string BIS _{n−1, (r + k) mod (R + 1), C} is replaced with the bit string CBIS _{n−1, r, C} according to a preset arithmetic expression. When the process of step S5 is performed for the first time in the n-th round, since the bit string BIS _{n−1, (r + k) mod (R + 1), C} is always stored in the area 10aa, the replacement unit 10i is stored in the area 10aa. The processing of this step is performed using the stored bit string BIS _{n−1, (r + k) mod (R + 1), C.} On the other hand, when the process of step S5 is performed after the second round in the n-th round, the bit string BIS _{n−1, (r + k) mod (R + 1), C} is not always stored in the area 10aa. The unit 10i performs the process of this step using the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the area 10ac. However, if it is determined that the bit string BIS _{n−1, (r + k) mod (R + 1), C} is stored in the area 10aa when the process of step S5 is performed after the second round in the n-th round, the replacement is performed. It is also possible to perform processing of this step using the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the area 10aa by the unit 10i. Moreover, since it is also assumed that an attacker causes a failure in the process in step S5, it is preferable to add a verification process for confirming that the correct process has been performed in step S5. In the example of the verification process, the replacement unit 10i performs an inverse operation (inverse conversion) of the bit string CBIS _{n-1, r, C} , and the result is the bit string BIS _{n-1, (r + k) mod (R + 1), C.} And the replacement unit 10i repeats the process of converting the bit string BIS _{n-1, (r + k) mod (R + 1), C} into the bit string CBIS _{n-1, r, C a} plurality of times, and the same result For example, processing for confirming that

Next, the control unit 10c sets the variable i to 0 and stores it in the temporary storage unit 10b (step S6). Thereafter, the right shift unit 10g generates a bit string BIS _{n-1, r} (i + 1) obtained by shifting the bit string BIS _{n-1, r} (i) stored in the region 10aa to the lower (right) W bits. BIS _{n-1, r} (0) = BIS _{n-1, r, 0} | BIS _{n-1, r, 1} | ... | BIS _{n-1, r, C.} Further, shifting the bit string BIS _{n-1, r} (i) to the lower order by W bits means that the lower W bits of the bit string BIS _{n-1, r} (i) are deleted and the remaining bits are shifted to the lower order by W bits. , Which means a process of generating a bit string with W bits 0 added to the upper part (a specific example will be described later). When the CPU 11 has such an arithmetic function, this processing may be performed by the arithmetic instruction, or a bit other than the lower W bits of the bit string BIS _{n−1, r} (i) is copied. This process may be performed by adding a W bit 0 to the top of the replicated bit string. Such bit stream is generated _{BIS n-1, r (i} + 1) is overwritten in a position where the bit string region _{10aa BIS n-1, r (} i) is stored, the area 10aa is updated (step S7 ).

Next, the exclusive OR operation unit 10h exclusives the bit string XORBIS _{n−1, r} (i) stored in the area 10ab and the bit string BIS _{n−1, r} (i + 1) stored in the area 10aa. OR value XORBIS _{n-1, r} (i + 1) = XORBIS _{n-1, r} (i) (+) BIS _{n-1, r} (i + 1) is calculated. XORBIS _{n-1, r} (0) = BIS _{n-1, r} (0). Calculated bit string _{XORBIS n-1, r (i} + 1) is overwritten in a position where the bit string regions _{10ab XORBIS n-1, r (} i) is stored, the area 10ab is updated (step S8).

  Next, the control unit 10c refers to the value of the variable i stored in the temporary storage unit 10b, and determines whether i = C-1 (step S9). When it is determined that i = C−1 is not satisfied, the control unit 10c updates the variable i with i + 1 as the value of the new variable i, stores the variable i in the temporary storage unit 10b, and performs processing. It returns to step S7 (step S10).

On the other hand, if it is determined in step S9 that i = C−1, the exclusive OR operation unit 10j includes the bit string CBIS _{n−1, r, C} stored in the region 10aa or the region 10ac, and the region 10b is read from the bit string XORBIS _{n-1, r, c} stored in 10ab, and their exclusive OR is calculated for each c = 0, 1,..., C, and each operation result corresponding to each c is calculated. The bit string BIS _{n, r, c} = from the upper W {(R + 1) · c + r} +1 bit to the W {(R + 1) · c + r + 1} bit of the _n-th round key K _n ε {0,1} ^L CBIS _{n-1, r, C} (+) XORBIS _{n-1, r, c} is used _, and the area 10ab is updated with the bit string BIS _{n, r, c} (step S11). The bit strings XORBIS _{n-1, r, c} are respectively XORBIS _{n-1, r} (C) = XORBIS _{n-1, r, 0} | XORBIS _{n-1, r, 1} |. . . | XORBIS is a bit string of W bits satisfying _{n-1, r, C.}

Next, the control unit 10c determines whether or not the bit strings BIS _{n, r, c} respectively corresponding to all integers r greater than or equal to 0 and less than or equal to R have been generated (step S12). Here, when it is determined that the bit strings BIS _{n, r, c} corresponding to all integers r between 0 and R have been generated, the round key generation process for the n-th round is completed.

On the other hand, when it is determined that the bit string BIS _{n, r, c} corresponding to any integer r between 0 and R has not been generated, the selection unit 10f selects a new one between 0 and R as in step S3. Select the integer r. The selected integer r is stored in the temporary storage unit 10b, whereby the integer r stored in the temporary storage unit 10b is updated, and thereafter read out to each processing unit as necessary. Next, the control unit 10c determines whether or not the bit string BIS _{n, r, c} corresponding to the integer r selected in step S13 has been generated (step S14). If it is determined that the bit string BIS _{n, r, c} corresponding to the integer r selected in step S13 has been generated, the process returns to step S13. On the other hand, when it is determined that the bit string BIS _{n, r, c} corresponding to the integer r selected in step S13 has not been generated, the control unit 10c duplicates the bit string of the area 10ab and stores it in the area 10aa. (Step S15), the process returns to Step S5.

The round keys K _0, K ₁ ,..., K _N and plaintext M of each round generated as described above are read into the cryptographic operation unit 10k, and the cryptographic operation unit 10k follows a predetermined encryption procedure such as AES. ., K _N is encrypted using the round keys K _0, K ₁ ,..., K _N and the cipher text enc (M) is stored in the area 10ad. The cryptographic computation processing of the cryptographic computation unit 10k may be executed collectively after all the round keys K _0, K ₁ ,..., K _N are generated, or the first round when the round key K ₁ is generated perform cryptographic operations, so that perform second round of cryptographic operation After generating round keys K _2, the encryption processing rounds may be performed after each round key is generated. The ciphertext enc (M) stored in the area 10ad is sent to the output unit 10e and output therefrom.

[Processing contents when this form is applied to AES]
Next, processing when the first embodiment is applied to AES will be described. In this case, R and C are 3, W is 8, L is 128, k is 1, and CBIS _{n-1, r, C} is a bit string BIS _{n-1, (r + 1) mod 4, This} is an 8-bit bit string in which ₃ is replaced according to a predetermined replacement rule.

  FIG. 6 is a diagram illustrating the entire processing at r = 2 when the first embodiment is applied to AES. 7 to 11 are diagrams exemplifying bit strings stored in the areas 10aa to 10ac of the storage unit 10a when the first embodiment is applied to AES. FIG. 12A is a diagram for explaining an example of the integer r selected by the selection unit 10f when the first embodiment is applied to AES. FIG. 12B to FIG. ) Is a diagram showing a processing target corresponding to each selected integer r. In the following, an n-th round key generation process when the present embodiment is applied to AES will be described with reference to these drawings.

In this example of round key generation processing, first, the 128-bit round key K _n-1 ε {0, 1} ^{128 of the} ( _{n-1) th} round is stored in the area 10aa of the storage unit 10a (step S1). . That is, the 8-bit bit string BIS _{n−1, r, c} consisting of the upper 8 (4 · c + r) +1 bit to 8 (4 · c + r + 1) bit of the round key K _n−1 is 0 or more and 3 or less. All integers r and all integers c not smaller than 0 and not larger than 3 are stored in the area 10aa (FIG. 6, FIG. 7A). Further, the control unit 10c duplicates this round key K _n−1 and stores it in the area 10ab of the storage unit 10a (step S2, FIG. 7A). Next, the selection unit 10f selects a random integer r of 0 or more and 3 or less (Step S3). In this example, it is assumed that r = 2 is selected (FIG. 12A). Next, the control unit 10c reads each bit string BIS _{n−1, p, 3} corresponding to each integer p = 0, 1, 2 except for 2 + 1 mod (3 + 1) = 3 from the area 10aa, These are duplicated and stored in the 24-bit area 10ac (step S4, FIG. 7A).

Next, the replacement unit 10i uses the bit string BIS _{n−1, (2 + 1) mod (3 + 1), 3} = BIS _{n− 1, 3, 3} stored in the area 10aa from the 8-bit bit string CBIS _n according to a predetermined replacement rule. generates _-1,2,3 by (SubWord processing), the bit string _{CBIS n-1, 2, 3} which generated, updates the area lOaa (step S5, Fig. 6, FIG. 7 (b)).

Next, the control unit 10c sets the variable i to 0 and stores it in the temporary storage unit 10b (step S6). Thereafter, the right shift unit 10g _receives the bit string BIS _n−1,2 (0) = BIS _n−1,2,0 | BIS _n−1,2,1 |... | BIS _n−1 stored in the area _{10aa . 2 and 3} (FIG. 12B) are generated by shifting the lower 8 bits to the bit string BIS _n−1,2 (1) (FIG. 6). The bit string BIS _{n-1, r} (1) generated in this way is overwritten at the position where the bit string BIS _{n-1, r} (0) of the area 10aa was stored, and the area 10aa is updated (step S7). FIG. 7 (b)).

Next, the exclusive OR operation unit 10h generates the bit string XORBIS _n−1,2 (0) = BIS _n−1,2 (0) stored in the area 10ab and the bit string BIS _n− stored in the area 10aa. _1,2 (1) exclusive OR value _{XORBIS n-1,2} (1) and = BIS n-1,2 (0) (+) calculating the _{BIS n-1,2} (1) (FIG. 6 ). The calculated bit string XORBIS _n−1,2 (1) is overwritten in the area 10ab where the bit string XORBIS _n−1,2 (0) = BIS _n−1,2 (0) was stored. Is updated (step S8, FIG. 7B).

Next, the control unit 10c refers to the value of the variable i stored in the temporary storage unit 10b, and determines whether i = 2 (step S9). Here, since i = 2, the variable i is updated with 1 as the value of the new variable i, the variable i is stored in the temporary storage unit 10b, and the process returns to step S7 (step S10). Thereafter, after the processes in steps S7 and S8 are repeated for i = 1 and 2 (FIGS. 6, 8, and 9), it is determined in step S9 that i = 2. Thereby, the exclusive OR operation unit 10j reads the bit string CBIS _n-1,2,3 stored in the area 10aa and the 8-bit bit string XORBIS _{n-1,2, c} stored in the area 10ab. , Their exclusive OR is calculated for each c = 0, 1, 2, 3, and each operation result corresponding to each c is calculated as the upper 8 of the _n-th round key K _n ε {0, 1} ¹²⁸ ( 4 · c + 2) +1 from bit 8 (4 · c + 2 + 1) bit string to bit _{BIS n, 2, c = CBIS} n-1,2,3 (+) XORBIS n-1,2, and is _c, the bit string BIS _{n , 2 and c} , the area 10ab is updated (step S11, FIG. 6 and FIG. 10).

Next, since the bit strings BIS _{n, r, c} respectively corresponding to all the integers r greater than or equal to 0 and less than or equal to 3 have not been generated (step S12), the selection unit 10f selects a new value greater than or equal to 0 and less than or equal to 3 as in step S3 Select the integer r. Here, it is assumed that r = 0 is selected (FIG. 12A). Here, since the bit string BIS _{n, 0, c} corresponding to the integer r = 0 selected in step S13 has not been generated (step S14), the control unit 10c duplicates the bit string of the area 10ab to the area 10aa. Store (step S15, FIG. 11), and the process returns to step S5.

Thereafter, the process from step S5 to S15 is performed for r = 0 (FIG. 12C), and the process from step S5 to S13 is performed for r = 1 (FIG. 12D). Here, since r = 0 is selected in step S13 for r = 1, the processing in step S13 is repeated, and the processing in steps S5 to S12 is performed for the next selected r = 3 (FIG. 12E). The bit string BIS _{n, r, c} corresponding to all integers r between 0 and 3 is generated, and the round key generation process for the nth round is completed.

<Features of this embodiment>
FIGS. 13 and 14 are diagrams illustrating an example in which an error is mixed in the round key generation process when the first embodiment is applied to AES.

[Mixture of 32-bit error]
During the generation of the round key for the ninth round, an attacker intentionally changes the power supply voltage of the cryptographic operation device 10 from the outside, and a failure occurs in 32 bits in the r = 1 row of the ninth round as shown in FIG. Suppose you woke up. However, since the processing in this embodiment is performed in units of columns, and the data stored in the storage unit 10a at the time of processing is also in units of columns (FIGS. 7 to 11), the same error value in the column direction is thus obtained in the ninth round. Does not propagate, the number of bytes from which this error value information can be obtained is reduced. This makes it difficult to analyze at the time of attack, and thus improves the safety against DFA attacks.

[Mixture of 16-bit error]
During the generation of the round key for the ninth round, the attacker intentionally changes the power supply voltage of the cryptographic operation device 10 from the outside, and as shown in FIG. 13, the bit string BIS _9, 1 in the row of r = 1 in the ninth round _{, 0} and BIS _{9 , 1, 1} 16 bits are _assumed to have failed. However, since the processing in this embodiment is performed in units of columns, and the data stored in the storage unit 10a at the time of processing is also in units of columns (FIGS. 7 to 11), the inserted 16-bit error is 10 rounds. It propagates only to the row of r = 1 of the eye and does not propagate in the column direction. Therefore, the error propagated to the round key of the 10th round is only the row of r = 1, and no error occurs in the other rows. Therefore, the information that can be obtained by the attacker through this DFA attack is limited to the portion corresponding to the row of r = 1 that caused the failure. As a result, the amount of information that can be obtained by an attacker by inserting a single failure is reduced, and analysis at the time of the attack becomes difficult, thus improving the safety against DFA attacks.

[Features by selecting random integer r]
In this embodiment, the integer r that identifies the row to be processed is a random integer. As a result, the processing order of each row of the round key at the time of generation of the round key becomes random, and it becomes difficult to cause a failure in a bit at a specific position aimed by the attacker. As a result, it becomes difficult for an attacker to obtain a secret key by a DFA attack.

  As described above, since the DFA attack can be suppressed without performing error detection or error correction in the method according to the present embodiment, an increase in arithmetic processing associated with error detection or error correction is required in the software implementation as in the present embodiment. It is possible to improve the safety against DFA attacks without imitating.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.
Similarly to the first embodiment, in this embodiment, the bit string BIS _{n, r, c} generated in the n-th round is overwritten on the area 10aa in which the bit string BIS _{n-1, r, c} of the storage unit 10a was stored. . Further, in order to obtain the bit string BIS _{n, r, c} , the bit string BIS _{n-1, r, c} and the bit string BIS _{n-1, (r + k) mod (R + 1), C} are required. Here, for example, k = 1, bit string BIS _{n, 1, c} is obtained, and after overwriting the area 10aa in which bit string BIS _{n-1, r, c} is stored, r = 0 is selected. Assume that a process for obtaining the bit string BIS _{n, 0, c} is executed. In this case, in order to obtain the bit string BIS _{n, 0, c} , the bit string BIS _{n-1,0, c} and the bit string BIS _{n-1,1, C} are required, but the bit string BIS _{n-1,1 in the} region 10aa is required. _{, C} is overwritten by the bit string BIS _{n, 1, C.} Therefore, in the first embodiment, another area 10ac is secured, and the bit string BIS _{n-1, 1, C and the} like are stored therein.

In this embodiment, k = 1 or −1, and each time the selection unit 10f, the replacement unit 10i, the right shift unit 10g, and the exclusive OR operation units 10h and 10j are repeated, the selection unit 10f is (r + k). Select mod (R + 1) as the new integer r. Thus, except for the last row of each round, the bit string BIS _{n−1, (r + k) mod (R + 1), C} is overwritten by BIS _{n, (r + k) mod (R + 1), C} before the bit string BIS _n, Used to generate _{r and c} . As a result, the amount of data stored in the area 10ac can be reduced. Hereinafter, only differences from the first embodiment will be described.

  FIG. 15 is a flowchart for explaining round key generation processing in the n-th round according to the second embodiment. FIG. 16 is a diagram for explaining each processing target in the n-th round of the second embodiment. Hereinafter, the difference between the second embodiment and the first embodiment will be described with reference to these drawings.

As shown in FIG. 15, in the present embodiment, the processing of steps S1 to S3 of the first embodiment is executed, and the control unit 10c duplicates the bit string BIS _{n-1, r, C} and stores it in the W of the storage unit 10a. Store in the bit area 10ac (step S104). Next, the same process as step S5 of the first embodiment is executed. However, the replacement unit 10i according to the present embodiment, as a general rule, uses the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the area 10aa according to a predetermined rule according to a predetermined rule CBIS _{n−1, r, C} And the area 10aa is updated with the generated bit string CBIS _{n-1, r, C} (step S5). Then, only when processing the last column in which the bit string BIS _{n−1, (r + k) mod (R + 1), C} does not exist in the area 10aa, the replacement unit 10i performs the bit string BIS _{n−1, (r + k)} stored in the area 10aa. _{) A} bit string CBIS _{n-1, r, C} is generated from _{mod (R + 1), C.}

After that, the processing of steps S6 to S12 of the first embodiment is executed, and it is determined in step S12 that the bit strings BIS _{n, r, c} respectively corresponding to all integers r of 0 or more and R or less have been generated. When the round key generation process for the n-th round is completed and it is determined that it has not been generated, the selection unit 10f selects (r + k) mod (R + 1) as a new integer r (step S113). The selected integer r is stored in the temporary storage unit 10b, whereby the integer r stored in the temporary storage unit 10b is updated, and thereafter read out to each processing unit as necessary. Next, the control unit 10c duplicates the bit string of the area 10ab and stores it in the area 10aa (step S15), and returns the process to step S5.

With the above processing, the amount of data to be stored in the area 10ac can be reduced. For example, as illustrated in FIG. 16, when k = 1 and C = R = 3 and r = 1 is selected in step S3, the columns to be processed are r = 1, 2, 3, 0. Change in order. In this case, at the time of obtaining the bit string BIS _{n, r, c} corresponding to each of r = 1, 2, 3 (FIG. 16 (a) to (c)), the bit string BIS _{n of the} area 10aa necessary for obtaining them. _{−1, (r + 1) mod 4} , ₃ is not overwritten by BIS _{n, (r + 1) mod 4, c} and is in an available state. On the other hand, at the time of _obtaining the bit string BIS _{n, 0, c} corresponding to each r = 0 (FIG. 16 (d)), the bit string BIS _n-1,1,3 of the area _10aa necessary for _{obtaining them} is It is overwritten by BIS _{n, 1, c} which is the processing result of 16 (a) and cannot be used. Therefore, when obtaining the bit string BIS _{n, 0, c} corresponding to the last row, the bit string BIS _n-1,1,3 stored in the area 10ac in step S104 is used. That is, in this case, only the bit string BIS _n-1,1,3 needs to be stored in the area 10ac.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. The present embodiment is a modification of the first embodiment, and executes each process corresponding to the integer r regardless of whether or not the bit string BIS _{n, r, c} for the selected integer r has already been obtained. This is the difference from the first embodiment. That is, the determination in step S14 is not performed. Hereinafter, only differences from the first embodiment will be described.

FIG. 17 is a flowchart for explaining round key generation processing in the n-th round according to the third embodiment. 18 to 22 are diagrams exemplifying bit strings stored in the respective areas 10aa to 10ac of the storage unit 10a when the third embodiment is applied to AES. When the third embodiment is applied to AES, R and C are 3, W is 8, L is 128, k is 1, and CBIS _{n-1, r, C} is a bit string BIS _{n. This is} an 8-bit bit string obtained by replacing _{-1, (r + 1) mod 4} , 3 according to a predetermined replacement rule.

In the round key generation process of the n-th round in this embodiment, first, the round key K _n-1 ε {0, 1} ^L having the length L = W · (C + 1) · (R + 1) bits in the ( _n−1 ) _th round is first obtained. It is stored in the area 10ac of the storage unit 10a (step S201). Further, the control unit 10c duplicates the round key K _n−1 and stores it in the areas 10aa and 10ab of the storage unit 10a (steps S302 and S2, FIG. 18A).

  Next, the selection unit 10f selects a random integer r of 0 or more and R or less (Step S3). In the example shown in FIGS. 18 to 22, r = 2 is selected.

Next, the replacement unit 10i generates a W-bit bit string CBIS _{n-1, r, C} from the bit string BIS _{n-1, (r + k) mod (R + 1), C} stored in the area 10ac according to a predetermined rule. The area 10aa is updated with the generated bit string CBIS _{n-1, r, C} (step S205, FIG. 18B).

Thereafter, after steps S6 to S11 of the first embodiment are executed (FIGS. 18B to 21), the control unit 10c performs bit sequences BIS _{n, r} respectively corresponding to all integers r of 0 or more and R or less. _{, C} are determined (step S12). Here, when it is determined that the bit strings BIS _{n, r, c} corresponding to all integers r between 0 and R have been generated, the round key generation process for the n-th round is completed.

On the other hand, when it is determined that the bit string BIS _{n, r, c} corresponding to any integer r between 0 and R is not generated, the control unit 10c duplicates the bit string of the area 10ab and stores it in the area 10aa. Store (step S15, FIG. 22), and the process returns to step S3.

<Features of this embodiment>
As described above, according to the present embodiment, regardless of whether or not the bit string BIS _{n, r, c} for the selected integer r has already been obtained, the bit string BIS _n, Unless _{r and c} are generated, each process corresponding to the integer r is executed. In this case, since the presence or absence of the iterative process does not change according to the value of the integer r, it is possible to prevent information such as the calculation order from leaking to the attacker due to a change in power consumption accompanying a change in calculation contents. As a result, safety is improved.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. This embodiment is a modification of the first embodiment. By devising a method for storing data in the storage unit, the storage area to be used can be reduced as compared with the first embodiment while using a random integer r. It is a form. Below, it demonstrates centering on difference with 1st Embodiment.

  23 and 24 are flowcharts for explaining round key generation processing in the n-th round according to the fourth embodiment. FIGS. 25 to 28 are diagrams exemplifying bit strings stored in the respective areas of the storage unit when the fourth embodiment is applied to AES.

In the present embodiment, first, after executing the processing of steps S1 to S3 of the first embodiment, the control unit 10c duplicates the bit string BIS _{n-1, r, C} stored in the area 10aa and outputs it as W bits. In the area 10ac (FIG. 25A). Then, the process of step S6 to S10 of 1st Embodiment is performed (FIG.25 (b) to FIG.27). If it is determined in step S9 that i = C−1, the replacement unit 10i determines from the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the region 10aa or the region 10ac. The W-bit bit string CBIS _{n-1, r, C} is generated in accordance with the above rule, and is overwritten on the area 10aa _where any bit string BIS _{n-1, r, c} was initially stored (step S255, FIG. 28). Then, the exclusive OR operation unit 10j reads the bit string CBIS _{n-1, r, C} stored in the area 10aa and the W bit bit string XORBIS _{n-1, r, c} stored in the area 10ab, The exclusive OR of these is calculated for each c = 0, 1,..., C, and each operation result corresponding to each c is converted into an upper round W {( _n) of the round key K _n ε {0, 1} ^L of the _n- th round. Bit sequence BIS _{n, r, c} = CBIS _{n-1, r, C} (+) XORBIS _{n-1, r, c} from R + 1) · c + r} +1 bit to W {(R + 1) · c + r + 1} bit, The area 10ab is updated with the bit string BIS _{n, r, c} (step S261, FIG. 28). Thereafter, the processing from step S12 to S14 of the first embodiment is executed, and when it is determined in step S14 that the bit string BIS _{n, r, c} corresponding to the integer r selected in step S13 has not been generated. The control unit 10c duplicates the bit string BIS _{n-1, r, C} , overwrites the used area in the area 10aa, and returns the process to step S6. The used area of the area 10aa means an area of the area 10aa that has already been used in the processing from step S7 to S10. In this way, the bit string CBIS _{n-1, r, C} is generated after the end of the shift operation, and the used area of the area 10aa is used to reduce the necessary number of bits of the area 10ac to W bits. it can.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. The present embodiment is a modification of the first and second embodiments. The cryptographic operation of the present embodiment is implemented by a cryptographic processor that performs cryptographic operations, and k = 1 or −1 as in the second embodiment. Each time the selection unit 10f, the replacement unit 10i, the right shift unit 10g, and the exclusive OR operation units 10h and 10j are repeated, the selection unit 10f selects (r + k) mod (R + 1) as a new integer r. It is a form to do. Below, it demonstrates centering on difference with 1st, 2 embodiment.

<Configuration>
FIG. 29 is a block diagram for explaining a hardware configuration of the cryptographic operation device 110 according to the fifth embodiment.
As shown in FIG. 29, the cryptographic operation device 110 of this embodiment includes a central processing unit (CPU) 11, a random-access memory (RAM) 12, a read-only memory (ROM) 13, an EEPROM 14, and random number generation. Device 15, input interface (IF) 16, output interface (IF) 17, data bus 18, and cryptographic processor 111. The EEPROM 14 stores a predetermined program and a round key K ₀ ε {0, 1} ^{L for the} _0th round. These programs and the round key K ₀ are respectively written in the RAM 12, and further, the CPU 11 executes the program written in the RAM 12 and performs cryptographic calculation processing using the round key K ₀ , whereby the cryptographic calculation device 110 of the present embodiment. Is built. The functional configuration constructed by the cryptographic operation device 110 of this embodiment is the same as that shown in FIG.

<Processing>
Next, the processing of this embodiment will be described. In the following, after generalizing the processing of this embodiment, the processing when this embodiment is applied to AES will be specifically exemplified.
[Generalized processing contents]
FIG. 30 is a flowchart for explaining round key generation processing in the n-th round according to the fifth embodiment. Hereinafter, the generalized processing of this embodiment will be described with reference to FIG.
In the round key generation process of the n-th round in this embodiment, first, the round key K _n−1 ε {0, 1} ^L having the length L = W · (C + 1) · (R + 1) bits in the ( _n−1 ) _th round is obtained. It is stored in the area 10aa of the storage unit 10a (step S1). Next, the selection unit 10f selects a random integer r of 0 or more and R or less (Step S3). Next, the control unit 10c duplicates the bit string BIS _{n-1, r, C} and stores it in the W-bit area 10ac of the storage unit 10a (step S104). Further, the bit string BIS _{n-1, r, C 0} , BIS _{n-1, r, 1} ,..., BIS _{n-1, r, C} are duplicated and stored in the area 10ab (step S304).

Next, the replacement unit 10i converts the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the area 10aa or the area 10ac into a W-bit bit string CBIS _{n−1, r, C} according to a predetermined rule. The generated bit string CBIS _{n-1, r, C} is stored in the area 10ac (step S305). Since the bit string BIS _{n−1, (r + k) mod (R + 1), C} is always stored in the area 10aa except for the case where the process of step S305 is performed last in the n-th round, the replacement unit 10i The processing of this step is performed using the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in 10aa. On the other hand, when the process of step S305 is performed at the end of the n-th round, since the bit string BIS _{n−1, (r + k) mod (R + 1), C} is not stored in the area 10aa, the replacement unit 10i is in the area 10ac. The processing of this step is performed using the stored bit string BIS _{n−1, (r + k) mod (R + 1), C.} In addition, since it is also assumed that an attacker will cause a failure in the process of step S305, it is preferable to add a verification process for confirming that the correct process has been performed in step S305.

Next, the control unit 10c sets the variable i to 0 and stores it in the temporary storage unit 10b (step S6). Thereafter, the right shift unit 10g generates a bit string BIS _{n−1, r} (i + 1) obtained by shifting the bit string BIS _{n−1, r} (i) stored in the area 10ab by W bits downward. Thus generated bit string _{BIS n-1, r (i} + 1) is overwritten in a position where the bit string regions _{10ab BIS n-1, r (} i) is stored, the area 10ab is updated (step S307 ).

Next, the exclusive OR operation unit 10h exclusives the bit string XORBIS _{n−1, r} (i) stored in the area 10aa and the bit string BIS _{n−1, r} (i + 1) stored in the area 10ab. OR value XORBIS _{n-1, r} (i + 1) = XORBIS _{n-1, r} (i) (+) BIS _{n-1, r} (i + 1) is calculated. Calculated bit string _{XORBIS n-1, r (i} + 1) is overwritten in a position where the bit string region _{10aa XORBIS n-1, r (} i) is stored, the area 10aa is updated (step S308).

  Next, the control unit 10c refers to the value of the variable i stored in the temporary storage unit 10b, and determines whether i = C-1 (step S9). When it is determined that i = C−1 is not satisfied, the control unit 10c updates the variable i with i + 1 as the value of the new variable i, stores the variable i in the temporary storage unit 10b, and performs processing. The process returns to step S307 (step S10).

On the other hand, if it is determined in step S9 that i = C-1, the exclusive OR operation unit 10j stores the bit string CBIS _{n-1, r, C} stored in the area 10ac and the area 10aa. Read W-bit bit string XORBIS _{n−1, r, c,} and calculates an exclusive OR of them for each c = 0, 1,..., C, and n rounds each operation result corresponding to each c Bit string BIS _{n, r, c} = CBIS _n− from the upper W {(R + 1) · c + r} +1 bit to the W {(R + 1) · c + r + 1} bit of the round key K _n ε {0,1} ^L _{1, r, C} (+) XORBIS _{n-1, r, c,} and the area 10aa is updated with the bit string BIS _{n, r, c} (step S311).

Next, the control unit 10c determines whether or not the bit strings BIS _{n, r, c} respectively corresponding to all integers r greater than or equal to 0 and less than or equal to R have been generated (step S12). Here, when it is determined that the bit strings BIS _{n, r, c} corresponding to all integers r between 0 and R have been generated, the round key generation process for the n-th round is completed. On the other hand, if it is determined that the bit string BIS _{n, r, c} corresponding to any integer r between 0 and R is not generated, the selection unit 10f sets (r + k) mod (R + 1) to a new integer r. (Step S113), and the process returns to step S304.

[Processing contents when this form is applied to AES]
Next, processing when the fifth embodiment is applied to AES will be described. In this case, R and C are 3, W is 8, L is 128, k is 1, and CBIS _{n-1, r, C} is a bit string BIS _{n-1, (r + 1) mod 4, This} is an 8-bit bit string in which ₃ is replaced according to a predetermined replacement rule.

  FIGS. 31 to 34 are diagrams illustrating bit strings stored in the respective areas 10aa to 10ac of the storage unit 10a when the fifth embodiment is applied to AES. In the following, an n-th round key generation process when the present embodiment is applied to AES will be described with reference to these drawings.

In this example of round key generation processing, first, the 128-bit round key K _n-1 ε {0, 1} ^{128 of the} ( _{n-1) th} round is stored in the area 10aa of the storage unit 10a (step S1). . That is, the bit string BIS _{n−1, r, c} (all r, c satisfying 0 ≦ r, c ≦ 3) is stored in the area 10aa (FIG. 31 (a)). Next, the selection unit 10f selects a random integer r of 0 or more and 3 or less (Step S3). In this example, it is assumed that r = 1 is selected.

Next, the control unit 10c duplicates the bit string BIS _n-1,1,3 , stores it in the 8-bit area 10ac of the storage unit 10a (step S104), and further, the bit string BIS _n- 1,1,3 _{. 0} , BIS _n-1,1,1 , BIS _n-1,1,2 , BIS _n-1,1,3 are duplicated and stored in the area 10ab (step S304, FIG. 31 (a)).

Next, the replacement unit 10i generates an 8-bit bit string CBIS _n-1,1,3 from the bit string BIS _n-1,2,3 stored in the area 10aa according to a predetermined rule, and the generated bit string CBIS _{n- 1, 1,} and 3 are stored in area | region 10ac (step S305, Fig.31 (a)).

Next, the control unit 10c sets the variable i to 0 and stores it in the temporary storage unit 10b (step S6). Thereafter, the right shift unit 10g receives the bit string BIS _n−1,1 (0) = BIS _n−1,1,0 | BIS _n−1,1,1 | BIS _n−1,1, stored in the area 10ab _{. 2} | BIS _n-1,1,3 is a bit string BIS _n-1,1 (1) = 0 shifted to the lower 8 bits BIS _n-1,1,0 | BIS _n-1,1,1 | BIS _n-1,1,2 are generated. The bit string BIS _n-1,1 (1) generated in this way is overwritten at the position where the bit string BIS _n-1,1 (0) of the area 10ab was stored, and the area 10ab is updated (step S307). FIG. 31 (b)).

Next, the exclusive OR operation unit 10h uses the bit string XORBIS _n−1,1 (0) = BIS _n−1,1,0 | BIS _n−1,1,1 | BIS _n− stored in the area 10aa. _{1, 1, 2} | BIS _n−1,1,3 and the bit string BIS _{n−1, r} (1) = 0 stored in the area 10ab = 0 | BIS _n−1,1,0 | BIS _{n−1,1 ,} 1 _{| BIS} exclusive-OR value _{XORBIS n-1,1 (1)} with _n-1,1,2 = XORBIS _n-1,1 to _{(0) (+) BIS n} -1,1 (1) calculate. The calculated bit string XORBIS _n-1,1 (1) is overwritten at the position where the bit string XORBIS _n-1,1 (0) of the area 10aa was stored, and the area 10aa is updated (step S308, FIG. 31). (B)).

Next, the control unit 10c refers to the value of the variable i stored in the temporary storage unit 10b, and determines whether i = 2 (step S9). Here, since i is not 2, the control unit 10c updates the variable i with 1 as the value of the new variable i, stores the variable i in the temporary storage unit 10b, and returns the process to step S307 (step S307). S10). Thereafter, after the processes of steps S307 and S308 are repeated for i = 1, 2 (FIGS. 32 and 33), it is determined that i = 2 in step S9. As a result, the exclusive OR operation unit 10j reads the bit string CBIS _n-1,1,3 stored in the area _10ac and the W bit bit string XORBIS _n-1,1,3 stored in the area _10aa. The exclusive OR of these is calculated for each c = 0, 1, 2, 3, and each operation result corresponding to each c is calculated as the bit string BIS _{n of the n- th} round key K _n ε {0, 1} ^L. _{, 1 and c} , and the area 10aa is updated (step S311, FIG. 34).

Next, the control unit 10c determines whether or not the bit strings BIS _{n, r, c} respectively corresponding to all integers r greater than or equal to 0 and less than or equal to R have been generated (step S12). Here, when it is determined that the bit strings BIS _{n, r, c} corresponding to all integers r of 0 or more and 3 or less have been generated, the round key generation process for the n-th round ends. On the other hand, when it is determined that the bit string BIS _{n, r, c} corresponding to any integer r between 0 and 3 has not been generated, the selection unit 10f selects 2 as a new integer r (step S113). ), The process returns to step S304.

Thereafter, the processing from step S304 to S311 is performed for r = 2, 3, 0, and the bit string BIS _{n, r, c} corresponding to all integers r of 0 or more and 3 or less has been generated, and the n-th round key The generation process ends.

<Features of this embodiment>
In the method of this embodiment, a DFA attack can be suppressed without performing error detection or error correction. Therefore, in a hardware implementation such as this embodiment, a circuit for performing error detection and error correction is added. The safety against DFA attacks can be improved without causing the accompanying increase in circuit scale.

  The present invention is not limited to the embodiment described above. For example, each data may be stored in the storage unit by a method other than the above, such as storing each data in the storage unit without overwriting until a round key is generated. In addition, the various processes described above are not only executed in time series according to the description, but may be executed in parallel or individually according to the processing capability of the apparatus that executes the processes or as necessary. Needless to say, other modifications are possible without departing from the spirit of the present invention.

  Further, when the above-described configuration is realized by a computer, processing contents of functions that each device should have are described by a program. The processing functions are realized on the computer by executing the program on the computer.

  The program describing the processing contents can be recorded on a computer-readable recording medium. As the computer-readable recording medium, for example, any recording medium such as a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory may be used.

  The program is distributed by selling, transferring, or lending a portable recording medium such as a DVD or CD-ROM in which the program is recorded. Furthermore, the program may be distributed by storing the program in a storage device of the server computer and transferring the program from the server computer to another computer via a network.

  A computer that executes such a program first stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its storage device. When executing the process, the computer reads a program stored in its own recording medium and executes a process according to the read program. As another execution form of the program, the computer may directly read the program from a portable recording medium and execute processing according to the program, and the program is transferred from the server computer to the computer. Each time, the processing according to the received program may be executed sequentially. Also, the program is not transferred from the server computer to the computer, and the above-described processing is executed by a so-called ASP (Application Service Provider) type service that realizes the processing function only by the execution instruction and result acquisition. It is good. Note that the program in this embodiment includes information that is used for processing by an electronic computer and that conforms to the program (data that is not a direct command to the computer but has a property that defines the processing of the computer).

  The present invention can be used, for example, for AES DFA prevention measures.

FIG. 1 is a diagram for explaining processing of a conventional extended key generation unit. FIG. 2 is a diagram for explaining the processing of the conventional extended key generation unit when a failure occurs in the ninth round. FIG. 3A is a block diagram for explaining a hardware configuration of the cryptographic operation apparatus according to the first embodiment. FIG. 3 (b), illustrating the functional configuration of the cryptographic computation apparatus which is constructed by performing a cryptographic operation processing CPU11 executes the program written in the RAM, using a round key K ₀ in FIGS. 3 (a) It is a block diagram for doing. FIG. 4 is a flowchart for explaining round key generation processing in the n-th round according to the first embodiment. FIG. 5 is a flowchart for explaining round key generation processing in the n-th round according to the first embodiment. FIG. 6 is a diagram illustrating the entire processing at r = 2 when the first embodiment is applied to AES. FIG. 7 is a diagram illustrating a bit string stored in each area of the storage unit when the first embodiment is applied to AES. FIG. 8 is a diagram illustrating a bit string stored in each area of the storage unit when the first embodiment is applied to AES. FIG. 9 is a diagram illustrating a bit string stored in each area of the storage unit when the first embodiment is applied to AES. FIG. 10 is a diagram illustrating a bit string stored in each area of the storage unit when the first embodiment is applied to AES. FIG. 11 is a diagram illustrating a bit string stored in each area of the storage unit when the first embodiment is applied to AES. FIG. 12A is a diagram for explaining an example of the integer r selected by the selection unit when the first embodiment is applied to AES. FIG. 12B to FIG. It is a figure which shows the process target corresponding to each selected integer r. FIG. 13 is a diagram illustrating a state in which an error is mixed in the round key generation process when the first embodiment is applied to AES. FIG. 14 is a diagram illustrating a state in which an error is mixed in the round key generation process when the first embodiment is applied to AES. FIG. 15 is a flowchart for explaining round key generation processing in the n-th round according to the second embodiment. FIG. 16 is a diagram for explaining each processing target in the n-th round of the second embodiment. FIG. 17 is a flowchart for explaining round key generation processing in the n-th round according to the third embodiment. FIG. 18 is a diagram illustrating a bit string stored in each area of the storage unit when the third embodiment is applied to AES. FIG. 19 is a diagram illustrating a bit string stored in each area of the storage unit when the third embodiment is applied to AES. FIG. 20 is a diagram illustrating a bit string stored in each area of the storage unit when the third embodiment is applied to AES. FIG. 21 is a diagram illustrating a bit string stored in each area of the storage unit when the third embodiment is applied to AES. FIG. 22 is a diagram illustrating a bit string stored in each area of the storage unit when the third embodiment is applied to AES. FIG. 23 is a flowchart for explaining round key generation processing in the n-th round according to the fourth embodiment. FIG. 24 is a flowchart for explaining round key generation processing in the n-th round according to the fourth embodiment. FIG. 25 is a diagram illustrating a bit string stored in each area of the storage unit when the fourth embodiment is applied to AES. FIG. 26 is a diagram illustrating a bit string stored in each area of the storage unit when the fourth embodiment is applied to AES. FIG. 27 is a diagram illustrating a bit string stored in each area of the storage unit when the fourth embodiment is applied to AES. FIG. 28 is a diagram illustrating a bit string stored in each area of the storage unit when the fourth embodiment is applied to AES. FIG. 29 is a block diagram for explaining a hardware configuration of the cryptographic operation apparatus according to the fifth embodiment. FIG. 30 is a flowchart for explaining round key generation processing in the n-th round according to the fifth embodiment. FIG. 31 is a diagram illustrating a bit string stored in each area of the storage unit when the fifth embodiment is applied to AES. FIG. 32 is a diagram illustrating a bit string stored in each area of the storage unit when the fifth embodiment is applied to AES. FIG. 33 is a diagram illustrating a bit string stored in each area of the storage unit when the fifth embodiment is applied to AES. FIG. 34 is a diagram illustrating a bit string stored in each area of the storage unit when the fifth embodiment is applied to AES.

Explanation of symbols

10,110 Cryptographic operation device

Claims (12)

A cryptographic operation device that performs a cryptographic operation using a round key,
A round key K of L = W · (C + 1) · (R + 1) bits in the (n−1) th round when R, C and W are constants of integers of 1 or more and n is a variable of integers of 1 or more. _n-1 ∈ {0, 1} storage unit for storing ^L ;
A selection unit for selecting an integer r of 0 or more and R or less,
Let c be an integer variable between 0 and C, and a bit string of W bits consisting of the upper W {(R + 1) · c + r} +1 bit to W {(R + 1) · c + r + 1} bit of the round key K _n−1 BIS _{n-1, r, c} , BIS _{n-1, r} (0) = BIS _{n-1, r, 0} | BIS _{n-1, r, 1} | ... | BIS _{n-1, r, C} Right shift unit for generating a bit string BIS _{n-1, r} (i + 1) obtained by shifting the bit string BIS _{n-1, r} (i) to the lower order by W bits when i is an integer of 0 to C-1. When,
A first exclusive OR operation unit for obtaining a bit string XORBIS _{n−1, r} (C) that is an exclusive OR of each bit string BIS _{n−1, r} (j) corresponding to each j of 0 or more and C or less; ,
Suppose that k is an integer constant between −R and R, and a bit string of W bits uniquely determined with respect to the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the storage unit is CBIS _{n− 1, r, C,} and XORBIS _{n-1, r} (C) = XORBIS _{n-1, r, 0} | XORBIS _{n-1, r, 1} | ... | W satisfying XORBIS _{n-1, r, C XORBIS n-1} each bit _{string, r,} in the case of a _{c, CBIS n-1, r} , C and _{XORBIS n-1, r,} the exclusive OR of the _c was calculated for each c, the c The bit string BIS from the upper W {(R + 1) · c + r} +1 bit to the W {(R + 1) · c + r + 1} bit of the _n-th round key K _n ε {0,1} ^L output as _{n, r, c} 2 exclusive OR operation part;
Until each bit string BIS _{n, r, c} of round key K _n is obtained for all integers r between 0 and R, the selection unit, the right shift unit, the first exclusive OR operation unit, and the first 2 a control unit that repeatedly executes each process of the exclusive OR operation unit;
A cryptographic operation device. The cryptographic operation device according to claim 1,
The selection unit selects a random integer r of 0 or more and R or less,
A cryptographic operation device characterized by that. The cryptographic operation device according to claim 2,
When the bit string BIS _{n, r, c} for the integer r selected by the selection unit has already been obtained, the control unit, the right shift unit corresponding to the integer r, the first exclusive OR Without causing the selection unit to select a new random integer r without repeatedly executing each process of the calculation unit and the second exclusive OR calculation unit,
A cryptographic operation device characterized by that. The cryptographic operation device according to claim 2,
Regardless of whether or not the bit string BIS _{n, r, c} for the integer r selected by the selection unit has already been obtained, the control unit performs the right shift unit corresponding to the integer r, the first exclusive Causing each process of the logical sum operation unit and the second exclusive OR operation unit to be executed;
A cryptographic operation device characterized by that. The cryptographic operation device according to claim 1,
A replacement unit for generating the bit string CBIS _{n-1, r, C} from the bit string BIS _{n-1, (r + k) mod (R + 1), C} stored in the storage unit according to a predetermined rule;
The control unit performs processing in the order of processing of the selection unit, processing of the replacement unit, processing of the right shift unit, processing of the first exclusive OR operation unit, and processing of the second exclusive OR operation unit. Repeat each process,
The bit string BIS _{n, r, c} output from the second exclusive OR operation unit is overwritten on the area where the bit string BIS _{n-1, r, c} of the storage unit is stored,
k is 1 or -1,
Each time the selection unit, the replacement unit, the right shift unit, the first exclusive OR operation unit, and the second exclusive OR operation unit are repeated, the selection unit is (r + k) mod. Select (R + 1) as the new integer r,
A cryptographic operation device characterized by that. The cryptographic operation device according to any one of claims 1 to 5,
R and C are 3, W is 8, L is 128, k is 1, and CBIS _{n-1, r, 3} is a bit string BIS _{n-1, ( r + 1) mod 4 , 3} is an 8-bit bit string that is replaced according to a predetermined replacement rule, and bit string CBIS _{n-1, r, 3} and bit string BIS _{n-1, (r + 1) mod 4,3} have a one-to-one correspondence.
A cryptographic operation device characterized by that. A cryptographic operation method for performing a cryptographic operation using a round key,
(a) When R, C, and W are integer constants of 1 or more and n is an integer variable of 1 or more, the length of L = W · (C + 1) · (R + 1) bits in the (n−1) th round Storing the round key K _n-1 ε {0, 1} ^L in the storage unit;
(b) the selection unit selecting an integer r not less than 0 and not more than R;
(c) The right shift unit uses c as an integer variable not less than 0 and not more than C, and the upper W {(R + 1) · c + r} +1 bit to W {(R + 1) · c + r + 1} bit of the round key K _n−1 a bit string of W bits consisting of up to a _{BIS n-1, r, c} , BIS n-1, r (0) = BIS n-1, r, 0 | BIS n-1, r, 1 | ... | BIS n _{−1, r, C} , where i is an integer between 0 and C−1, the bit string BIS _{n−1, r} (i + 1) obtained by shifting the bit string BIS _{n−1, r} (i) downward by W bits )
(d) XORBIS _{n-1, r} (i) and bit string BIS _{n when} the first exclusive OR operation unit sets XORBIS _{n-1, r} (0) = BIS _{n-1, r} (0) Calculating an exclusive OR value XORBIS _{n−1, r} (i + 1) with _{−1, r} (i + 1);
(e) The second exclusive OR operation unit sets k to an integer constant not less than −R and not more than R, for the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the storage unit. An exclusive OR obtained by executing the steps (c) and (d) for each integer i not less than 0 and not more than C−1 _{, where} CBIS _{n−1, r, C} is a uniquely determined W bit string. For the value XORBIS _{n-1, r} (C), XORBIS _{n-1, r} (C) = XORBIS _{n-1, r, 0} | XORBIS _{n-1, r, 1} | ... | XORBIS _{n-1, r, XORBIS n-1} each bit string of W bits satisfying _{C, r,} in the case of a _{c, CBIS n-1, r} , C and _{XORBIS n-1, r,} each of the exclusive OR of the _c c And the operation result corresponding to each c is the nth round key _n ∈ ^{{0,1} L} Top W {(R + 1) · c + r} W +1 bit {(R + 1) · c + r + 1} bit string _{BIS n} to bit _of, a _r, and outputting as _c, and ,
Wherein the step (b) (e) is a step which is repeatedly executed for all integers r of 0 or more R less until each bit string BIS n round key K _{n, r, c} are obtained,
A cryptographic operation method characterized by the above. The cryptographic operation method according to claim 7,
The step (b) is a step of selecting a random integer r not less than 0 and not more than R.
A cryptographic operation method characterized by the above. The cryptographic operation method according to claim 7,
(f) The replacing unit further includes a step of generating a bit string CBIS _{n−1, r, C} from the bit string BIS _{n−1, (r + k) mod (R + 1), C} stored in the storage unit according to a predetermined rule. And
Steps (b) to (f) are steps that are repeatedly executed in the order of step (b), step (f), step (c), step (d), step (e),
The bit string BIS _{n, r, c} generated in step (e) is overwritten on the area where the bit string BIS _{n-1, r, c} of the storage unit is stored,
k is 1 or -1,
Each time the process from step (b) to (f) is repeated, (r + k) mod (R + 1) is selected as a new integer r in step (b).
A cryptographic operation method characterized by the above. The cryptographic operation method according to claim 8, comprising:
Regardless of whether or not the bit string BIS _{n, r, c} for the integer r selected in step (b) has already been obtained, the steps (c), (d), (e) corresponding to the integer r Execute each process of
A cryptographic operation method characterized by the above. A cryptographic calculation method according to any one of claims 7 to 10,
R and C are 3, W is 8, L is 128, k is 1, and CBIS _{n-1, r, 3} is a bit string BIS _{n-1, ( r + 1) mod 4 , 3} is an 8-bit bit string that is replaced according to a predetermined replacement rule, and bit string CBIS _{n-1, r, 3} and bit string BIS _{n-1, (r + 1) mod 4,3} have a one-to-one correspondence.
A cryptographic operation method characterized by the above.   A program for causing a computer to function as the cryptographic operation device according to any one of claims 1 to 6.

Images