JP2009302320A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of transmitting an electric field applied to a gate contact plug to a metal film at a sufficient speed even when contact resistance between the metal film being a gate electrode and a polycrystal silicon film is large; and a manufacturing method thereof. <P>SOLUTION: The semiconductor device is provided with: a semiconductor substrate 1; a gate insulating film 3 formed on the semiconductor substrate 1; a gate electrode 6 having the metal film 4 formed on the gate insulating film 3, and the polycrystalline silicon film 5 formed on the metal film 4; an interlayer insulation film 11 formed on the gate electrode 6; and a contact plug 12 formed to penetrate the interlayer insulation film 11 and the polycrystalline silicon film 5 to contact the metal film 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MIPS (Metal Inserted Poly-Si Stack) structure and a manufacturing method thereof.

  Conventionally, as a structure for adjusting a threshold voltage in a gate electrode, a MIPS (Metal Inserted Poly-Si Stack) structure having a metal film between a gate insulating film and a polycrystalline silicon film is known.

  FIG. 4 is a cross-sectional view showing a configuration of a conventional semiconductor device having a MIPS structure. As shown in the figure, in the conventional semiconductor device having the MIPS structure (the structure having the metal film 4 between the gate insulating film 3 and the polycrystalline silicon film 5), the gate contact plug 12 is the surface layer of the polycrystalline silicon film 5. The structure is in contact only with the silicide film 10 formed in the above. That is, the electric field applied to the gate contact plug 12 reaches the channel portion through the contact between the polycrystalline silicon film 5 and the metal film 4. A technique related to the MIPS structure is disclosed in Non-Patent Document 1 below.

H.T.Huang, et.al, 45 nm High-k / Metal-Gate CMOS Technology for GPU / NPU Applications with Highest PFET Performance, IEDM 2007, p. 285-288

  However, in the case where the contact resistance between the metal film and the polycrystalline silicon film is large, the electric field applied from the contact plug to the polycrystalline silicon film on the gate is sufficiently high at a sufficient speed, particularly in a fine MOS device. There was a problem of not being transmitted to the membrane.

  Therefore, the present invention has been made to solve such a problem, and even when the contact resistance between the metal film as the gate electrode / polycrystalline silicon film is large, the electric field applied to the gate contact plug is sufficient. It is an object of the present invention to obtain a semiconductor device that can be sufficiently transmitted to a metal film at a high speed and a manufacturing method thereof.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a metal film formed on the gate insulating film, and a polycrystalline silicon film formed on the metal film , An interlayer insulating film formed on the gate electrode, and a contact plug formed to contact the metal film through the interlayer insulating film and the polycrystalline silicon film.

  In one embodiment of the present invention, a semiconductor device manufacturing method includes first preparing a semiconductor substrate, forming a gate insulating film on the semiconductor substrate, and laminating a metal film and a polycrystalline silicon film on the gate insulating film in this order. To form a gate electrode. Next, an interlayer insulating film is formed over the gate electrode. Next, a contact hole is formed by etching the interlayer insulating film and the polycrystalline silicon film so that the metal film is exposed. Next, metal is deposited in the contact hole to form a contact plug.

According to the semiconductor device and the manufacturing method thereof in one embodiment of the present invention, the contact plug of the gate electrode is formed through the polycrystalline silicon film, so that the contact between the contact plug and the gate electrode is the metal / metal contact. Become. As a result, the contact resistance becomes 10 ⁻⁹ ohm · cm ² , and the contact resistance between the polycrystalline silicon film and the metal film can be reduced by 1 to 7 digits. Further, by making it possible to reduce the contact resistance, the electric field applied to the gate contact can be sufficiently transmitted to the metal film at a sufficient speed.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. Hereinafter, the configuration of the semiconductor device according to the present embodiment will be described with reference to FIG. The semiconductor device according to the present embodiment includes a silicon substrate 1 (semiconductor substrate) on which an element isolation region 2 is formed, a high-k gate insulating film 3 (gate insulating film) formed on the silicon substrate 1, and a high-k gate. A gate electrode 6 made of a metal film 4 (TiN in this embodiment) and a polycrystalline silicon film 5 (poly-Si) formed on the insulating film 3 is provided. That is, the semiconductor device in this embodiment has a MIPS structure.

  Further, the offset spacer 7 and the side wall 8 (in the present embodiment, a two-layer structure including the first side wall 8a and the second side wall 8b) formed on the side surface of the gate electrode 6, the polycrystalline silicon film 5 Formed on the silicide film 10 (Ni in the present embodiment) formed on the surface layer of a part of the region, on other regions of the polycrystalline silicon film 5 (regions where the silicide film 10 is not formed) and on the sidewalls 8 Hard mask 9 (silicon oxide film in this embodiment), interlayer insulating film 11 (first interlayer insulating film 11a (silicon nitride film) in this embodiment), second layer formed on hard mask 9; A two-layer structure comprising an interlayer insulating film 11b (silicon oxide film).

  Further, a contact plug 12 (barrier metal film 12a (TiN) and metal plug formed in this embodiment) is formed so as to penetrate through the interlayer insulating film 11, the hard mask 9 and the polycrystalline silicon film 5 and come into contact with the metal film 4. 12b (made of tungsten).

  As shown in FIG. 1, when the contact plug 12 of the gate electrode 6 is formed through the polycrystalline silicon film 5, the contact between the contact plug 12 and the gate electrode 6 is a Metal / Metal contact.

  2 and 3 are cross-sectional views showing a method for manufacturing a semiconductor device in the present embodiment. A method for manufacturing a semiconductor device according to the present embodiment will be described below with reference to FIGS. First, an element isolation region 2 and a well region (not shown) are formed on a silicon substrate 1 (FIG. 2A).

  Next, a high-k gate insulating film 3, a metal film 4 and a polycrystalline silicon film 5 are laminated in this order on the silicon substrate 1, and a gate electrode 6 having a MIPS structure is formed by a photo / dry etching process (FIG. 2b). )). Next, offset spacers 7 and sidewalls 8 are formed on the side surfaces of the gate electrode 6 (FIG. 2C).

  Next, a hard mask 9 is formed on the gate electrode 6, the offset spacer 7 and the sidewall 8 in the region where the gate contact is to be formed. Next, after forming a metal film on the silicon substrate 1, heat treatment is performed to form a silicide layer 10 on the surface layer of the polycrystalline silicon film 5 where the hard mask 8 is not formed (FIG. 3D).

  Next, a contact interlayer insulating film 11 such as a silicon nitride film 11a and a silicon oxide film 11b is deposited, and the metal layer 4 penetrates the interlayer insulating film 11, the hard mask 9 and the polycrystalline silicon film 5 by a photo / dry etching process. A contact hole 13 is formed so as to be exposed (FIG. 3E).

  Next, TiN of the barrier metal film 12a and tungsten of the metal plug 12b are deposited, and the contact plug 12 is formed by leaving the TiN 12a / tungsten 12b only in the contact hole 13 by the CMP method, whereby the semiconductor device shown in FIG. Is formed.

  Here, the metal film 4 is formed using any one of an alloy of a refractory metal, an alloy of a refractory metal and a rare earth metal, and an alloy containing a nitride, oxide and carbide thereof. More specifically, any one of TiN, TaC, TaN, La compound, Mg compound and Al compound is used. By using these as a metal film, productivity can be improved and the threshold voltage can be reduced.

As described above, according to the semiconductor device and the manufacturing method thereof in the present embodiment, the contact plug 12 of the gate electrode 6 is formed so as to penetrate the polycrystalline silicon film 5. The contact is a Metal / Metal contact. As a result, the contact resistance is 10 ⁻⁹ ohm · cm ² , and the contact resistance between the polycrystalline silicon film 5 and the metal film 4 can be reduced by 1 to 7 digits. Further, by making it possible to reduce the contact resistance, the electric field applied to the gate contact plug 12 can be sufficiently transmitted to the metal film 4 at a sufficient speed.

  The present invention can be applied to all products using MOS transistors. In particular, the present invention can be applied to SoC (System-on-chip) products in general after the 45 nm node.

It is sectional drawing which showed the structure of the semiconductor device in this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in this invention. It is sectional drawing which showed the structure of the semiconductor device in a prior art.

Explanation of symbols

  1 silicon substrate, 2 element isolation region, 3 high-k gate insulating film, 4 metal film, 5 polycrystalline silicon film, 6 gate electrode, 7 offset spacer, 8 sidewall, 8a first sidewall, 8b second Side wall, 9 hard mask, 10 silicide film, 11 interlayer insulating film, 11a first interlayer insulating film, 11b second interlayer insulating film, 12 contact plug, 12a barrier metal film, 12b metal plug, 13 contact hole.

Claims (8)

A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode having a metal film formed on the gate insulating film, a polycrystalline silicon film formed on the metal film, and
An interlayer insulating film formed on the gate electrode;
And a contact plug formed so as to penetrate the interlayer insulating film and the polycrystalline silicon film and come into contact with the metal film. A silicide layer formed in a surface layer of a partial region of the polycrystalline silicon film;
A hard mask formed on another region of the polycrystalline silicon film, and
2. The semiconductor device according to claim 1, wherein the contact plug is formed so as to penetrate through the interlayer insulating film, the hard mask, and the polycrystalline silicon film and to contact the metal film.   3. The semiconductor device according to claim 1, wherein the metal film is made of any one of an alloy of a refractory metal, an alloy of a refractory metal and a rare earth metal, and an alloy containing a nitride, an oxide, and a carbide thereof.   The semiconductor device according to claim 3, wherein the metal film is made of any one of TiN, TaC, TaN, La compound, Mg compound, and Al compound. (A) preparing a semiconductor substrate;
(B) forming a gate insulating film on the semiconductor substrate;
(C) forming a gate electrode by laminating a metal film and a polycrystalline silicon film in this order on the gate insulating film;
(D) forming an interlayer insulating film on the gate electrode;
(E) etching the interlayer insulating film and the polycrystalline silicon film to form a contact hole so that the metal film is exposed;
And (f) forming a contact plug by depositing a metal in the contact hole. (G) after the step (c), forming a hard mask on the polycrystalline silicon film in a region where the contact plug is to be formed;
(H) after the step (g), further comprising a step of forming a silicide layer in a region of the polycrystalline silicon film where the hard mask is not formed,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the step (e) forms a contact hole by etching the interlayer insulating film, the hard mask, and the polycrystalline silicon film so that the metal film is exposed. Method.   The step (c) forms a metal film made of any one of an alloy of a refractory metal, an alloy of a refractory metal and a rare earth metal, an alloy containing a nitride, an oxide and a carbide thereof. The manufacturing method of the semiconductor device of description.   The method of manufacturing a semiconductor device according to claim 7, wherein the step (c) forms a metal film made of any one of TiN, TaC, TaN, La compound, Mg compound, and Al compound.

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