JP2009301714A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory which makes its data reliability improve, by reducing the stress on the memory cell gates due to a high voltage applied to the word lines at writing. <P>SOLUTION: In an electrically rewritable nonvolatile memory having a configuration of a number of I/Os, each arbitrary number of I/Os are divided into a number of I/O groups, and the word lines are divided into groups of the same number as the divided I/O groups, each having a word line driver; and at reading, all the word lines of the I/O groups are selected to read data; and when programming, a high voltage is selectively applied to the word lines of one or more I/O groups. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention generally relates to a semiconductor memory device, and more particularly to a page mode memory capable of accessing a plurality of pages at high speed.

  There is a page mode memory as a memory that realizes high-speed data reading / writing with respect to the memory cell array. In page mode memory, multiple pages can be read simultaneously in a single read operation and stored in the sense amplifier, and data can be read at high speed by selecting a page by external addressing. it can. If it is within a plurality of pages read at a time, it is sufficient to read data from the sense amplifier instead of accessing the memory cell array and reading data each time a page is designated. Accordingly, the time from addressing to data reading is shortened, and high-speed data reading can be realized.

  FIG. 1 shows a configuration of a conventional page mode memory.

  The memory cell array 10 is divided into four pages Page0 to Page3 in units of pages, and further divided into portions corresponding to the input / output terminals in each page. For example, the input / output terminal I / O 0 is connected to the corresponding memory cell array portion in each page via the corresponding input / output buffer 11 and the sense amplifier 12. The same applies to the other input / output terminals, and each input / output terminal is connected to all of the four pages Page0 to Page3.

  At the time of data reading, all the data of the four pages Page0 to Page3 is called to the sense amplifier 12, and the switch 13 corresponding to the selected page is turned on to read the data of this page to the outside of the memory.

  At the time of data writing, a write operation is performed by designating data to be written with all input / output terminals corresponding to the selected address as a unit.

  In the configuration of FIG. 1, the input / output buffer 11 is connected to a corresponding sense amplifier 12 via a signal line 14. Since each input / output terminal needs to be connected to all pages, the signal line 14 is routed a long distance corresponding to the physical expansion of the memory cell array corresponding to the four pages Page0 to Page3. become.

  Accordingly, the wiring resistance and capacitance of the signal line 14 are increased, and the signal delay is also increased. This slows down the data read / write operation and hinders the speeding up of the memory.

  In the conventional technique, as shown in FIG. 1, since each page block has an I / O, when writing, all pages must be written. Since the actual write operation is performed for each I / O, the word line of each page is in a selected state and a high voltage is applied until the writing of all the I / O is completed. The data will be adversely affected due to stress.

  In an electrically rewritable nonvolatile memory having a plurality of I / O configurations, a plurality of I / Os are divided into a plurality of I / O groups every arbitrary number, and word lines are divided into I / O groups And each word line driver is selected, all I / O word lines are selected when reading, I / O data is read, and one or more I / O groups are programmed A high voltage is selectively applied to the minute word line.

  According to at least one embodiment of the present disclosure, it is possible to reduce the stress applied to the gate of the memory cell due to the application of a high voltage to the word line during a write operation, and to improve data reliability.

It is a figure which shows the structure of the conventional page mode memory. It is a figure which shows the structure of the semiconductor memory device by this invention. FIG. 3 is a diagram showing an erase unit for erasing data when the configuration of FIG. 2 is applied to a flash memory. It is a figure which shows the Example of the semiconductor memory device by this invention. It is a block diagram which shows the memory cell arrangement | sequence and the part of a Y selection gate in detail. FIG. 3 is a block diagram showing a configuration for erasing data in units of a plurality of blocks in a flash memory. 2 is a block diagram showing a configuration for writing data in a plurality of block units in a flash memory. FIG. It is the chart which showed the timing of each signal at the time of writing of a prior art. It is the chart which showed the timing of each signal at the time of writing by this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a diagram showing a configuration of a semiconductor memory device according to the present invention.

  In the semiconductor memory device of FIG. 2, the memory cell array 20 is divided into blocks corresponding to input / output terminals, and further divided into a plurality of pages within each block. In the example of FIG. 2, the number of pages is 4, and each block is divided into pages Page 0 to Page 3. Hereinafter, unless otherwise specified, the term “block” refers to a block corresponding to each input / output terminal.

  For example, the input / output terminal I / O 0 is connected to all the page portions in the corresponding block via the corresponding input / output buffer 21 and the sense amplifier 22. The same applies to the other input / output terminals, and each input / output terminal is connected to all four pages Page0 to Page3 in the corresponding block.

  At the time of data reading, all the data of the four pages Page0 to Page3 is called to the sense amplifier 22, and the switch 23 corresponding to the selected page is turned on to read the data of this page to the outside of the memory.

  In the configuration of FIG. 2, the signal line 24 has a wiring length corresponding to the physical expansion of the block because the input / output terminals need only be connected to the block corresponding to each input / output terminal of the memory cell array 20. If you do it, it is enough. That is, the wiring length can be greatly shortened as compared with the configuration of FIG. 1, and the wiring resistance and capacitance of the signal line can be reduced. Therefore, the semiconductor memory device according to the present invention can operate at high speed by reducing the wiring resistance and capacitance of the signal line in the device input / output portion.

  FIG. 3 is a diagram showing an erase unit for erasing data when the configuration of FIG. 2 is applied to a flash memory.

  In the configuration of the prior art as shown in FIG. 1, erasing is performed in units of pages. That is, each page of pages Page 0 to Page 3 is erased one page at a time, and all pages are erased by four erase operations. On the other hand, in the configuration of FIG. 2, erasing is sequentially performed using four blocks as one erasing unit, and all blocks are erased by four erasing operations. Such an erase operation will be described in detail later.

  FIG. 4 is a diagram showing an embodiment of a semiconductor memory device according to the present invention. In the embodiment described below, a flash memory will be described as an example. However, the signal line wiring and the like shown in FIG. 2 are not particularly limited to the flash memory. In FIG. 4, the same elements as those in FIG. 2 are referred to by the same numerals.

  In FIG. 4, the memory cell array 20 is connected to the sense amplifier 22 via the Y selection gate 30. Further, the sense amplifier 22 is connected to the input / output buffer 21 via an NMOS transistor 23 that functions as a switch.

  At the time of data reading, data at a specified address in each page is read from the memory cell array 20 and stored in the sense amplifier 22. By setting one of the switch signals PA0 to PA3 to HIGH, the corresponding NMOS transistor 23 is turned on. Accordingly, one of the four sense amplifiers 22 corresponding to the four pages is selected, and the data of the selected sense amplifier 22 is read out to the outside of the apparatus via the input / output buffer 21. .

  The signal lines 24 connecting the input / output buffers 21 and the sense amplifiers 22 need only be connected to each of the four sense amplifiers 22 that form a set corresponding to the four pages Page0 to Page3. It suffices to have a wiring length corresponding to the physical expansion of the pair of sense amplifiers 22. That is, it is possible to operate at high speed by reducing the wiring resistance and capacitance of the signal lines in the device input / output portion.

  FIG. 5 is a block diagram showing in detail the memory cell array 20 and the Y selection gate 30.

  In FIG. 5, the memory cell array 20 includes memory cells MC, word lines WL0 to WL512, a source line 41, and a bit line 42. When one of the word lines WL0 to WL512 is selected and activated, the stored data appears on the bit line 42 depending on whether the memory cell MC is in the program state or the erase state. That is, when the memory cell MC is in the erased state, the bit line 42 is connected to the source line 41 via the memory cell MC, and the potential of the bit line 42 is dropped to the ground voltage. When the memory cell MC is in the programmed state, the bit line 42 is not connected to the source line 41 and is pulled up to the HIGH state by the sense amplifier 22.

  One of the data appearing on the bit line 42 is selected by the Y selection gate 30. The Y selection gate 30 includes a plurality of NMOS transistors 31. Address signals YD0-0 to YD2-1 are supplied to the gate of the NMOS transistor 31. By setting this address signal, an appropriate NMOS transistor 31 is turned on, and one of the plurality of bit lines 42 is selected and connected to the sense amplifier 22.

  When erasing data, the source line 41 is set to a high potential of, for example, 5V, and the gate voltage (word line potential) is set to a low potential of, for example, about −9V. Thereby, the data in the memory cell MC can be erased.

  FIG. 5 shows a configuration for one page corresponding to one sense amplifier 22. For example, when the whole is composed of four pages, four configurations of FIG. 5 are provided for each input / output buffer. become.

  FIG. 6 is a block diagram showing a configuration for erasing data in units of a plurality of blocks in the flash memory according to the embodiment of the present invention.

  In the memory erasure control, as shown in FIG. 6, the memory cell array 20 is controlled by being divided into 4n local erase blocks B00 to Bn3. Here, one local erase block corresponds to one erasing unit shown in FIG.

  The address buffer 53 is a buffer that holds an address for designating the local erase block to be erased in the column direction and the row direction. The erase control circuit 52 controls the erase operation for the local erase block specified by the address of the address buffer 53. The erase circuit 51 executes an actual erase operation on the local erase block under the control of the erase control circuit 52. The sense amplifier control circuit 54 controls the operation of the sense amplifier 22 and is not a circuit directly related to the erase operation of the memory cell array 20.

  Each local erase block includes a plurality of I / O blocks (the blocks shown in FIG. 2 corresponding to each I / O), and an erasing operation for these plurality is executed as a unit. In a flash memory, a voltage necessary for an erasing operation is generated inside a memory device using a pump circuit. When the area of the memory cell array 20 to be erased becomes large, the current consumption of the erase operation exceeds the capacity of the pump. Therefore, the erase operation is performed with a predetermined size corresponding to the capacity of the pump as one unit. In the example of FIG. 6, one unit of the erase operation is a local erase block.

  When erasing data, the local erase blocks are erased one by one, and for example, the local erase blocks B00 to B03 are erased by a series of erase operations. That is, the local erase block B00 is erased first, the address in the column direction is incremented by one, the local erase block B01 is erased, the local erase block B02 is erased, and finally the local erase block Bn3 is erased.

  In this way, all pages Page0 to Page3 can be erased for data corresponding to all input / output terminals (I / O0 to I / O15 in FIG. 4).

  When writing data, the bit line is set to a high voltage of about 6V, and the gate voltage (word line potential) is set to a high potential of about 9V.

  In the conventional technique, as shown in FIG. 1, since each page block has an I / O, when writing, all pages must be written. Since the actual write operation is performed for each I / O, the word line of each page is in a selected state and a high voltage is applied until the writing of all the I / O is completed. The data will be adversely affected due to stress. FIG. 8 shows this state in a timing chart. While the write operation is being executed, the PGMS signal is HIGH. First, verify (PGMV) is executed to check the write state, and then write (PGM) is actually executed when writing is necessary. During this period, a high voltage is applied to the word line (WL) as shown in the figure.

  In FIG. 7, which is an embodiment of this patent, the write operation is performed in units of local blocks, that is, a plurality of I / O groups as in the same manner as the erase operation. Since each local block has a driver (Xdec) for controlling the word line, a high voltage is applied only to this word line (WL0) when the local block in which writing is performed, for example, B00 is selected. When applied, the word lines (WL1, WL2, WL3) of other local blocks can be set to the ground voltage VSS, thereby reducing the stress applied to the gate of the memory cell. FIG. 9 shows this state in the timing chart.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

In addition, this invention includes the invention attached to the following.
(Appendix 1)
A plurality of input / output terminals, a memory cell array composed of blocks corresponding to each of the plurality of input / output terminals, and a plurality of memory cells arranged adjacent to each of the blocks, and sense data in the memory cell array A sense amplifier, a plurality of switches corresponding to the plurality of sense amplifiers, and a signal wiring that connects the plurality of sense amplifiers to a corresponding one of the plurality of input / output terminals via the plurality of switches. A semiconductor memory device.
(Appendix 2)
The supplementary note 1, wherein one of the plurality of switches is selectively turned on in accordance with an input address to select one page from a plurality of pages corresponding to the plurality of sense amplifiers and read data. Semiconductor memory device.
(Appendix 3)
The semiconductor memory device according to appendix 1, wherein the memory cell array includes flash memory cells.
(Appendix 4)
4. The semiconductor memory device according to appendix 3, wherein data erasure of the memory cell array is sequentially executed for each erase unit by combining a plurality of blocks as one erase unit.
(Appendix 5)
A semiconductor memory device that simultaneously reads out data for a plurality of pages from a memory cell array, stores the data in a plurality of sense amplifiers, and reads out data of a selected page from the selected sense amplifier. Memory cell regions corresponding to the plurality of pages are arranged adjacent to each other in the memory cell array, and the plurality of sense amplifiers are arranged adjacent to each other for the one input / output terminal. A semiconductor memory device comprising a wiring for connecting the plurality of sense amplifiers provided for an output terminal to the one input / output terminal.
(Supplementary note 6) The semiconductor memory device according to supplementary note 5, wherein the memory cell array includes flash memory cells.
(Appendix 7)
7. The semiconductor memory device according to appendix 6, wherein data erasure of the memory cell array is sequentially executed for each erase unit by grouping the memory cell regions corresponding to a plurality of input / output terminals as one erase unit.
(Appendix 8)
A semiconductor memory device that simultaneously reads out data for a plurality of pages from a memory cell array, stores the data in a plurality of sense amplifiers, and reads out data of a selected page from the selected sense amplifier. 2. A semiconductor memory device, wherein memory cell regions corresponding to the plurality of pages are arranged adjacent to each other in the memory cell array.
(Appendix 9)
A semiconductor memory device that simultaneously reads out data for a plurality of pages from a memory cell array, stores the data in a plurality of sense amplifiers, and reads out data of a selected page from the selected sense amplifier. A semiconductor memory comprising: a plurality of sense amplifiers arranged adjacent to each other, and a wiring for connecting the plurality of sense amplifiers provided for the one input / output terminal to the one input / output terminal. apparatus.
(Appendix 10)
In an electrically rewritable nonvolatile memory having a plurality of I / O configurations, a plurality of I / Os are divided into a plurality of I / O groups every arbitrary number, and word lines are divided into I / O groups And each word line driver is selected, all I / O word lines are selected when reading, I / O data is read, and one or more I / O groups are programmed A semiconductor memory device, wherein a high voltage is selectively applied to a minute word line.
(Appendix 11)
11. The semiconductor memory device according to appendix 10, wherein programming is performed for each I / O group until programming is performed for all I / O.
(Appendix 12)
12. The semiconductor memory device according to appendix 11, wherein a program sequencer is provided, and when programming data for I / O, the sequencer automatically performs programming for each I / O group internally.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

10 memory cell array 11 input / output buffer 12 sense amplifier 13 switch 14 signal line 20 memory cell array 21 input / output buffer 22 sense amplifier 23 switch 24 signal line 51 erase circuit 52 erase control circuit 53 address buffer

Claims (1)

  In an electrically rewritable nonvolatile memory having a plurality of I / O configurations, a plurality of I / Os are divided into a plurality of I / O groups every arbitrary number, and word lines are divided into I / O groups And each word line driver is selected, all I / O word lines are selected when reading, I / O data is read, and one or more I / O groups are programmed A semiconductor memory device, wherein a high voltage is selectively applied to a minute word line.

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