JP2009295941A - Storage element and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve user-friendliness of a memory element regarding a storage element and a method of manufacturing the same. <P>SOLUTION: In the memory element with a first electrode 22, a second electrode, and an oxide semiconductor layer 24 formed by calcium praseodymium manganate on the first electrode, a metal oxide layer 26 is provided between the second electrode 28 and the oxide semiconductor layer 24. Thus, information is stored without foaming and the user-friendliness when the memory element 20 is used is improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory element and a method for manufacturing the same, and more particularly, a first electrode, a second electrode, and an oxide semiconductor layer formed of an oxide semiconductor interposed between the first electrode and the second electrode. And a first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying a positive first voltage to the second electrode using the first electrode as a reference voltage, A state of electrical resistance generated between the first electrode and the second electrode by applying a negative second voltage to the second electrode using the first electrode as a reference voltage, and is different from the first resistance state. The present invention relates to a memory element that stores information using a resistance state and a manufacturing method thereof.

Conventionally, as this type of memory element, an upper electrode made of aluminum, a lower electrode made of gold, and a calcium praseodymium manganate (Pr _0.7 Ca _0.3 MnO ₃₎ interposed between the upper electrode and the lower electrode. ) Has been proposed (for example, see Non-Patent Document 1). In this memory element, when the lower electrode is set to 0V and + 5V is applied to the upper electrode, the electrical resistance state between the lower electrode and the upper electrode becomes a high resistance state having a high resistance value, and when −5V is applied to the upper electrode. The electrical resistance state between the lower electrode and the upper electrode becomes a low resistance state with a low resistance value, and information can be stored using the change in the resistance state.
Kenta Tsubouti et al., “High-Thoroughput Characterization of Metal Electrode Performance for Electric-Field-Induced Resistance Switching in Metal / Pr0.7Ca0.3MnO3 / Metal Structures”, WILEY-VCH Verlag GmbH and Co. KGaA, Advanced Materials (Advansed Materiarls), May 30, 2007, No. 19, p. 1711-1713

  In the memory element described above, when a voltage increasing from 0 V is applied to the upper electrode, a phenomenon called “forming” occurs in which the current between the lower electrode and the upper electrode rapidly decreases when the voltage of the upper electrode is +4 V. It is known that the change in the resistance state described above occurs only after such forming. In other words, in the above-mentioned memory element, after being manufactured in a factory or the like, information cannot be stored unless a forming is caused by applying a voltage of +4 V or higher to the upper electrode before use, and the usability is always satisfactory. It is not. Therefore, a memory element in which the resistance state changes without performing such forming is desirable.

  A memory element and a manufacturing method thereof according to the present invention include an oxide semiconductor layer formed of an oxide semiconductor interposed between a first electrode and a second electrode, and the first electrode serves as a reference voltage and is positively connected to the second electrode. A first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying the first voltage, and a negative second voltage applied to the second electrode using the first electrode as a reference voltage. Used in a memory element that stores information using a second resistance state different from the first resistance state, which is an electrical resistance state generated between the first electrode and the second electrode by applying The main purpose is to improve usability.

  The memory element and the manufacturing method thereof according to the present invention adopt the following means in order to achieve the main object described above.

The memory element of the present invention is
A first electrode; a second electrode; and an oxide semiconductor layer formed of an oxide semiconductor interposed between the first electrode and the second electrode, wherein the first electrode is used as a reference voltage. A first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying a positive first voltage to the second electrode, and the first electrode as a reference voltage A second resistance state different from the first resistance state in an electrical resistance state generated between the first electrode and the second electrode by applying a negative second voltage to the second electrode; A storage element for storing information using
A metal oxide layer interposed between one of the first electrode and the second electrode and the oxide semiconductor layer and formed thinner than the oxide semiconductor layer by a metal oxide having a predetermined insulation performance It is characterized by providing.

In this memory element of the present invention, a metal oxide formed thinner than an oxide semiconductor layer by a metal oxide having a predetermined insulating performance between one of the first electrode and the second electrode and the oxide semiconductor layer By interposing the layer, the first resistance state or the second resistance state is generated by adjusting the voltage applied to the second electrode without forming, and information can be stored. Thereby, the usability at the time of using can be improved. Here, the “metal oxide having a predetermined insulation performance” may be a metal oxide having an electrical resistivity of 1 × 10 ¹⁰ Ω · m or more.

In the memory element of the present invention in which the metal oxide layer is formed of a metal oxide having an electrical resistivity of 1 × 10 ¹⁰ Ω · m or more, the second electrode is shot when brought into contact with the oxide semiconductor. It may be formed of a Schottky metal that forms a key contact, and the metal oxide layer may be formed so as to be interposed between the second electrode and the oxide semiconductor layer. In this way, information can be stored more appropriately. In this case, the oxide semiconductor layer may be formed of an oxide semiconductor having a p-type conductivity. In the memory element of the present invention in which the oxide semiconductor layer is formed of an oxide semiconductor having a p-type conductivity, the oxide semiconductor layer is formed of calcium praseodymium manganate, and the second electrode Is formed of any one of aluminum, tin, iron, and manganese, and the metal oxide layer is formed of an oxide of the second electrode, or the oxide semiconductor layer is formed of nickel oxide. The second electrode may be formed of aluminum, titanium, or tin, and the metal oxide layer may be formed of an oxide of the second electrode. it can. Further, the second electrode is formed of a Schottky metal that forms a Schottky contact with the oxide semiconductor, and the metal oxide layer is interposed between the second electrode and the oxide semiconductor layer. In the memory element of the present invention, the oxide semiconductor layer may be formed of an oxide semiconductor having an n-type conductivity. In the memory element of the present invention in which the oxide semiconductor layer is formed of an n-type oxide semiconductor, the oxide semiconductor layer is formed of titanium oxide or strontium titanate. The two electrodes are formed of aluminum or titanium, and the metal oxide layer is formed of any of aluminum oxide, titanium oxide, strontium titanate, manganese oxide, iron oxide, cobalt oxide, and tin oxide. The oxide semiconductor layer is formed of titanium oxide or strontium titanate, and the second electrode is formed of any of nickel, tin, manganese, iron, and cobalt, and the metal oxide The layer may be formed of an oxide of the second electrode.

In the memory element of the present invention in which the metal oxide layer is formed of a metal oxide having an electrical resistivity of 1 × 10 ¹⁰ Ω · m or more, the second electrode is ohmic when brought into contact with the oxide semiconductor. The metal oxide layer may be formed so as to be interposed between the second electrode and the oxide semiconductor layer. In this case, the oxide semiconductor layer is made of calcium praseodymium manganate, the second electrode is made of gold, and the metal oxide layer is made of aluminum oxide. You can also

The first method for manufacturing a memory element of the present invention is as follows.
A first electrode; a second electrode; and an oxide semiconductor layer formed of an oxide semiconductor interposed between the first electrode and the second electrode, wherein the first electrode is used as a reference voltage. A first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying a positive first voltage to the second electrode, and the first electrode as a reference voltage A second resistance state different from the first resistance state in an electrical resistance state generated between the first electrode and the second electrode by applying a negative second voltage to the second electrode; A method of manufacturing a storage element that stores information using
Forming a first electrode by depositing a first metal on a substrate; and
The oxide semiconductor layer is deposited on the formed first electrode and a metal oxide having an electric resistivity of 1 × 10 ¹⁰ Ω · m or more is deposited thinner than the oxide semiconductor, An oxide semiconductor layer forming a metal oxide layer formed of the metal oxide, and a metal oxide layer forming step;
A second electrode forming step of forming the second electrode by evaporating a second metal different from the first metal on the formed metal oxide layer;
It is a summary to provide.

In the first method for manufacturing a memory element according to the present invention, a first metal is deposited on a substrate to form a first electrode, an oxide semiconductor is deposited on the formed first electrode, and an electrical resistivity is obtained. Is formed by depositing a metal oxide having a thickness of 1 × 10 ¹⁰ Ω · m or more thinner than an oxide semiconductor to form an oxide semiconductor layer and a metal oxide layer formed of the metal oxide. A second electrode is formed by evaporating a second metal different from the first metal on the layer. Thus, a memory element including a metal oxide layer interposed between the oxide semiconductor layer and the second electrode can be formed.

The second method for manufacturing a memory element of the present invention is as follows.
A first electrode; a second electrode; and an oxide semiconductor layer formed of an oxide semiconductor interposed between the first electrode and the second electrode, wherein the first electrode is used as a reference voltage. A first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying a positive first voltage to the second electrode, and the first electrode as a reference voltage A second resistance state different from the first resistance state in an electrical resistance state generated between the first electrode and the second electrode by applying a negative second voltage to the second electrode; A method of manufacturing a storage element that stores information using
Forming a first electrode by depositing a first metal on a substrate; and
An oxide semiconductor layer forming step of forming the oxide semiconductor layer by depositing the oxide semiconductor on the formed first electrode;
A second metal that is different from the first metal on the formed oxide semiconductor layer and has an oxygen diffusion coefficient of 1 × 10 ⁻¹⁵ cm ² / sec or more in the oxide of the metal From a metal oxide having an electrical resistivity of 1 × 10 ¹⁰ Ω · m or more between the oxide semiconductor layer and the second electrode together with the second electrode formed of the second metal by vapor deposition A second electrode metal oxide layer forming step for forming the formed metal oxide layer;
It is a summary to provide.

In the second method for manufacturing a memory element of the present invention, a first metal is deposited on a substrate to form the first electrode, and the oxide semiconductor is deposited on the formed first electrode. An oxide semiconductor layer is formed, and a diffusion coefficient of oxygen in the metal oxide which is different from the first metal on the formed oxide semiconductor layer is 1 × 10 ⁻¹⁵ cm ² / sec or more. Metal oxide having an electrical resistivity of 1 × 10 ¹⁰ Ω · m or more between the oxide semiconductor layer and the second electrode together with the second electrode formed by vapor deposition of the second metal A metal oxide layer formed from a material is formed. Since the metal oxide is formed between the oxide semiconductor layer and the second electrode together with the second electrode, the memory element includes the metal oxide layer interposed between the oxide semiconductor layer and the second electrode in fewer steps Can be formed.

  Next, the best mode for carrying out the present invention will be described using examples.

FIG. 1 is a block diagram showing an outline of the configuration of a memory element 20 as a first embodiment of the present invention. The memory element 20 includes a first electrode 22 formed on a substrate 10 made of lanthanum aluminate (LaAlO ₃ ), an oxide semiconductor layer 24 formed on the first electrode 22, and an oxide semiconductor layer 24. A metal oxide layer 26 formed of a high metal oxide and a second electrode 28 formed on the metal oxide layer 26 are provided. The substrate 10 is made of lanthanum aluminate. However, the substrate 10 only needs to be made of a material having a high electrical resistivity such that the current flowing through the substrate 10 can be ignored, and the electrical resistivity is 10 ^10. It is desirable to be formed of a material larger than Ω · m.

The oxide semiconductor layer 24 is a p-type oxide semiconductor calcium praseodymium manganate (Pr _1−x Ca _x MnO ₃ , x is 0.3 to 0.5, and in the embodiment, x is 0.3. PCMO) to a thickness of 80 nm.

  The first electrode 22 is formed to a thickness of 20 nm with lanthanum nickelate (LaNiO, hereinafter referred to as LNO) having good lattice constant matching with PCMO for forming the oxide semiconductor layer 24 and having good electrical conductivity. Has been. The first electrode 22 only needs to be formed of a material having a low electrical resistivity, and is preferably formed of a material having an electrical resistivity of less than 10 −4 Ω · m. The first electrode 22 includes a connection electrode 30 formed of silver (Ag) and electrically connected to the first electrode 22, and a voltage is applied through the connection electrode 30.

  The second electrode 28 is a metal that generates a Schottky contact in which the height φBP of the Schottky barrier calculated by the following equation (1) generated when contacting the PCMO that forms the oxide semiconductor layer 24 is greater than 0. In the embodiment, it is formed of aluminum (Al). In equation (1), Eg represents the band gap of PCMO, q represents the elementary charge, χ represents the electron affinity of PCMO, and φm represents the work function of aluminum.

  φBP = Eg / q + χ-φm (1)

The metal oxide layer 26 is formed to a thickness of 3 nm from aluminum oxide (AlO _x , x is a real number greater than 0), which is an oxide of aluminum as the material of the second electrode 28. The metal oxide layer 26 only needs to be formed of a material having high insulating performance, that is, a material having high electric resistivity, and is preferably formed of a material having an electric resistivity of greater than 10 ¹⁰ Ω · m.

Next, a method for manufacturing the memory element 20 configured as described above will be described. FIG. 2 is a flowchart showing an outline of the manufacturing process of the memory element 20. First, the growth temperature (the temperature of the substrate 10) is 700 ° C. and the oxygen partial pressure is 3.99 Pa by a pulse laser deposition method (hereinafter referred to as PLD method) using a KrF excimer laser with an intensity of 0.7 mJ / cm ² and a frequency of 1 Hz. The first electrode 22 is formed by depositing LNO with a thickness of 20 nm (step S100).

After the first electrode 22 is formed, the growth temperature (the temperature of the substrate 10) is set to 700 ° C. on the formed first electrode 22 by a PLD method using a KrF excimer laser with an intensity of 0.7 mJ / cm ² and a frequency of 5 Hz. A PCMO layer with a partial pressure of 3.99 Pa is deposited to form a PCMO layer (step S110), and a KrF excimer laser with an intensity of 1.5 mJ / cm ² and a frequency of 1 Hz is formed on the PCMO layer thus formed. The growth temperature (the temperature of the substrate 10) is room temperature (about 20 ° C.), the oxygen partial pressure is 1.33 × 10 Pa, and the thickness is 3 nm with AlO _x (x is Al: O = 3: 1 to 1). (A real number satisfying 1: 0.7) is deposited to form an aluminum oxide layer (step S120), and the aluminum oxide layer and a part of the PCMO layer are sequentially etched by ion milling. The first electrode 22 is partially exposed to form a metal oxide layer 26 made of aluminum oxide and an oxide semiconductor layer 24 made of PCMO (step S130). In the embodiment, after the first electrode 22 is formed, PCMO and aluminum oxide are sequentially deposited on the first electrode 22 to form a PCMO layer and an aluminum oxide layer, and then the PCMO layer and the aluminum oxide are formed by ion milling. The metal oxide layer 26 and the oxide semiconductor layer 24 are formed by sequentially etching a part of the layer. After the first electrode 22 is formed, a part of the first electrode is masked with a metal to form PCMO. After the metal and aluminum oxide are sequentially deposited, the metal oxide layer 26 and the oxide semiconductor layer 24 may be formed by removing the metal used for the mask.

  Subsequently, Al is deposited on the formed metal oxide layer 26 by vacuum deposition, and then the deposited Al layer is patterned to form the second electrode 28 (step S140), and then the first electrode 22 is formed. After depositing Ag by a vacuum evaporation method on the exposed part of the film, the deposited Ag layer is patterned to form the connection electrode 30 (step S150). Thus, by forming the first electrode 22, the oxide semiconductor layer 24, and the metal oxide layer 26 using the PLD method, the surface of the first electrode 22, the oxide semiconductor layer 24, and the metal oxide layer 26 is a molecular layer. It can be formed flat at the level. In the embodiment, the first electrode 22, the oxide semiconductor layer 24, and the metal oxide layer 26 are formed by the PLD method. However, for example, a method of forming another thin film such as a CVD (Chemical Vapor Deposition) method. Any method may be used as long as it is formed.

  The operation of the memory element 20 configured in this way will be described. In FIG. 3, after manufacturing the memory element, first, the first electrode 22 is grounded (0 V) via the connection electrode 30 and the voltage Vc of the second electrode 28 is changed to change the first electrode 22 and the second electrode. It is explanatory drawing which shows an example of the measurement result which measured absolute value | Ic | of the electrode current Ic which flows between electrodes. As shown in the figure, when the voltage Vc is set to +6 V, the resistance Rc between the first electrode 22 and the second electrode 28 is increased, and when the voltage Vc is lowered, the high resistance state is obtained. When the voltage Vc becomes −6V, the resistance Rc becomes low, and the low resistance state is maintained. When the voltage Vc becomes 0V, the low resistance state is maintained until the voltage Vc becomes 0V. Therefore, in the memory element 20, information can be stored by setting the voltage Vc to + 6V or −6V and setting the memory element 20 to a high resistance state or a low resistance state, and the voltage Vc is a voltage between −6V and 0V ( For example, the stored information can be read by detecting the interelectrode current Ic as −4V). That is, the memory element 20 functions as a nonvolatile memory. FIG. 4 shows that after applying a pulse having an amplitude of + 6V (pulse voltage is 0V to + 6V) to the voltage Vc five times, a pulse having an amplitude of -6V (pulse voltage is -6V to 0V) is applied five times. It is explanatory drawing which shows an example of the measurement result of resistance Rc when it repeats. In the memory element 20 of the example, as shown in the figure, it can be seen that the resistance Rc is relatively stable with respect to the number of pulse applications, and the change in the resistance state occurs relatively stably. As described above, the memory element 20 can appropriately store information using the change in the resistance state.

  FIG. 5 illustrates an example of a measurement result of the interelectrode current Ic when the voltage Vc is changed in a conventional memory element having the same configuration as the memory element 20 except that the metal oxide layer 26 is not provided. FIG. In the conventional memory device, as shown in the figure, after the interelectrode voltage Vc is gradually increased from 0V to cause “forming” in which the current Ic rapidly decreases in the vicinity of + 3V, when the voltage Vc is increased to + 5V, the low resistance state is reached. Thus, when the voltage Vc is set to -5V, a high resistance state is obtained. In the memory element 20 of the embodiment, as illustrated in FIG. 3, the resistance state changes without causing the forming first. This is considered because the metal oxide layer 26 is interposed between the second electrode 28 and the oxide semiconductor layer 24. As described above, after the memory device 20 is manufactured in a factory or the like, it is not necessary to apply a positive voltage to the second electrode 28 so that forming occurs before use, and the usability is improved as compared with the conventional device. It has become.

  In the memory element 20 of the first embodiment described above, in the memory element 20 including the first electrode 22, the second electrode, and the oxide semiconductor layer 24 formed of calcium praseodymium manganate on the first electrode 22. Since the metal oxide layer 26 is provided between the second electrode 28 and the oxide semiconductor layer 24, information can be stored without forming. Thereby, the usability when using the memory element 20 can be improved.

In the memory element 20 of the first embodiment, the metal oxide layer 26 is formed to a thickness of 3 nm, but the thickness of the metal oxide layer 26 is preferably about 1 nm to 5 nm. FIG. 6 shows a measurement result of the interelectrode current Ic when the voltage Vc of the second electrode 28 is changed in a memory element having the same configuration as the memory element 20 except that the thickness of the metal oxide layer 26 is 1 nm. FIG. 7 is a diagram illustrating an example of the first electrode 22 when a pulse having an amplitude of −6V is applied to the second electrode 28 five times and then a pulse having an amplitude of −6V is applied five times. It is explanatory drawing which shows an example of the measurement result of resistance Rc between the 2nd electrodes. As shown in FIG. 6, a change in the resistance state is observed even when the thickness of the metal oxide layer 26 is 1 nm. As can be seen from a comparison between FIG. 4 and FIG. 7, the resistance ratio (Rh / Rl) of the resistance Rh in the high resistance state to the resistance Rl in the low resistance state indicates that the thickness of the metal oxide layer 26 is 3 nm. In this case, it is about 10 ³ , whereas it is as low as 70 when the thickness is 1 nm. Therefore, it is considered that the resistance ratio tends to decrease by reducing the thickness of the metal oxide layer 26.

In the memory element 20 of the first embodiment, the aluminum oxide layer (metal oxide layer 26) is formed under an oxygen partial pressure of 1.33 × 10 Pa. However, the oxygen partial pressure at the time of forming the aluminum oxide layer is not limited. Is not limited to 1.33 × 10 Pa, and is preferably set according to the characteristics required for the memory element 20, for example, less than 1.33 × 10 Pa. FIG. 8 is an explanatory diagram showing an example of a measurement result of the current Ic when the voltage Vc is changed when the oxygen partial pressure is 1.33 × 10 ⁻² Pa when forming the aluminum oxide layer. 9 shows a case where a pulse having an amplitude of + 7V is applied five times to the second electrode 28 when an oxygen partial pressure is 1.33 × 10 ⁻² Pa, and then a pulse having an amplitude of −7V is applied five times. FIG. 10 is an explanatory diagram showing an example of the measurement result of the resistance Rc, and FIG. 10 is an electrode when the voltage Vc is changed when the oxygen partial pressure is 1.33 × 10 ⁻⁴ Pa when forming the aluminum oxide layer. FIG. 11 is an explanatory diagram showing an example of the measurement result of the inter-current Ic. FIG. 11 shows a state in which a pulse having an amplitude of +5 V is applied five times to the second electrode 28 when the oxygen partial pressure is 1.33 × 10 ⁻⁴ Pa Resistance when repeating the application of 5 pulses of -5V amplitude Is an explanatory view showing an example of Rc measurements, FIG. 12, FIG. 4, FIG. 9 is an explanatory diagram showing a relationship between the oxygen partial pressure and the resistor Rc using the measurement results of FIG. 11. As illustrated in FIGS. 8 to 11, in the memory element, two resistance states are observed regardless of whether the oxygen partial pressure is 1.33 × 10 ⁻² Pa or 1.33 × 10 ⁻⁴ Pa. Therefore, although it can function as a non-volatile memory, as shown in FIG. 12, the resistance value Rl in the low resistance state does not change much even when the oxygen partial pressure is increased, whereas the resistance Rh in the high resistance state is The oxygen partial pressure tends to increase as the oxygen partial pressure increases. Since the proportion of oxygen contained in the aluminum oxide layer increases as the oxygen partial pressure increases, it is considered that the resistance of the aluminum oxide layer contributes to the resistance Rh in the high resistance state. Therefore, it is considered that the characteristic of the memory element 20 can be adjusted by appropriately adjusting the resistance value Rh in the high resistance state by appropriately adjusting the oxygen partial pressure when forming the aluminum oxide layer.

  Next, a memory element 120 as a second embodiment of the present invention will be described. The memory element 120 includes a point in which the second electrode 28 in the memory element 20 of the first embodiment is formed of tin (Sn) instead of aluminum, and the metal oxide layer 26 is replaced by tin oxide (SnOx, The structure is the same except that x is a real number greater than 0) and the thickness of the metal oxide layer 26 is about 0.4 nm to 500 nm. Here, in order to avoid redundant description, detailed description of the configuration of the memory element 120 is omitted. Tin, like aluminum, is a metal that forms a Schottky contact when contacted with PCMO.

  Subsequently, a method of manufacturing the memory device 120 configured as described above will be described. To avoid redundant description, the same steps as the method of manufacturing the memory device 20 illustrated in FIG. Are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 13 is a flowchart showing an outline of the manufacturing process of the memory element 120. In manufacturing the memory element 120, first, LNO having a thickness of 20 nm is deposited by the PLD method to form the first electrode 22 (step S100), and an 80 nm PCMO layer is formed on the first electrode 22 by the PLD method. (Step S110) A part of the PCMO layer is etched by ion milling to expose a part of the first electrode 22, and the oxide semiconductor layer 24 formed by PCMO is formed (Step S130B).

After the oxide semiconductor layer 24 is formed in this way, tin is deposited by a vacuum evaporation method to form an Sn layer and a metal oxide layer 26 made of tin oxide is formed between the oxide semiconductor layer 24 and then deposited. The second electrode 28 is formed by patterning the Sn layer using a predetermined mask (step S140B), and the connection electrode 30 is formed by vacuum deposition (step S150). Here, by depositing tin, the metal oxide layer 26 can be formed between the Sn layer (second electrode 28) and the oxide semiconductor layer 24 because the diffusion coefficient of oxygen in tin oxide is 500 ° C. Since it is relatively large at 2.6 × 10 ⁻⁸ cm ² / sec, by depositing Sn, oxygen in the oxide semiconductor layer 24 diffuses into the Sn layer to form a sufficiently thick metal oxide layer 26. It is thought that it is because it can do. On the other hand, in the memory element 20 of the first embodiment, the diffusion coefficient of oxygen in aluminum oxide is as small as 7.7 × 10 ⁻²² cm ² / sec at 500 ° C. on the PCMO layer (oxide semiconductor layer 24). Since a sufficient thickness of the metal oxide layer 26 cannot be formed even if aluminum is deposited on the substrate, a separate step of forming an aluminum oxide layer (metal oxide layer 26) on the PCMO layer is required. . As described above, in the memory element 120 of the second embodiment, the metal oxide layer 26 can be formed together with the deposition of the second electrode 28. Therefore, the memory element 120 can be formed with fewer steps.

  Next, the operation of the memory element 120 will be described. In FIG. 14, after manufacturing the memory element, first, the first electrode 22 is grounded (0 V) via the connection electrode 30, and the voltage Vc of the second electrode 28 is changed to change the first electrode 22 and the second electrode. FIG. 15 is an explanatory diagram showing an example of a measurement result obtained by measuring the interelectrode current Ic flowing between the voltage Vc and the voltage Vc. FIG. 15 shows five pulses of a −6 V amplitude after 5 pulses of a +6 V amplitude are applied to the voltage Vc. It is explanatory drawing which shows an example of the measurement result of resistance Rc between the 1st electrode 22 and the 2nd electrode 28 when applying repeatedly. As illustrated in FIG. 14, in the memory element 120, without forming, when the voltage Vc is set to + 5V, the resistance Rc is increased to a high resistance state. When the voltage Vc is decreased, the high resistance state is maintained. When the voltage Vc becomes -5V, the resistance Rc becomes low and the low resistance state is maintained. When the voltage Vc becomes low, the low resistance state is maintained until the voltage Vc becomes 0V, so that the nonvolatile memory can operate. ing. Further, as illustrated in FIG. 15, the number of times of writing also shows good characteristics. As described above, the memory element 120 does not need to be applied with a positive voltage to the second electrode 28 so that the forming occurs before use after being manufactured in a factory or the like, and the memory element 120 requires a forming in use. Compared to, the usability is improved.

  Since the memory element 120 of the second embodiment described above includes the metal oxide layer 26 formed of tin oxide between the second electrode 28 formed of tin and the oxide semiconductor layer 24, forming is performed. Information can be stored without. As a result, it is possible to improve the usability when used as compared with a conventional memory element that requires forming when used. In addition, by depositing tin having a relatively high oxygen diffusion coefficient on the oxide semiconductor layer 24, the metal oxide layer 26 can be formed together with the second electrode in the same process. The memory element 120 can be formed with fewer steps compared to forming the second electrode 28 with a relatively low metal.

In the memory device 120 of the second embodiment of the present invention, the second electrode 28 is formed of tin and the metal oxide layer 26 is formed of tin oxide which is an oxide of tin. When the metal to be formed is brought into contact with PCMO, it forms a Schottky contact and the oxygen diffusion coefficient in the metal oxide becomes 1 × 10 ⁻¹⁵ cm ² / sec or more, for example, iron (Fe, iron oxide) 2.1 × at 500 ° C. the diffusion coefficient of oxygen (FeO _x, x is a value 0 or a real number) in the ^{10 -15 cm 2 /sec~3.5×10 -15 cm 2} / sec) and manganese (Mn The second electrode 28 may be formed by, for example, a diffusion coefficient of oxygen in manganese oxide (MnO _x , x is a real number greater than or equal to 0) having a diffusion coefficient of 2.7 × 10 −9 cm ² / sec at 900 ° C. When the second electrode 28 is formed of iron, in the manufacturing method illustrated in FIG. 13, it is desirable to perform an annealing process for 20 minutes under a high vacuum at a temperature of 200 ° C. after the process of step S140B. In FIG. 16, when the annealing process is not performed, the first electrode 22 is grounded (0 V), and the voltage Vc of the second electrode 28 is changed to flow between the first electrode 22 and the second electrode 28. FIG. 17 is an explanatory diagram showing an example of a measurement result of measuring the current Ic. FIG. 17 shows the second electrode 28 connected to the first electrode 22 through the connection electrode 30 when annealing is performed. It is explanatory drawing which shows an example of the measurement result which measured the interelectrode current Ic which flows between the 1st electrode 22 and the 2nd electrode 28 by changing the voltage Vc. As illustrated in FIG. 17, the annealing process causes a change in the resistance state in which the memory element 20 can operate as a nonvolatile memory. This is presumably because the diffusion of oxygen in the oxide semiconductor layer 24 toward the second electrode 28 is promoted by the annealing treatment, and the formation of the metal oxide layer 26 is promoted. Further, when the second electrode 28 is formed of manganese, the second electrode 28 is formed by depositing manganese at a relatively low temperature of 180 ° C. to 300 ° C. in the process of step S140B of the manufacturing method of FIG. desirable.

  Next, a memory element 220 as a third embodiment of the present invention will be described. The memory element 220 is formed of gold (Au), which is a metal that forms an ohmic contact when the second electrode 28 in the memory element 20 of the first embodiment is brought into contact with PCMO instead of aluminum. The memory element 20 has the same configuration, and the manufacturing process is the same except that the second electrode 28 in the memory element 20 is formed of gold instead of aluminum. Here, in order to avoid redundant description, detailed description of the configuration of the memory element 220 is omitted.

  In FIG. 18, after manufacturing the memory element, first, the first electrode 22 is grounded (0 V) via the connection electrode 30, and the voltage Vc of the second electrode 28 is changed to change the first electrode 22 and the second electrode. FIG. 19 is an explanatory diagram showing an example of a measurement result obtained by measuring the interelectrode current Ic flowing between the voltage V and the voltage Vc. FIG. 19 shows five pulses of −5V amplitude after applying a pulse of + 5V amplitude to the voltage Vc five times. It is explanatory drawing which shows an example of the measurement result of resistance Rc between the 1st electrode 22 and the 2nd electrode 28 when applying repeatedly. As illustrated in FIG. 18, if the voltage Vc is set to +5 V without forming, the resistance Rc between the first electrode 22 and the second electrode 28 becomes high, and thus the voltage Vc is changed to the high resistance state. Even if the voltage Vc is lowered, the high resistance state is maintained. When the voltage Vc becomes -5V, the resistance Rc becomes low. When the voltage Vc becomes low, the low resistance state is maintained until the voltage Vc becomes 0V. It can operate as a memory. In addition, as illustrated in FIG. 19, the number of writing times also exhibits good characteristics. Such a change in the resistance state is shown in FIG. 20. In the memory element that does not include the metal oxide layer 26, the resistance state exhibits an ohmic characteristic regardless of the voltage Vc as shown in FIG. This is thought to be due to the provision of material layers. As described above, in the memory element 220, after being manufactured in a factory or the like, it is not necessary to apply a positive voltage to the second electrode 28 so that forming occurs before use, and a conventional element that requires forming when used is used. Compared to, the usability is improved.

  Since the memory element 220 of the third embodiment described above includes the metal oxide layer 26 formed of aluminum oxide between the second electrode 28 formed of gold and the oxide semiconductor layer 24, forming is performed. Information can be stored without. Thereby, compared with the memory element 20 which needs forming at the time of use, the usability at the time of using the memory element 20 can be improved more.

In the memory elements 20, 120, and 220 of the first to third embodiments, the oxide semiconductor layer 24 is formed by PCMO. For example, nickel oxide (NiO) or other p-type oxidation different from PCMO is used. It may be formed of a physical semiconductor. In this case, combinations of the material of the metal oxide layer 26 and the material of the second electrode 28 include aluminum and aluminum oxide, titanium and titanium oxide (TiO _x , x is a real number greater than 0), tin and tin oxide. Etc. are desirable.

In the memory elements 20, 120, and 220 of the first to third embodiments, the oxide semiconductor layer 24 is formed of a p-type oxide semiconductor. For example, titanium oxide (TiO ₂ ) or strontium titanate ( It may be formed of an n-type oxide semiconductor such as SrTiO ₃ ). In this case, it is desirable to form the second electrode 28 with a Schottky metal that forms a Schottky contact when the second electrode 28 is brought into contact with the oxide semiconductor that is the material of the oxide semiconductor layer 24. In this case, the second electrode 28 is made of aluminum or titanium, the metal oxide layer 26 is made of aluminum oxide (AlO _x , x is a real number greater than 0), and titanium oxide (TiO _x , x is , Strontium titanate (SrTiO _x , x is a real number greater than 0), manganese oxide (MnO _x , x is a real number greater than 0), iron oxide (FeO _x , x is It is desirable to form any one of a real number greater than 0), cobalt oxide (CoO _x , x is a real number greater than 0), and tin oxide (SnO _x , x is a real number greater than 0). Further, when the second electrode 28 is brought into contact with an oxide semiconductor that is a material of the oxide semiconductor layer 24, the Schottky metal that forms a Schottky contact is formed, and the metal oxide layer 26 is formed of an oxide of a Schottky metal. You can also In this case, the combination of the material of the second electrode 28 and the material of the metal oxide layer 26 includes nickel (Ni) and nickel oxide (NiO _x , x is a real number greater than 0), tin and tin oxide ( SnO _x , x is a real number greater than 0), manganese and manganese oxide (MnO _x , x is a real number greater than 0), iron and iron oxide (FeO _x , x is a real number greater than 0), cobalt And cobalt oxide (CoO _x , x is a real number greater than 0). When the oxide semiconductor layer 24 is formed of an n-type oxide semiconductor, the absolute value of the interelectrode current Ic flowing between the first electrode 22 and the second electrode 28 by changing the voltage Vc of the second electrode 28. When the value | Ic | is measured, it can be considered that the figure is symmetrical to that illustrated in FIG. That is, when the voltage Vc is set to a predetermined negative voltage (for example, −7 V), the resistance Rc between the first electrode 22 and the second electrode 28 is increased, and thus the voltage Vc is increased when the resistance is changed to the high resistance state. Even if it is raised, the high resistance state is maintained, and when the voltage Vc becomes a predetermined positive voltage (for example, + 7V), the resistance Rc becomes low, and the low resistance state is reached until the voltage Vc drops to 0V. The state is maintained, and it can operate as a nonvolatile memory.

  In the memory elements 20, 120, and 220 of the first to third embodiments, the first electrode 22 and the second electrode 28 are formed of different metals, but the first electrode 22 and the second electrode 28 are It may be formed of the same metal. In this case, the metal oxide layer 26 may be interposed between the second electrode 28 and the oxide semiconductor layer 24, or may be interposed between the first electrode 22 and the oxide semiconductor layer 24. Also good.

  In the memory elements 20, 120, and 220 of the first to third embodiments, the memory element is formed on the substrate 10. However, instead of the substrate 10, the thin film shape that is thinner than the substrate 10 is highly insulating. It is good also as what is formed on the insulating layer formed with the material.

  The best mode for carrying out the present invention has been described with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the gist of the present invention. Of course, it can be implemented in the form.

  The present invention can be used in the memory element manufacturing industry.

1 is a configuration diagram showing an outline of a configuration of a memory element 20 formed of lanthanum aluminate (LaAlO ₃ ) and formed on a substrate 10 as a first embodiment of the present invention. 4 is a flowchart showing an outline of a manufacturing process of the memory element 20. FIG. 6 is an explanatory diagram showing an example of a measurement result obtained by measuring the absolute value | Ic | of the interelectrode current Ic by changing the voltage Vc of the second electrode 28 after manufacturing the memory element 20; A result of measurement of the resistance Rc between the first electrode 22 and the second electrode 28 when applying a pulse having an amplitude of + 6V to the voltage Vc five times and then applying a pulse having an amplitude of −6V five times is repeated. It is explanatory drawing which shows an example. It is explanatory drawing which shows an example of the measurement result of the electric current Ic when changing the voltage Vc in the conventional memory element of the structure similar to the memory element 20 except the point which does not provide the metal oxide layer 26. FIG. The absolute value | Ic | of the interelectrode current Ic when the voltage Vc of the second electrode 28 is changed in the memory element having the same configuration as the memory element 20 except that the thickness of the oxide semiconductor layer 24 is 1 nm. It is explanatory drawing which shows an example of the measurement result. Measurement of resistance Rc between first electrode 22 and second electrode 28 when applying a pulse of amplitude of −6 V to the second electrode 28 five times and then applying a pulse of −6 V amplitude five times It is explanatory drawing which shows an example of a result. It is explanatory drawing which shows an example of the measurement result of the electric current Ic when changing the voltage Vc when oxygen partial pressure is 1.33 * 10 ^<-2 > Pa when forming an aluminum oxide layer. The first is when the application of the pulse of the amplitude of + 7V to the second electrode 28 when the oxygen partial pressure is 1.33 × 10 ⁻² Pa is applied five times and then the pulse of the amplitude of −7V is applied five times. It is explanatory drawing which shows an example of the measurement result of the resistance value between the electrode 22 and the 2nd electrode. It is explanatory drawing which shows an example of the measurement result of the electric current Ic when changing the voltage Vc when oxygen partial pressure is 1.33 * 10 <^-4> Pa when forming an aluminum oxide layer. When the oxygen partial pressure is 1.33 × 10 ⁻⁴ Pa and the pulse of + 5V amplitude is applied to the second electrode 28 five times and then the pulse of −5V amplitude is applied five times, It is explanatory drawing which shows an example of the measurement result of resistance Rc between the 1 electrode 22 and the 2nd electrode. It is explanatory drawing which shows the relationship between oxygen partial pressure and resistance Rc. It is a flowchart which shows the outline of the manufacturing process of the memory element 120 of 2nd Example. An explanatory view showing an example of a measurement result obtained by measuring the interelectrode current Ic flowing between the first electrode 22 and the second electrode 28 by first changing the voltage Vc of the second electrode 28 after manufacturing the memory element 120. It is. A result of measurement of the resistance Rc between the first electrode 22 and the second electrode 28 when applying a pulse having an amplitude of + 6V to the voltage Vc five times and then applying a pulse having an amplitude of −6V five times is repeated. It is explanatory drawing which shows an example. It is explanatory drawing which shows an example of the measurement result which measured the interelectrode current Ic which flows between the 1st electrode 22 and the 2nd electrode 28 by changing the voltage Vc of the 2nd electrode 28 when not performing an annealing process. The first electrode 22 is grounded (0 V) via the connection electrode 30 when the annealing process is performed, and the voltage Vc of the second electrode 28 is changed between the first electrode 22 and the second electrode 28. It is explanatory drawing which shows an example of the measurement result which measured the electric current Ic which flows. The first electrode 22 is grounded (0 V) via the connection electrode 30 and the voltage Vc of the second electrode 28 is changed to measure the interelectrode current Ic flowing between the first electrode 22 and the second electrode 28. It is explanatory drawing which shows an example of the measured result. The result of measurement of the resistance Rc between the first electrode 22 and the second electrode 28 when applying the pulse of the amplitude of + 5V to the voltage Vc five times and then applying the pulse of the amplitude of −5V five times is repeated. It is explanatory drawing which shows an example. It is explanatory drawing which shows an example of the measurement result of the electric current Ic when changing the voltage Vc in the conventional memory element of the structure similar to the memory element 220 except for not having the metal oxide layer 26.

Explanation of symbols

  10 substrate, 20, 120, 220 memory element, 22 first electrode, 24 oxide semiconductor layer, 26 metal oxide layer, 28 second electrode, 30 connection electrode.

Claims (13)

A first electrode; a second electrode; and an oxide semiconductor layer formed of an oxide semiconductor interposed between the first electrode and the second electrode, wherein the first electrode is used as a reference voltage. A first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying a positive first voltage to the second electrode, and the first electrode as a reference voltage A second resistance state different from the first resistance state in an electrical resistance state generated between the first electrode and the second electrode by applying a negative second voltage to the second electrode; A storage element for storing information using
A metal oxide layer interposed between one of the first electrode and the second electrode and the oxide semiconductor layer and formed thinner than the oxide semiconductor layer by a metal oxide having a predetermined insulation performance A memory element comprising: The memory element according to claim 1, wherein the metal oxide layer is formed of a metal oxide having an electrical resistivity of 1 × 10 ¹⁰ Ω · m or more. The memory element according to claim 2,
The second electrode is formed of a Schottky metal that forms a Schottky contact when brought into contact with the oxide semiconductor,
The memory element is formed by interposing the metal oxide layer between the second electrode and the oxide semiconductor layer.   The memory element according to claim 3, wherein the oxide semiconductor layer is formed of an oxide semiconductor having a p-type conductivity. The storage element according to claim 4,
The oxide semiconductor layer is formed of calcium praseodymium manganate,
The second electrode is formed of any one of aluminum, tin, iron, and manganese,
The memory element, wherein the metal oxide layer is formed of an oxide of the second electrode. The storage element according to claim 4,
The oxide semiconductor layer is made of nickel oxide,
The second electrode is made of aluminum, titanium, or tin,
The memory element, wherein the metal oxide layer is formed of an oxide of the second electrode.   The memory element according to claim 3, wherein the oxide semiconductor layer is formed of an n-type oxide semiconductor. The storage element according to claim 7,
The oxide semiconductor layer is made of titanium oxide or strontium titanate,
The second electrode is made of aluminum or titanium,
The metal oxide layer is formed of any one of aluminum oxide, titanium oxide, strontium titanate, manganese oxide, iron oxide, cobalt oxide, and tin oxide. The storage element according to claim 7,
The oxide semiconductor layer is made of titanium oxide or strontium titanate,
The second electrode is formed of any one of nickel, tin, manganese, iron, and cobalt,
The memory element, wherein the metal oxide layer is formed of an oxide of the second electrode. The memory element according to claim 2,
The second electrode is formed of a metal that forms an ohmic contact with the oxide semiconductor,
The memory element is formed by interposing the metal oxide layer between the second electrode and the oxide semiconductor layer. The storage element according to claim 10,
The oxide semiconductor layer is formed of calcium praseodymium manganate,
The second electrode is made of gold,
The memory element, wherein the metal oxide layer is formed of aluminum oxide. A first electrode; a second electrode; and an oxide semiconductor layer formed of an oxide semiconductor interposed between the first electrode and the second electrode, wherein the first electrode is used as a reference voltage. A first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying a positive first voltage to the second electrode, and the first electrode as a reference voltage A second resistance state different from the first resistance state in an electrical resistance state generated between the first electrode and the second electrode by applying a negative second voltage to the second electrode; A method of manufacturing a storage element that stores information using
Forming a first electrode by depositing a first metal on a substrate; and
The oxide semiconductor layer is deposited on the formed first electrode and a metal oxide having an electric resistivity of 1 × 10 ¹⁰ Ω · m or more is deposited thinner than the oxide semiconductor, An oxide semiconductor layer forming a metal oxide layer formed of the metal oxide, and a metal oxide layer forming step;
A second electrode forming step of forming the second electrode by evaporating a second metal different from the first metal on the formed metal oxide layer;
A method for manufacturing a memory element. A first electrode; a second electrode; and an oxide semiconductor layer formed of an oxide semiconductor interposed between the first electrode and the second electrode, wherein the first electrode is used as a reference voltage. A first resistance state as an electrical resistance state generated between the first electrode and the second electrode by applying a positive first voltage to the second electrode, and the first electrode as a reference voltage A second resistance state different from the first resistance state in an electrical resistance state generated between the first electrode and the second electrode by applying a negative second voltage to the second electrode; A method of manufacturing a storage element that stores information using
Forming a first electrode by depositing a first metal on a substrate; and
An oxide semiconductor layer forming step of forming the oxide semiconductor layer by depositing the oxide semiconductor on the formed first electrode;
A second metal that is different from the first metal on the formed oxide semiconductor layer and has an oxygen diffusion coefficient of 1 × 10 ⁻¹⁵ cm ² / sec or more in the oxide of the metal From a metal oxide having an electrical resistivity of 1 × 10 ¹⁰ Ω · m or more between the oxide semiconductor layer and the second electrode together with the second electrode formed of the second metal by vapor deposition A second electrode metal oxide layer forming step for forming the formed metal oxide layer;
A method for manufacturing a memory element.

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