JP2009295818A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly evaluate on-chip variation in characteristics of a MOSFET incorporated in an LSI. <P>SOLUTION: In a method of evaluating on-chip variations in characteristics of a MOSFET, in an LSI that incorporates a logic circuit using the MOSFET and a substrate bias control circuit for applying a substrate bias to the MOSFET; the median value and the mean value of the off-current of the MOSFET are monitored; and the ratio between the mean value and the median value is obtained to evaluate on-chip variation inside characteristics of the MOSFET. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit (LSI) and an evaluation method thereof, and more particularly to a system that suppresses variation in characteristics between chips in an LSI that performs substrate bias control, and an insulated gate field effect transistor (MOSFET) formed in the chip. The present invention relates to a system and method for evaluating characteristic variations, and is used for LSI in general and systems using the LSI.

  In recent LSIs, with the miniaturization of MOSFETs formed in the chip, it becomes difficult to suppress the characteristic variation, and the importance of the design considering the characteristic variation is increasing. In particular, in recent years, not only the characteristics variation between chips determined by the specifications of manufacturing equipment but also the characteristics variation (On-Chip Variation: OCV) in MOSFETs in the same chip has become apparent, and the importance of considering this has increased. ing.

  Conventionally, a technique for modulating the Vth of a MOSFET by controlling the substrate bias using the substrate bias effect that the threshold voltage (Vth) of the MOSFET has a dependency on the reverse substrate bias (| Vbs |) has attracted attention. Has been. In this case, the delay time of logic circuits such as ring oscillators in the LSI and the characteristics of MOSFET leakage current are monitored. However, since the substrate bias effect of Vth of the MOSFET shows a saturation tendency, the setting step of | Vbs | becomes rough in the conventional monitoring method of delay characteristics or leak characteristics.

  In addition, a technique is known that compensates for variations in characteristics between LSI chips by controlling the substrate bias. However, the in-chip characteristic variation (OCV) has a dependency on | Vbs |, and the OCV increases as the applied amount of | Vbs | increases. There is an upper limit of | Vbs | that can be suppressed. In other words, if the substrate bias is applied more than necessary, the function yield may be lowered in a large-capacity static random access memory (SRAM) or the like.

  Therefore, in view of the importance of considering the OCV, it is possible to suppress a decrease in the yield of the manufactured chip by adding a margin considering the OCV at the time of designing. However, setting an excessive margin causes an increase in chip area, power consumption, and design schedule. Therefore, it is necessary to set an appropriate margin and it is important to establish a method for evaluating OCV.

Patent Document 1 discloses a technique for evaluating and displaying variations in Vth of MOSFETs by evaluating characteristics of a plurality of MOSFETs.
Japanese Patent No. 3972076

  The present invention has been made to solve the above-described conventional problems, and it is possible to suppress the occurrence of a function failure by minimizing an increase in in-chip characteristic variation due to application of a substrate bias of a built-in MOSFET. An object is to provide a semiconductor integrated circuit.

  Another object of the present invention is to provide a semiconductor integrated circuit and an evaluation method for the semiconductor integrated circuit capable of accurately evaluating the in-chip characteristic variation of the built-in MOSFET.

  Still another object of the present invention is to increase the detection accuracy for monitoring the in-chip characteristic variation of the built-in MOSFET, and to perform the evaluation separately from the in-chip characteristic variation and the inter-chip characteristic variation. It is to provide a circuit and an evaluation method thereof.

  A semiconductor integrated circuit according to a first aspect of the present invention includes a logic circuit using a MOSFET, a first monitor circuit for monitoring variations in characteristics of the MOSFET in the LSI chip, a delay time of the logic circuit, and a leakage of the MOSFET. A second monitor circuit that monitors a current characteristic; and a substrate bias control circuit that applies a substrate bias controlled based on a monitoring result by the first monitor circuit and the second monitor circuit to the MOSFET. It is characterized by doing.

  A semiconductor integrated circuit according to a second aspect of the present invention includes a logic circuit using a MOSFET, a substrate bias control circuit for applying a substrate bias to the MOSFET, and an evaluation system for evaluating variations in characteristics of the MOSFET in the chip. And the evaluation system includes a median value detection circuit that monitors the median value of the off-state current of the MOSFET, and an average value detection circuit that monitors the average value of the off-state current of the MOSFET. By measuring the ratio between the average value and the median value of the MOSFET, the in-chip characteristic variation of the MOSFET is evaluated.

  A semiconductor integrated circuit according to a third aspect of the present invention includes a logic circuit using a MOSFET, a substrate bias control circuit for applying a substrate bias to the MOSFET, and an evaluation system for evaluating characteristic variations of the MOSFET. The evaluation system includes a maximum delay amount detection circuit that detects a maximum delay amount of a delay time of a logic circuit using the MOSFET, and an average delay amount detection circuit that detects an average delay amount, and the maximum delay By comparing the amount and the average delay amount, the characteristic variation of the MOSFET is evaluated by separating the characteristic variation in the chip and the characteristic variation between the chips of the MOSFET.

  According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit evaluation method comprising: a logic circuit using a MOSFET; and a substrate bias control circuit for applying a substrate bias to the MOSFET. An on-chip characteristic variation evaluation method comprising: monitoring a median value and an average value of an off-current of the MOSFET and measuring a ratio between the average value and the median value of the off-current in the MOSFET. The characteristic variation is evaluated.

  According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit evaluation method comprising: a logic circuit using a MOSFET; and a substrate bias control circuit for applying a substrate bias to the MOSFET. An evaluation method for evaluating in-chip characteristic variation, wherein the maximum delay amount or the minimum delay amount of the delay time of the logic circuit using the MOSFET is detected, and the average delay amount is detected, and the maximum delay amount or the minimum delay amount is detected. And the average delay amount are compared to separate the in-chip characteristic variation and the inter-chip characteristic variation of the MOSFET to evaluate the MOSFET characteristic variation.

  According to the semiconductor integrated circuit according to the first aspect of the present invention, it is possible to suppress the occurrence of a function failure by minimizing the increase in in-chip characteristic variation due to the application of the substrate bias of the built-in MOSFET.

  In addition, the semiconductor integrated circuit and the evaluation method thereof according to the second aspect of the present invention can accurately evaluate the in-chip characteristic variation of the built-in MOSFET.

  In addition, the semiconductor integrated circuit and the evaluation method thereof according to the third aspect of the present invention increase the detection accuracy for monitoring the in-chip characteristic variation of the built-in MOSFET, and also separate the in-chip characteristic variation and the inter-chip characteristic variation from each other. Can be evaluated.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a configuration of an in-chip characteristic variation suppressing system mounted on an LSI according to the first embodiment of the present invention. In the chip of this LSI, a logic circuit using MOSFET and a core circuit (Chip Core) 11 such as SRAM are formed, and a substrate bias control circuit 12 for applying a substrate bias is incorporated therein. .

  Further, in order to determine the substrate bias application amount, a first monitor circuit (delay monitor circuit or leak monitor circuit) 13 for monitoring the delay time of the logic circuit in the LSI or the leakage current of the MOSFET, and the MOSFET chip A second monitor circuit (OCV monitor circuit) 14 for monitoring characteristic variation (OCV) is provided.

  According to the configuration of FIG. 1, the substrate bias control circuit 12 applies a substrate bias appropriately controlled to the core circuit 11 based on the monitoring result by the first monitoring circuit 13 and the monitoring result by the second monitoring circuit 14. It becomes possible to do. As a result, it is possible to minimize the increase in variation in the characteristics within the chip due to the application of the substrate bias, and to suppress the occurrence of a function failure.

  Note that part or all of the substrate bias control circuit 12 can be configured outside the chip. The second monitor circuit 14 can also be used as a test circuit when performing a function test of the LSI chip.

<Second Embodiment>
FIG. 2 is a block diagram showing a configuration of an in-chip MOSFET characteristic variation evaluation system mounted on an LSI according to the second embodiment of the present invention. This LSI is a logic circuit using MOSFETs, a core circuit (not shown) such as SRAM, a substrate bias control circuit (not shown) for applying a substrate bias to this, and evaluating variations in MOSFET characteristics in the chip. Built-in evaluation system. The evaluation system includes a median value detection circuit 20 that is formed in the chip and monitors the median value of the off-current (Ioff) of the MOSFET, and an average value detection circuit 25 that monitors the average value of Ioff.

  The median value detection circuit 20 uses a plurality of delay circuits (delays) 21 having a delay time inversely proportional to the MOSFET leakage current Ioff to detect the median value of Ioff, and then reduces variations in the median value of Ioff. It is configured. That is, by arranging a plurality of delay circuits (delays) 21 in parallel and inputting the outputs of the delay circuits 21 to, for example, the majority circuit 22, the median value of the subset block of the median value detection circuit 20 is directly detected. . Further, by connecting the median detection circuits 20 in a plurality of stages, variation in the median value of Ioff is reduced. By summing the median values of the subset blocks in this way, when the total value is converted into one subset block, the median value is averaged by canceling the dispersion of the median value, and the accuracy is relatively improved. The median will be detected.

  The average value detection circuit 25 detects the average value of Ioff by connecting a plurality of delay circuits (delays) 21 having a delay time inversely proportional to the leakage current Ioff of the MOSFET. In actuality, the average value is averaged by detecting the total value of each stage and canceling the variations of the plurality of stages, and the average value with relatively improved accuracy is detected.

  As will be described later, when comparing the average value of Ioff with the median value of Ioff, the circuit configuration of the average value detection circuit 25 and the median value detection circuit 20 (preferably, in order to minimize deviations other than random variations) It is desirable to have the same (including layout). Therefore, as shown in FIG. 2, a majority circuit 22 is formed in the average value detection circuit 25 as in the case of the median value detection circuit 20.

  In this case, as shown in FIG. 3, the delay amount is exponentially distributed depending on the OCV of the MOSFET characteristics, and the median value and average value of Ioff vary depending on the magnitude of OCV, and the average value of Ioff varies from the median value. Deviation. Therefore, OCV can be measured and evaluated by measuring the ratio between the average value and the median value of Ioff.

<Third Embodiment>
FIG. 4 is a block diagram showing a configuration of an in-chip MOSFET characteristic variation evaluation system mounted on an LSI according to the third embodiment of the present invention. This LSI is a logic circuit using MOSFETs, a core circuit (not shown) such as SRAM, a substrate bias control circuit (not shown) for applying a substrate bias to this, and evaluating variations in MOSFET characteristics in the chip. Built-in evaluation system. The evaluation system monitors the maximum delay time (maximum delay time) in a logic circuit (for example, a ring oscillator in an LSI) using a MOSFET in order to monitor the characteristic variation (OCV) of the MOSFET formed in the chip. A maximum delay amount detection circuit 40 for detecting and an average delay amount detection circuit 45 for detecting an average value are provided.

  The maximum delay amount detection circuit 40 uses a plurality of delay circuits (delays) 41 to detect the maximum value of the delay time of the delay circuit 41 (the maximum value in the delay time having variation), and then reduces the variation in the maximum value. It is configured. That is, a plurality of delay circuits (delays) 41 are arranged in parallel, and each output of the plurality of delay circuits 41 is input to, for example, an AND circuit 42, thereby detecting the maximum delay time of the delay circuit 41. Further, the maximum delay amount detection circuit 40 is connected in a plurality of stages to average the distribution of the maximum delay amount. That is, as shown in FIG. 5, the variation in the distribution of the maximum delay amount averaged compared to the variation in the distribution of the maximum delay amount is reduced, and the detection accuracy of the maximum delay amount can be improved.

  The average delay amount detection circuit 45 detects the average delay amount by connecting a plurality of delay circuits (delays) 41 in a plurality of stages. Here, as will be described later, when comparing the averaged maximum delay amount and the average delay amount, the average delay amount detection circuit 45 and the maximum delay amount detection circuit are used in order to minimize deviations other than random variations. It is desirable to have the same 40 circuit configurations (including layout if possible). Therefore, as shown in FIG. 4, an AND circuit 42 is formed in the average delay amount detection circuit 45 as in the case of the maximum delay amount detection circuit 40.

  By comparing the averaged maximum delay amount obtained in this way and the average delay amount by a comparison circuit (not shown), the in-chip characteristic variation and the inter-chip characteristic variation are separated to evaluate the OCV. It becomes possible.

  Instead of the maximum delay amount detection circuit 40, a minimum delay amount detection circuit that detects the minimum value of the delay time in the logic circuit using the MOSFET is used, and the averaged minimum delay amount and the average delay amount are calculated. You may change so that it may compare.

1 is a block diagram showing a configuration of an in-chip characteristic variation suppression system mounted on an LSI according to a first embodiment of the present invention. The block diagram which shows the structure of the MOSFET characteristic variation evaluation system in a chip | tip mounted in LSI concerning the 2nd Embodiment of this invention. FIG. 3 is a characteristic diagram for explaining the operation of FIG. 2. The block diagram which shows the structure of the MOSFET characteristic variation evaluation system in a chip | tip mounted in LSI concerning the 3rd Embodiment of this invention. FIG. 5 is a characteristic diagram for explaining the operation of FIG. 4.

Explanation of symbols

20 ... median value detection circuit, 21 ... delay circuit (delay), 22 ... majority decision circuit, 25 ... average value detection circuit.

Claims (5)

  A logic circuit using MOSFET, a first monitor circuit for monitoring variation in characteristics of the MOSFET in the LSI chip, a second monitor circuit for monitoring delay characteristics of the logic circuit and characteristics of leakage current of the MOSFET, A semiconductor integrated circuit, comprising: a substrate bias control circuit that applies a substrate bias controlled based on a monitoring result by the first monitor circuit and the second monitor circuit to the MOSFET. Built-in a logic circuit using a MOSFET, a substrate bias control circuit for applying a substrate bias to the MOSFET, and an evaluation system for evaluating variations in characteristics of the MOSFET in the chip,
The evaluation system includes a median value detection circuit that monitors a median value of the off-state current of the MOSFET, and an average value detection circuit that monitors an average value of the off-state current of the MOSFET. A semiconductor integrated circuit characterized by evaluating a variation in characteristics of the MOSFET in the chip by measuring a ratio to the value. Built-in a logic circuit using a MOSFET, a substrate bias control circuit for applying a substrate bias to the MOSFET, and an evaluation system for evaluating variation in characteristics of the MOSFET,
The evaluation system includes a first delay amount detection circuit that detects a maximum delay amount or a minimum delay amount of a delay time of a logic circuit using the MOSFET, and a second delay amount detection circuit that detects an average delay amount. And comparing the maximum delay amount or the minimum delay amount and the average delay amount to separate the in-chip characteristic variation and the inter-chip characteristic variation of the MOSFET to evaluate the MOSFET characteristic variation. A semiconductor integrated circuit. An evaluation method for evaluating in-chip characteristic variation of the MOSFET in a semiconductor integrated circuit including a logic circuit using a MOSFET and a substrate bias control circuit for applying a substrate bias to the MOSFET,
A semiconductor integrated circuit characterized by monitoring the median value and average value of the off-state current of the MOSFET, and evaluating the in-chip characteristic variation of the MOSFET by measuring the ratio of the mean value and median value of the off-current. Evaluation methods. An evaluation method for evaluating in-chip characteristic variation of the MOSFET in a semiconductor integrated circuit including a logic circuit using a MOSFET and a substrate bias control circuit for applying a substrate bias to the MOSFET,
By detecting the maximum delay amount or the minimum delay amount of the delay time of the logic circuit using the MOSFET and the average delay amount, and comparing the maximum delay amount or the minimum delay amount with the average delay amount, A method for evaluating a semiconductor integrated circuit, wherein the variation in characteristics of the MOSFET is evaluated by separating the variation in characteristics between chips and the variation in characteristics between chips.

Images