JP2009295719A - Through plug wire - Google Patents

Through plug wire Download PDF

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JP2009295719A
JP2009295719A JP2008146602A JP2008146602A JP2009295719A JP 2009295719 A JP2009295719 A JP 2009295719A JP 2008146602 A JP2008146602 A JP 2008146602A JP 2008146602 A JP2008146602 A JP 2008146602A JP 2009295719 A JP2009295719 A JP 2009295719A
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plug
semiconductor substrate
wiring
shape
insulating film
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Kazutoshi Kamibayashi
和利 上林
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ZYCUBE KK
ZyCube Co Ltd
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ZYCUBE KK
ZyCube Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing through plugs, which can suppress generation of problems that when plugs pierced through a semiconductor substrate chip are microfabricated, connection resistance with an electrode connected to the plugs is increased, a leak current may is increased, or insulation destruction or stress migration is generated. <P>SOLUTION: End parts of through plugs 350 for electrically connecting an electrode pad 400 formed on the surface of a semiconductor substrate 100 to a connection electrode 380 formed on the rear face of the substrate 100 are partially entered into the electrode pad 400 and the connection electrode 380. An insulating separation part 210 for insulating the through plugs 350 from the semiconductor substrate 100 is partially entered into an insulating film 205 formed on the surface side of the semiconductor substrate 100. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、貫通プラグ配線の構造に関しており、特に回路が設けられた複数の半導体チップに貫通プラグを設け、これらを積層し接続した3次元積層LSIを作る技術に関する。   The present invention relates to a structure of a through plug wiring, and more particularly, to a technique for forming a three-dimensional stacked LSI in which through plugs are provided in a plurality of semiconductor chips provided with circuits, and these are stacked and connected.

近年、複数の半導体チップを積層した3次元LSIが提案されている。3次元LSIでは、各々の半導体チップの半導体基板を貫通する貫通プラグを設けて、積層した半導体チップ間を電気的に接続している。   In recent years, a three-dimensional LSI in which a plurality of semiconductor chips are stacked has been proposed. In the three-dimensional LSI, a through plug that penetrates the semiconductor substrate of each semiconductor chip is provided to electrically connect the stacked semiconductor chips.

3次元LSIに用いられている半導体基板を貫通する貫通プラグの構造としては、例えば特許文献1に記載されるものがある。図18はこの構造を説明するための平面図であり、図19は図18のA−Bの位置における断面構造を模式的に示す。半導体基板100の一部に、基板を貫通するように絶縁分離領域200が設けられ、当該絶縁分離領域に基板を貫通する貫通プラグ300が設けられる。半導体基板の表側と裏側に露出するこの貫通プラグの上端部と下端部に、上層や下層の半導体チップに設けられた電極を接続することで、3次元LSIを構成する。   An example of the structure of a through plug that penetrates a semiconductor substrate used in a three-dimensional LSI is disclosed in Patent Document 1, for example. FIG. 18 is a plan view for explaining this structure, and FIG. 19 schematically shows a cross-sectional structure at a position AB in FIG. An insulating isolation region 200 is provided in part of the semiconductor substrate 100 so as to penetrate the substrate, and a through plug 300 penetrating the substrate is provided in the insulating isolation region. A three-dimensional LSI is configured by connecting electrodes provided on the upper and lower semiconductor chips to the upper and lower ends of the through plug exposed on the front and back sides of the semiconductor substrate.

半導体基板を貫通する他の貫通プラグの構造として、特許文献2に記載されるものもある。図20は、この構造を説明するもので平面構造を模式的に示す。また、図21は図20のA−Bの位置における断面構造を模式的に示す。半導体基板100の一部に、基板を貫通するように絶縁膜202で絶縁分離された矩形ドーナツ状の貫通プラグ302が設けられ、この矩形ドーナツ状の貫通プラグで囲まれた半導体基板分離領域101にも、絶縁膜201で絶縁分離された線状貫通プラグ301が設けられる。当該従来例では、矩形ドーナツ状の貫通プラグ302と線状貫通プラグ301の両方を用いて半導体チップ間の接続を行っており、理論回路など大きな電流を入出力する半導体チップ間の接続にも対応できるようにしている。
特開2006−165025号公報 特開2006−19431号公報
As another through plug structure penetrating the semiconductor substrate, there is one described in Patent Document 2. FIG. 20 schematically illustrates a planar structure for explaining this structure. FIG. 21 schematically shows a cross-sectional structure at the position AB in FIG. A rectangular donut-shaped through plug 302 insulated and separated by an insulating film 202 is provided in a part of the semiconductor substrate 100 so as to penetrate the substrate, and the semiconductor substrate isolation region 101 surrounded by the rectangular donut-shaped through plug is provided in the semiconductor substrate isolation region 101. In addition, a linear through plug 301 insulated and separated by the insulating film 201 is provided. In the conventional example, the connection between the semiconductor chips is performed using both the rectangular donut-shaped through plug 302 and the linear through plug 301, and the connection between the semiconductor chips that input and output a large current such as a theoretical circuit is also supported. I can do it.
JP 2006-165025 A JP 2006-19431 A

図18〜21に示す従来構造の貫通プラグは、絶縁膜で絶縁分離された貫通プラグを半導体基板の表面側から裏面側に貫通するように設けた構造であることを特徴としている。さらに強調するならば、従来の貫通プラグは絶縁膜に接しており、当該絶縁膜に取り囲まれて設けられることが特徴である。   The through-plug having the conventional structure shown in FIGS. 18 to 21 is characterized in that a through-plug insulated and separated by an insulating film is provided so as to penetrate from the front surface side to the back surface side of the semiconductor substrate. To further emphasize, the conventional through plug is in contact with the insulating film and is provided so as to be surrounded by the insulating film.

前記の絶縁膜は、半導体基板と貫通プラグとを絶縁分離する機能を有している。貫通プラグの上端部および下端部への電気的接続は、露出した貫通プラグの端面に、バンプあるいはハンダボールなどの金属を用いて、他の半導体チップの表面に設けられた電極に接続することで行う。   The insulating film has a function of insulating and separating the semiconductor substrate and the through plug. The electrical connection to the upper end and the lower end of the through plug is achieved by connecting the exposed end of the through plug to an electrode provided on the surface of another semiconductor chip using a metal such as a bump or a solder ball. Do.

電気的接続にバンプあるいはハンダボールを用いることから、接続部は60〜100ミクロン程度の面積を要する。従って、従来の半導体チップで用いられるボンディングパッド(寸法は約100ミクロン平方)を介して、半導体チップを相互に電気的接続を行い、3次元LSIを実現するものである。   Since bumps or solder balls are used for electrical connection, the connection portion requires an area of about 60 to 100 microns. Therefore, the semiconductor chips are electrically connected to each other via the bonding pads (dimensions of about 100 microns square) used in the conventional semiconductor chip to realize a three-dimensional LSI.

LSIの微細化・高密度化は年々進んでおり、3次元LSIに用いられる貫通プラグにおいても、より微細な寸法で電気的接続を行える技術が要求されていた。すなわち、異なる半導体チップ内に設けられたトランジスタ回路を、相互に接続するための微細な貫通プラグの技術が求められている。微細な貫通プラグに求められる寸法は、少なくとも10ミクロン以下が必要となるが、かかる微細寸法の貫通プラグ構造では、プラグに接続する電極との接触面積が貫通プラグの断面積であることから、きわめて小さな接触面積で接続することになり、接続抵抗が大きくなり接続不良が多発するという欠点があった。   The miniaturization and densification of LSIs have been progressing year by year, and a technology capable of electrical connection with finer dimensions has been required even for through plugs used in three-dimensional LSIs. That is, there is a demand for a fine through plug technology for mutually connecting transistor circuits provided in different semiconductor chips. The dimension required for a fine through-plug is required to be at least 10 microns or less. In such a through-plug structure with such a fine dimension, the contact area with the electrode connected to the plug is the cross-sectional area of the through-plug. Since the connection is made with a small contact area, there is a disadvantage that connection resistance increases and connection failures frequently occur.

さらに、図21の従来構造の貫通プラグで微細化しようとすると、半導体を貫通するプラグ径は極力大きくしたいことから、貫通プラグ302と半導体基板100とを絶縁分離する絶縁膜202の厚さを数100ナノメートル以下と薄くすることになる。絶縁膜が薄くなると、貫通プラグと半導体基板との間に生ずるリーク電流経路130が増大するため、LSIが誤作動を引き起こす、あるいは絶縁破壊を引き起こしLSIが不良になるなどの重大な問題が起こる。   Furthermore, when trying to miniaturize the through-plug having the conventional structure shown in FIG. 21, since the plug diameter that penetrates the semiconductor is desired to be as large as possible, the thickness of the insulating film 202 that insulates and isolates the through-plug 302 and the semiconductor substrate 100 is several It will be as thin as 100 nanometers or less. When the insulating film is thinned, the leakage current path 130 generated between the through plug and the semiconductor substrate increases, which causes serious problems such as malfunction of the LSI or failure of the LSI due to dielectric breakdown.

一方、絶縁分離する絶縁膜202の厚さを充分に厚く設けると、当該絶縁膜と貫通プラグに用いる電極材料との熱膨張係数が大きいために、貫通プラグの特に上端部および下端部の近傍に大きなストレスが加わる。この結果、貫通プラグに用いた電極材が電流の流れに沿って移動する現象(ストレスマイグレーション)が顕著となり、貫通プラグの一部に空洞が生じ断線するという問題も生ずる。かかるストレスマイグレーションによる断線は、貫通プラグの径寸法が小さくなるほど顕著となることから、微細な貫通プラグ配線ではきわめて重大な問題となる。ストレスマイグレーションによる断線は、ある程度の時間を経過した後に発現することから、製品が市場に出回った後に故障となるため、長期信頼性を著しく劣化させる点で影響が極めて大きい。   On the other hand, if the insulating film 202 to be insulated and separated is provided with a sufficiently large thickness, the thermal expansion coefficient between the insulating film and the electrode material used for the through plug is large. Therefore, particularly in the vicinity of the upper end and the lower end of the through plug. It adds a lot of stress. As a result, the phenomenon (stress migration) in which the electrode material used for the through plug moves along the flow of current becomes remarkable, and a problem arises in that a cavity is formed in a part of the through plug and is disconnected. The disconnection due to the stress migration becomes more serious as the diameter of the through plug becomes smaller, and therefore becomes a very serious problem in a fine through plug wiring. Since disconnection due to stress migration occurs after a certain amount of time has elapsed, a failure occurs after the product is put on the market, so that the influence is extremely great in that the long-term reliability is significantly deteriorated.

本発明は、貫通プラグの径寸法がきわめて小さい場合でも接続抵抗が小さくでき、また貫通プラグと半導体基板との間の絶縁性に優れ、長期信頼性の特性にも優れた貫通プラグ配線を提供することを目的としている。   The present invention provides a through plug wiring that can reduce the connection resistance even when the diameter of the through plug is extremely small, has excellent insulation between the through plug and the semiconductor substrate, and has excellent long-term reliability characteristics. The purpose is that.

本発明によれば、回路が設けられた複数の半導体チップからなる3次元積層LSIにおいて、前記半導体チップの半導体基板を貫通プラグの形状に合わせて貫通させた、少なくとも1個の孔のそれぞれに埋め込まれた前記貫通プラグと、該貫通プラグのすべてを取り囲む形状に前記半導体基板を貫通して設けた孔に埋め込まれた絶縁分離部と、前記貫通プラグに接続される前記半導体基板の表面と裏面に設けた電極と、を具備することを特徴とする貫通プラグ配線を提供する。   According to the present invention, in a three-dimensional stacked LSI composed of a plurality of semiconductor chips provided with a circuit, the semiconductor substrate of the semiconductor chip is embedded in each of at least one hole penetrating according to the shape of the through plug. The through plug, the insulating isolation part embedded in the hole penetrating the semiconductor substrate in a shape surrounding the through plug, and the front and back surfaces of the semiconductor substrate connected to the through plug And a through-plug wiring characterized by comprising an electrode provided.

また、前記半導体基板の表面と裏面に設けた前記電極の少なくとも一方に、前記貫通プラグの一部が食い込んだ埋め込み構造を有することを特徴とする貫通プラグ配線である。   Further, the through-plug wiring is characterized in that at least one of the electrodes provided on the front surface and the back surface of the semiconductor substrate has a buried structure in which a part of the through-plug is cut.

さらに、前記半導体基板の表面および裏面に設けられた絶縁膜に、前記絶縁分離部の一部が食い込んだ埋め込み構造を有することを特徴とした貫通プラグ配線である。   Further, the through plug wiring is characterized in that the insulating film provided on the front and back surfaces of the semiconductor substrate has a buried structure in which a part of the insulating isolation portion is cut.

また、前記半導体基板を前記貫通プラグの形状に合わせて貫通させた孔の断面形状が、線または正方形もしくは円形の形状であることを特徴とする貫通プラグ配線である。   Further, the through-plug wiring is characterized in that the cross-sectional shape of the hole through which the semiconductor substrate is passed in accordance with the shape of the through-plug is a line, a square or a circular shape.

また、前記貫通プラグと該貫通プラグの形状に穿った貫通孔側壁を形成する前記半導体基板の間に、導電性ポリシリコン、金属の窒素化合物又は金属の珪素化合物からなる導電緩衝膜を設けることを特徴とする貫通プラグ配線である。   In addition, a conductive buffer film made of conductive polysilicon, a metal nitrogen compound, or a metal silicon compound is provided between the through-plug and the semiconductor substrate forming the through-hole side wall formed in the shape of the through-plug. This is a featured through plug wiring.

および、前記絶縁分離部に囲まれた前記半導体基板の領域は、前記貫通プラグを埋め込む孔を抜いた残余の領域であり、前記導電緩衝膜を介して又は直接に前記貫通プラグと接触することを特徴とする貫通プラグ配線である。   The region of the semiconductor substrate surrounded by the insulating isolation part is a remaining region where a hole for embedding the through plug is removed, and is in contact with the through plug via the conductive buffer film or directly. This is a featured through plug wiring.

本発明によれば、貫通プラグの両端部に接続する他の電極との接触面積が大きくできることから、接続抵抗を低く維持しながら、微細な寸法の貫通プラグ配線構造が実現される。   According to the present invention, since the contact area with other electrodes connected to both end portions of the through plug can be increased, a through plug wiring structure with a fine dimension can be realized while keeping the connection resistance low.

また、本発明になる貫通プラグ配線は、プラグ径が10ミクロン以下の微細プラグであっても、0.1ミリオーム以下という実用上充分に低い接続抵抗のプラグが再現性良く実現できる。従って、異なる半導体チップ間のトランジスタ回路ブロックを相互に接続することも、さらにはトランジスタ回路自体を相互に接続することが可能である。このため、3次元積層LSIのいっそうの高密度化に極めて有効である。   In addition, the through-plug wiring according to the present invention can realize a plug having a practically low connection resistance of 0.1 milliohm or less with good reproducibility even if the plug diameter is a fine plug of 10 microns or less. Therefore, it is possible to connect transistor circuit blocks between different semiconductor chips to each other and to connect the transistor circuits themselves to each other. Therefore, it is extremely effective for further increasing the density of the three-dimensional stacked LSI.

本発明によれば、貫通プラグと半導体基板とを絶縁分離する絶縁膜の厚さを充分厚く設けることができることから、貫通プラグと半導体基板との間に生ずるリーク電流を実用上問題ない低いレベルに抑えることができ、あるいは絶縁破壊を防止できる。したがって、LSIの誤動作を防止し故障の少ない、高品質で信頼性に優れた3次元積層LSIが実現される。   According to the present invention, since the insulating film for insulating and separating the through plug and the semiconductor substrate can be provided with a sufficiently large thickness, the leakage current generated between the through plug and the semiconductor substrate is at a low level that does not cause a problem in practice. It can be suppressed, or dielectric breakdown can be prevented. Therefore, a high-quality and highly reliable three-dimensional stacked LSI is realized that prevents malfunction of the LSI and has few failures.

さらに、本発明になる貫通プラグ配線は、貫通プラグと絶縁分離膜との間に半導体基板材料が設けられるため、貫通プラグに加わるストレスが小さい。このため、ストレスマイグレーション現象が防止できるため、貫通プラグの断面寸法が微細になっても断線が生じにくいという効果がある。したがって、長期信頼性に優れた3次元積層LSIが提供できる。   Furthermore, since the through plug wiring according to the present invention is provided with a semiconductor substrate material between the through plug and the insulating isolation film, the stress applied to the through plug is small. For this reason, since a stress migration phenomenon can be prevented, there is an effect that even if the cross-sectional dimension of the through plug becomes fine, disconnection hardly occurs. Therefore, it is possible to provide a three-dimensional stacked LSI having excellent long-term reliability.

以下、本発明になる貫通プラグ配線の構造およびこの製造工程を、図面を用いて説明する。
(弟1の実施の形態)
The structure of the through plug wiring according to the present invention and the manufacturing process will be described below with reference to the drawings.
(Embodiment of brother 1)

図1は、本発明になる第1の貫通プラグ配線の構造を説明する図であり、トランジスタ回路が設けられた半導体基板(トランジスタや配線等はすべて完成している)の裏面側から見た平面構造を模式的に示す。図において、100は半導体基板、210は絶縁分離部、101は絶縁分離部210により分離された半導体基板領域、350は貫通プラグ、400は半導体基板の表面(図では紙面の裏側になる)に設けられた半導体チップの内部および外部に信号を伝えるための電極パッドを示す。   FIG. 1 is a diagram for explaining the structure of a first through plug wiring according to the present invention, and is a plan view seen from the back side of a semiconductor substrate (all transistors, wirings, etc. are completed) provided with transistor circuits. The structure is shown schematically. In the figure, 100 is a semiconductor substrate, 210 is an insulation separation part, 101 is a semiconductor substrate region separated by the insulation separation part 210, 350 is a through plug, and 400 is provided on the surface of the semiconductor substrate (in the figure, on the back side of the paper). 2 shows electrode pads for transmitting signals to the inside and outside of the manufactured semiconductor chip.

図2は図1のA−Bの位置における断面構造を模式的に示す。図において、110はトランジスタのソースやドレインなどの回路素子が設けられた領域、205は半導体基板表面に設けられた絶縁膜、220と230は半導体基板裏面に設けられた第一の絶縁膜と第二の絶縁膜、380は貫通プラグ350と接続をとる接続電極、をそれぞれ示す。なお、構造の説明を容易とするために、接続電極380は図1では省略されている。当該例では、貫通プラグ350には銅、ニッケル、タングステンなどの金属、あるいは金属珪素化合物や金属窒素化合物、あるいは導電性ポリシリコンなどが用いられる。   FIG. 2 schematically shows a cross-sectional structure at the position AB in FIG. In the figure, 110 is a region in which circuit elements such as a source and drain of a transistor are provided, 205 is an insulating film provided on the surface of the semiconductor substrate, 220 and 230 are the first insulating film and the second insulating film provided on the back surface of the semiconductor substrate. Two insulating films, 380, are connection electrodes that are connected to the through plugs 350, respectively. Note that the connection electrode 380 is omitted in FIG. 1 for easy explanation of the structure. In this example, the through plug 350 is made of a metal such as copper, nickel, or tungsten, a metal silicon compound, a metal nitrogen compound, or conductive polysilicon.

本発明の特徴は、貫通プラグ350は、半導体基板の表面(図2では下側)に設けられた電極パッド400の厚み方向に食い込むように設けられ、また半導体基板の裏面(図2では上側)に設けられた電極380の厚み方向にも食い込むように設けられる。この構造により、貫通プラグ350に対する電極パッド400、および電極380との間の接触面積を拡大できることから、接触抵抗を充分に低く維持している。   The feature of the present invention is that the through plug 350 is provided so as to bite in the thickness direction of the electrode pad 400 provided on the front surface (lower side in FIG. 2) of the semiconductor substrate, and the rear surface (upper side in FIG. 2) of the semiconductor substrate. The electrode 380 is provided so as to bite in the thickness direction. With this structure, the contact area between the electrode pad 400 and the electrode 380 with respect to the through plug 350 can be increased, so that the contact resistance is kept sufficiently low.

さらに、当該発明の貫通プラグ配線では、貫通プラグ350は、分離された半導体基板領域101と接触する構成となっている。半導体基板にはシリコン結晶が用いられるが、シリコン結晶は絶縁膜に比べて貫通プラグ材料に対するストレスが小さい。このため、ストレスマイグレーションの現象が起こりにくく、したがって貫通プラグに空洞が生じにくい。   Furthermore, in the through plug wiring of the present invention, the through plug 350 is configured to contact the separated semiconductor substrate region 101. Although a silicon crystal is used for the semiconductor substrate, the silicon crystal has less stress on the through plug material than the insulating film. For this reason, the phenomenon of stress migration is unlikely to occur, and therefore a cavity is unlikely to occur in the through plug.

さらに、当該貫通プラグ配線では、貫通プラグ350は、分離された半導体基板領域101と接触する構成となっており、分離された半導体基板領域101も貫通プラグと同電位になる。したがって、分離された半導体基板領域101も、貫通プラグ抵抗の低減に役立っている。   Further, in the through plug wiring, the through plug 350 is in contact with the separated semiconductor substrate region 101, and the separated semiconductor substrate region 101 has the same potential as the through plug. Therefore, the separated semiconductor substrate region 101 also helps to reduce the through plug resistance.

なお、本実施例では、絶縁分離部210が半導体基板表面の絶縁膜205に単に接する構造となっており、絶縁分離部210の厚さが数千オングストローム以下になると、当該膜の接合界面を通じてリーク電流経路140が生じ易くなり、貫通プラグ350と半導体基板100との間にリーク電流が生じる。この現象は、回路のショートあるいは不要な消費電力の増加をもたらし、LSIの性能を著しく損ねる。あるいは絶縁破壊を生ずることで故障の原因となる。これを防止する構造を備えたものが、図3に示す本発明の第2の実施形態である。
(弟2の実施の形態)
In this embodiment, the insulating isolation part 210 is simply in contact with the insulating film 205 on the surface of the semiconductor substrate. When the thickness of the insulating isolation part 210 is several thousand angstroms or less, leakage occurs through the bonding interface of the film. The current path 140 is easily generated, and a leak current is generated between the through plug 350 and the semiconductor substrate 100. This phenomenon causes a short circuit or an unnecessary increase in power consumption, which significantly impairs the performance of the LSI. Or it causes breakdown by causing dielectric breakdown. A structure that prevents this is the second embodiment of the present invention shown in FIG.
(Embodiment of brother 2)

図3は本発明になる第2の実施の形態を説明する図で、貫通配線の断面構造を模式的に示す。本実施例では、絶縁分離部210が半導体基板表面の絶縁膜205に食い込んで設けられる。この構造にすることにより、従来の微細な寸法の絶縁分離膜で発生していたリーク電流を、実用的に支障ないレベルに抑えられる。また、半導体基板の裏面側においても、絶縁分離膜210は第一の絶縁膜220の内部にまで食い込んで設けられており、当該絶縁膜の界面を通じてのリーク電流も実用上無視できるレベルに抑えられる。
(弟3の実施の形態)
FIG. 3 is a diagram for explaining a second embodiment according to the present invention, and schematically shows a cross-sectional structure of the through wiring. In this embodiment, the insulating separation part 210 is provided so as to bite into the insulating film 205 on the surface of the semiconductor substrate. By adopting this structure, the leakage current generated in the conventional insulating separation film having fine dimensions can be suppressed to a level that does not impede practically. In addition, the insulating separation film 210 is also provided to penetrate into the first insulating film 220 on the back surface side of the semiconductor substrate, and the leakage current through the interface of the insulating film can be suppressed to a level that can be ignored in practice. .
(Embodiment of brother 3)

図2および図3に示す構造の貫通プラグ配線では、貫通プラグ350が、分離された半導体基板領域101と接触する構成となっている。貫通プラグ350に金属材料が用いられる場合には、数百℃の熱処理中に、当該金属材料が半導体基板であるシリコンと異常反応を起こし、貫通プラグやその近辺の半導体基板に微細な空洞が生ずる場合がある。かかる空洞が生ずると、貫通プラグが断線し、あるいは抵抗が高くなるという問題が生ずる。かかる現象は、貫通プラグに用いる金属材料の種類にも依存するが、貫通プラグの構造をさらに工夫することで避けることができる。   In the through plug wiring having the structure shown in FIGS. 2 and 3, the through plug 350 is in contact with the separated semiconductor substrate region 101. When a metal material is used for the through plug 350, the metal material causes an abnormal reaction with silicon, which is a semiconductor substrate, during heat treatment at several hundred degrees Celsius, and a fine cavity is generated in the through plug and the semiconductor substrate in the vicinity thereof. There is a case. When such a cavity is generated, there arises a problem that the through plug is disconnected or the resistance is increased. Such a phenomenon depends on the type of metal material used for the through plug, but can be avoided by further devising the structure of the through plug.

図4は、貫通プラグの構造を工夫した第3の実施の形態を示しており、貫通配線の断面構造を模式的に示す。図において、図2や図3と同記号は同じ機能を有する物であり、352は導電緩衝膜である。当該実施例では、第1の材料からなる貫通プラグ350の周囲を、第2の材料からなる導電緩衝膜352で取り囲まれる構造であるのが特徴である。かかる構造では、貫通プラグの材料としては、銅、ニッケル、タングステンなど導電性の高い材料を用い、導電緩衝膜にはポリシリコン、およびタングステンやタンタルなどの珪素化合物材料、あるいはタングステンやタンタルやチタンなどの窒化物材料を用いる。   FIG. 4 shows a third embodiment in which the structure of the through plug is devised, and schematically shows a cross-sectional structure of the through wiring. In the figure, the same symbols as those in FIGS. 2 and 3 have the same function, and 352 is a conductive buffer film. This embodiment is characterized in that the periphery of the through plug 350 made of the first material is surrounded by the conductive buffer film 352 made of the second material. In such a structure, a material having a high conductivity such as copper, nickel, or tungsten is used as the material of the through plug, and a silicon compound material such as polysilicon and tungsten or tantalum, or tungsten, tantalum, or titanium is used as the conductive buffer film. The nitride material is used.

導電緩衝膜352に用いられるポリシリコン、珪素化合物材料や窒化物材料は、半導体基板に用いられるシリコンに対する化学的反応力が小さいという性質を持っており、分離された半導体基板領域101のシリコンとの異常反応が生じにくいため、当該部分での空洞の発生や断線の発生を効果的に防止している。   Polysilicon, silicon compound materials, and nitride materials used for the conductive buffer film 352 have a property that the chemical reaction force with respect to silicon used for the semiconductor substrate is small. Since abnormal reactions are unlikely to occur, the generation of cavities and disconnections at the relevant portions are effectively prevented.

なお、当該例では、貫通プラグ材料としてポリシリコン、およびタングステンやタンタルなどの珪素化合物材料、あるいはタングステンやタンタルやチタンなどの窒化物材料を用いることとして説明したが、半導体基板としてGaAsなどの化合物結晶が用いられる場合には、反応の生じにくい他の材料を用いて良いことは言うまでもない。
(弟4の実施の形態)
In this example, it has been described that polysilicon and silicon compound material such as tungsten or tantalum or nitride material such as tungsten, tantalum or titanium are used as the through plug material. However, a compound crystal such as GaAs is used as the semiconductor substrate. Needless to say, other materials that do not easily react may be used.
(Embodiment of brother 4)

図5は、本発明になる第4の実施例を示し、半導体基板の裏面側から見た平面構造を示す。図において、図1と同記号は同じ機能を有する物である。当該実施例では、貫通プラグ350はストライプ状に設けられ、接続される電極との接触面積を広く設ける効果がある。なお、当該構造においても、A−Bにおける断面構造は図2と同じになる。
(弟5の実施の形態)
FIG. 5 shows a fourth embodiment according to the present invention, and shows a planar structure viewed from the back side of the semiconductor substrate. In the figure, the same symbols as those in FIG. 1 denote the same functions. In this embodiment, the through plugs 350 are provided in a stripe shape, which has an effect of providing a wide contact area with the connected electrodes. Note that also in this structure, the cross-sectional structure taken along AB is the same as that in FIG.
(Embodiment of brother 5)

図6は、本発明になる第5の実施例を示し、半導体基板の裏面側から見た平面構造を示す。図において、図1と同記号は同じ機能を有する物である。当該実施例では、貫通プラグ350は矩形のドーナツ状に設けられ、接続される電極との接触面積を広く取ることで大きな電流を流せる効果がある。なお、貫通プラグの形状は、この上に設けられる電極との接触面積を制限することがない限りその形状や本数は自由に選択して良いことは明らかである。
(製造工程1)
FIG. 6 shows a fifth embodiment according to the present invention, and shows a planar structure viewed from the back side of the semiconductor substrate. In the figure, the same symbols as those in FIG. 1 denote the same functions. In this embodiment, the through plug 350 is provided in a rectangular donut shape, and has an effect of allowing a large current to flow by widening the contact area with the connected electrode. It is obvious that the shape and the number of the through plugs can be freely selected as long as the contact area with the electrode provided thereon is not limited.
(Manufacturing process 1)

本発明になる貫通プラグの構造は、次のような製造工程により形成される。図7〜図15は図3に示した実施例の貫通プラグ配線を形成する工程を説明するもので、貫通プラグ配線の断面構造を示している。まず、図7において、半導体基板の表面にトランジスタ回路が設けられた半導体基板(トランジスタや配線等は製作済み)の表面に、樹脂250を用いて支持基板500を接着する。支持基板としての好ましい材料は、例えばガラスやシリコンなどが挙げられる。支持基板500を接着した後に、半導体基板の裏面側(図7の上側)を研削および研磨を行い、基板の厚さを所望の厚さにする。この時の好ましい厚さは、30〜300ミクロンである。   The structure of the through plug according to the present invention is formed by the following manufacturing process. 7 to 15 are for explaining the process of forming the through plug wiring of the embodiment shown in FIG. 3, and show the sectional structure of the through plug wiring. First, in FIG. 7, a support substrate 500 is bonded using a resin 250 to the surface of a semiconductor substrate (transistors, wirings, and the like already manufactured) provided with a transistor circuit on the surface of the semiconductor substrate. Examples of preferable materials for the support substrate include glass and silicon. After the support substrate 500 is bonded, the back surface side (the upper side in FIG. 7) of the semiconductor substrate is ground and polished, so that the substrate has a desired thickness. A preferable thickness at this time is 30 to 300 microns.

次に、図8において、半導体基板の裏面に第一の絶縁膜220を設けた後にフォトレジスト600を塗布する。続いて、例えば赤外光で目合わせが出来る露光装置により、半導体基板表面に設けられている電極パッド400に対して位置決めを行い、露光・現像を行うことにより、貫通プラグを設けるべき領域を囲む部分の前記フォトレジスト600の所望の部分に開口パターン221を設ける。なお、当該工程で用いる露光装置として、赤外光で目合わせをする方式以外にも、裏面の光学パターンを予め記憶する光学パターンリンク方式を採用するのも一法である。   Next, in FIG. 8, after providing the first insulating film 220 on the back surface of the semiconductor substrate, a photoresist 600 is applied. Subsequently, for example, by using an exposure apparatus capable of alignment with infrared light, positioning is performed with respect to the electrode pad 400 provided on the surface of the semiconductor substrate, and exposure / development is performed, thereby surrounding a region where the through plug is to be provided. An opening pattern 221 is provided in a desired portion of the photoresist 600 in the portion. In addition to the method of aligning with infrared light, an optical pattern link method that stores the optical pattern on the back side in advance is also employed as the exposure apparatus used in this process.

次に、図9において、フォトレジストの開口パターン221をマスクにして第一の絶縁膜220を選択的に除去し、絶縁膜の開孔パターン222を形成する。   Next, in FIG. 9, the first insulating film 220 is selectively removed using the photoresist opening pattern 221 as a mask to form an opening pattern 222 of the insulating film.

次に、図10において、第一の絶縁膜220の開孔パターン222をマスクにして、例えばドライエッチングの手段を用いて、半導体基板100に貫通孔102を掘り込む。このエッチングでは、半導体基板100の厚み分を掘り込み、さらに絶縁膜205に部分的に食い込むようにする。絶縁膜205に部分的に食い込む量は、0.02〜0.2ミクロンで良い結果を得た。   Next, in FIG. 10, the through hole 102 is dug into the semiconductor substrate 100 by using, for example, dry etching means with the hole pattern 222 of the first insulating film 220 as a mask. In this etching, the thickness of the semiconductor substrate 100 is dug, and further, the insulating film 205 is partially bitten. Good results were obtained when the amount of biting into the insulating film 205 was 0.02 to 0.2 microns.

次に、図11において、孔102の内部に絶縁膜を埋め込み、絶縁分離部210が設けられる。当該絶縁膜材料の好ましい例としては、SiO2系、SiON系、PSG系などが挙げられ、化学的気相成長法あるいは塗布法などの手法で形成する。当該絶縁分離膜210は、絶縁性を充分に得るために、材料の異なる膜を複数層に設けても良い。   Next, in FIG. 11, an insulating film is embedded in the hole 102 to provide an insulating separation part 210. Preferable examples of the insulating film material include SiO 2 type, SiON type, and PSG type, and they are formed by a method such as a chemical vapor deposition method or a coating method. The insulating separation film 210 may be provided with a plurality of layers made of different materials in order to obtain sufficient insulation.

次に、図12において、半導体基板の裏面に第二の絶縁膜230を設けた後に、再びフォトレジスト露光工程により、半導体基板表面に設けられた電極パッド400に対して位置決めを行い、貫通プラグを掘り込む位置の第二の絶縁膜230に開孔パターン231を設ける。   Next, in FIG. 12, after the second insulating film 230 is provided on the back surface of the semiconductor substrate, the photoresist pad is positioned again with respect to the electrode pad 400 provided on the semiconductor substrate surface, and the through plug is inserted. An opening pattern 231 is provided in the second insulating film 230 at the position to be dug.

次に、図13において、第二の絶縁膜230の開孔パターン231をマスクにして、第一の絶縁膜220、半導体基板100、絶縁膜205と掘り込み、さらに配線パッド400の厚さ方向にも部分的に食い込むように掘り込み、貫通孔104を設ける。配線パッド400に部分的に食い込む量は、0.01〜0.1ミクロンで良い結果を得た。   Next, in FIG. 13, using the opening pattern 231 of the second insulating film 230 as a mask, the first insulating film 220, the semiconductor substrate 100, and the insulating film 205 are dug, and further in the thickness direction of the wiring pad 400. Also, a through hole 104 is provided by digging so as to partially bite. Good results were obtained when the amount of partial biting into the wiring pad 400 was 0.01 to 0.1 microns.

次に、図14において、貫通孔104の内部に導電材料を埋め込み、貫通プラグ350が設けられる。当該導電材料の好ましい例としては、タングステン・シリサイド、導電性ポリシリコン、導電性ペーストなどがあり、いずれを選択するかは自由である。   Next, in FIG. 14, a conductive material is embedded in the through hole 104, and a through plug 350 is provided. Preferable examples of the conductive material include tungsten silicide, conductive polysilicon, and conductive paste, and any one can be selected freely.

次に、図15において、フォトレジスト膜600を設け、露光工程により基板裏面側の貫通プラグ350の端部を含む領域の第二の絶縁膜230が、ドライエッチング等の手法で選択的に除去され、配線接続領域105が設けられる。かかる工程で、貫通プラグ350の端部が、第二の絶縁膜220の表面から大きく張り出た構造となる。この貫通プラグの好ましい張り出し量としては、0.01〜0.3ミクロンでよい結果を得た。   Next, in FIG. 15, a photoresist film 600 is provided, and the second insulating film 230 in the region including the end of the through plug 350 on the back surface side of the substrate is selectively removed by a method such as dry etching in the exposure process. A wiring connection region 105 is provided. Through this process, the end of the through plug 350 has a structure that greatly protrudes from the surface of the second insulating film 220. As a preferable overhang amount of this through plug, good results were obtained with 0.01 to 0.3 microns.

この後に、フォトレジスト・パターン600をマスクとして、無電界メッキなどの手段により、配線接続領域105に金属電極が選択的に設けられ、接続電極380が設けられ、図3に示した貫通プラグ配線構造が形成される。当該接続電極380の好ましい材料としては、Al、Ni、Cu、およびそれらを含む合金であり、いずれを選択するかは自由である。また、接続電極380の厚さとしては、0.5〜2ミクロンでよい結果を得た。   Thereafter, using the photoresist pattern 600 as a mask, a metal electrode is selectively provided in the wiring connection region 105 by means such as electroless plating, and a connection electrode 380 is provided, and the through plug wiring structure shown in FIG. Is formed. Preferred materials for the connection electrode 380 are Al, Ni, Cu, and alloys containing them, and any one can be freely selected. Further, good results were obtained when the thickness of the connection electrode 380 was 0.5 to 2 microns.

上記した製造工程では、支持基板としてガラスやシリコンを用いるとして説明したが、半導体チップを用いて、回路が形成された表面側に接着することでも良い。この場合は、支持基板となる半導体チップの回路パターンに対し位置合わせをする必要がある。
(製造工程2)
In the above-described manufacturing process, it has been described that glass or silicon is used as the support substrate. However, a semiconductor chip may be used to adhere to the surface side on which the circuit is formed. In this case, it is necessary to align the position with respect to the circuit pattern of the semiconductor chip serving as the support substrate.
(Manufacturing process 2)

図4に示した構造の貫通プラグ配線は、次のような工程で形成される。まず、前記した弟6の実施の形態で説明したと同じ工程を経て、図13に示される貫通孔104の形成まで行う。続いて、図16に示すように、形成された貫通孔104の側壁に導電緩衝膜352が、CVD法あるいはスパッタ蒸着法などの手段で設けられる。当該導電緩衝膜の材料としては、タングステンやタンタルなどの珪素化合物、あるいはタングステンやタンタルやチタンなどの窒化物を用いる。かかる膜は、基板であるシリコンとの化学的反応を防止する効果があり、その厚さとして0.01〜0.2ミクロンで良い結果を得た。   The through plug wiring having the structure shown in FIG. 4 is formed by the following process. First, through the same steps as described in the embodiment of the younger brother 6 described above, the process up to the formation of the through hole 104 shown in FIG. Subsequently, as shown in FIG. 16, a conductive buffer film 352 is provided on the side wall of the formed through-hole 104 by means such as a CVD method or a sputter deposition method. As the material of the conductive buffer film, a silicon compound such as tungsten or tantalum, or a nitride such as tungsten, tantalum, or titanium is used. Such a film has an effect of preventing chemical reaction with silicon as a substrate, and a good result was obtained with a thickness of 0.01 to 0.2 microns.

次に、図17に示すように、貫通プラグ350が設けられる。当該貫通プラグの材料としては、銅、ニッケル、タングステン、導電性ポリシリコンなど導電性の高い材料を用いる。この後、前記した弟6の実施の形態で説明したと同じ工程を経て、図4に示される貫通プラグ配線が形成される。   Next, as shown in FIG. 17, a through plug 350 is provided. As the material of the through plug, a highly conductive material such as copper, nickel, tungsten, or conductive polysilicon is used. Thereafter, the through plug wiring shown in FIG. 4 is formed through the same process as described in the embodiment of the younger brother 6 described above.

「本発明になる第1の貫通プラグ配線の構造を説明する平面図」"Plan view explaining the structure of the first through plug wiring according to the present invention" 「本発明になる第1の貫通プラグ配線の構造を説明する断面図」"Cross-sectional view for explaining the structure of the first through plug wiring according to the present invention" 「本発明になる第2の貫通プラグ配線の構造を説明する断面図」“Cross sectional view for explaining the structure of the second through plug wiring according to the present invention” 「本発明になる第3の貫通プラグ配線の構造を説明する断面図」"Cross-sectional view illustrating the structure of the third through plug wiring according to the present invention" 「本発明になる第4の貫通プラグ配線の構造を説明する平面図」"Plan view explaining the structure of the fourth through plug wiring according to the present invention" 「本発明になる第4の貫通プラグ配線の構造を説明する平面図」"Plan view explaining the structure of the fourth through plug wiring according to the present invention" 「本発明の貫通プラグ配線の工程断面図1」"Process sectional view 1 of through plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図2」"Process sectional view 2 of through-plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図3」"Process sectional view 3 of the through plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図4」"Process sectional view 4 of through plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図5」"Process sectional view 5 of through-plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図6」"Process sectional view 6 of through plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図7」"Process sectional view 7 of through plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図8」"Process sectional view 8 of through plug wiring of the present invention" 「本発明の貫通プラグ配線の工程断面図9」"Process sectional view 9 of through plug wiring of the present invention" 「本発明の他の貫通プラグ配線の工程断面図1」"Process sectional view 1 of other through plug wiring of the present invention" 「本発明の他の貫通プラグ配線の工程断面図2」“Process sectional view 2 of another through plug wiring of the present invention” 「従来の貫通配線の構造を説明する平面図」"Plan view explaining the structure of a conventional through wiring" 「従来の貫通配線の構造を説明する断面図」"Cross-sectional view explaining the structure of a conventional through wiring" 「従来の貫通配線の他の構造を説明する平面図」"Plan view explaining another structure of conventional through wiring" 「従来の貫通配線の他の構造を説明する断面図」"Cross-sectional view explaining another structure of conventional through wiring"

符号の説明Explanation of symbols

100 半導体基板
101 分離された半導体基板領域
102, 104 貫通孔
105 配線接続領域
110 回路素子が設けられた領域
130, 140 リーク電流の経路
200 絶縁分離領域
201, 202, 205 絶縁膜
210 絶縁分離部
221, 222, 231 開口パターン
220 第一の絶縁膜
230 第二の絶縁膜
250 樹脂
300, 301, 302, 350 貫通プラグ
352 導電緩衝膜
380 接続電極
400 配線パッド
500 支持基板
600 フォトレジスト
100 Semiconductor substrate
101 Isolated semiconductor substrate area
102, 104 Through hole
105 Wiring connection area
110 Area where circuit elements are provided
130, 140 Leakage current path
200 Isolation region
201, 202, 205 Insulating film
210 Isolation section
221, 222, 231 Opening pattern
220 First insulation film
230 Second insulation film
250 resin
300, 301, 302, 350 Through plug
352 Conductive buffer film
380 Connection electrode
400 wiring pads
500 Support substrate
600 photoresist

Claims (6)

回路が設けられた複数の半導体チップからなる3次元積層LSIにおいて、
前記半導体チップの半導体基板を貫通プラグの形状に合わせて貫通させた、少なくとも1個の孔のそれぞれに埋め込まれた前記貫通プラグと、
該貫通プラグのすべてを取り囲む形状に前記半導体基板を貫通して設けた孔に埋め込まれた絶縁分離部と、
前記貫通プラグに接続される前記半導体基板の表面と裏面に設けた電極と、
を具備することを特徴とする貫通プラグ配線。
In a three-dimensional stacked LSI composed of a plurality of semiconductor chips provided with a circuit,
The through plug embedded in each of at least one hole, penetrating the semiconductor substrate of the semiconductor chip according to the shape of the through plug; and
An insulating isolation part embedded in a hole provided through the semiconductor substrate in a shape surrounding all of the through plug;
Electrodes provided on the front and back surfaces of the semiconductor substrate connected to the through plug;
Through-plug wiring characterized by comprising.
前記電極の少なくとも一方に、前記貫通プラグの一部が食い込んだ埋め込み構造を有することを特徴とする請求項1記載の貫通プラグ配線。   The through plug wiring according to claim 1, wherein at least one of the electrodes has an embedded structure in which a part of the through plug is cut. 前記半導体基板の表面および裏面に設けられた絶縁膜に、前記絶縁分離部の一部が食い込んだ埋め込み構造を有することを特徴とする請求項1又は請求項2記載の貫通プラグ配線。   3. The through plug wiring according to claim 1, wherein the insulating film provided on the front surface and the back surface of the semiconductor substrate has a buried structure in which a part of the insulating isolation portion is cut. 前記半導体基板を前記貫通プラグの形状に合わせて貫通させた孔の断面形状が、線または正方形もしくは円形の形状であることを特徴とする請求項1乃至請求項3のいずれか記載の貫通プラグ配線。   The through plug wiring according to any one of claims 1 to 3, wherein a cross-sectional shape of a hole through which the semiconductor substrate passes through in accordance with a shape of the through plug is a line, a square shape, or a circular shape. . 前記貫通プラグと該貫通プラグの形状に穿った貫通孔側壁を形成する前記半導体基板の間に、導電性ポリシリコン、金属の窒素化合物又は金属の珪素化合物からなる導電緩衝膜を設けることを特徴とする請求項1乃至請求項4のいずれか記載の貫通プラグ配線。   A conductive buffer film made of conductive polysilicon, a metal nitrogen compound, or a metal silicon compound is provided between the through plug and the semiconductor substrate forming a through hole side wall formed in the shape of the through plug. The through plug wiring according to any one of claims 1 to 4. 前記絶縁分離部に囲まれた前記半導体基板の領域は、前記貫通プラグを埋め込む孔を抜いた残余の領域であり、前記導電緩衝膜を介して又は直接に前記貫通プラグと接触することを特徴とする請求項1乃至請求項5のいずれか記載の貫通プラグ配線。   The region of the semiconductor substrate surrounded by the insulating isolation part is a remaining region where a hole for embedding the through plug is removed, and is in contact with the through plug through the conductive buffer film or directly. The through plug wiring according to any one of claims 1 to 5.
JP2008146602A 2008-06-04 2008-06-04 Through plug wire Pending JP2009295719A (en)

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JP2011192662A (en) * 2010-03-03 2011-09-29 Napura:Kk Substrate for electronic device and electronic device
US8415784B2 (en) 2009-06-02 2013-04-09 Napra Co., Ltd. Electronic device, conductive composition, metal filling apparatus, and electronic device manufacturing method
JP2014512692A (en) * 2011-04-22 2014-05-22 テセラ インコーポレイテッド Vias in porous substrates
JP2014187404A (en) * 2014-07-08 2014-10-02 Fujikura Ltd Method of manufacturing through wiring board
US9312207B2 (en) 2014-03-14 2016-04-12 Kabushiki Kaisha Toshiba Semiconductor device
JP2022520481A (en) * 2019-02-18 2022-03-30 長江存儲科技有限責任公司 New Silicon Penetration Contact Structure and How to Form It
US11721628B2 (en) 2019-07-23 2023-08-08 Samsung Electronics Co., Ltd. Semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8415784B2 (en) 2009-06-02 2013-04-09 Napra Co., Ltd. Electronic device, conductive composition, metal filling apparatus, and electronic device manufacturing method
US8759211B2 (en) 2009-06-02 2014-06-24 Napra Co., Ltd. Electronic device, conductive composition, metal filling apparatus, and electronic device manufacturing method
JP2011192662A (en) * 2010-03-03 2011-09-29 Napura:Kk Substrate for electronic device and electronic device
JP2014512692A (en) * 2011-04-22 2014-05-22 テセラ インコーポレイテッド Vias in porous substrates
US9455181B2 (en) 2011-04-22 2016-09-27 Tessera, Inc. Vias in porous substrates
US9312207B2 (en) 2014-03-14 2016-04-12 Kabushiki Kaisha Toshiba Semiconductor device
JP2014187404A (en) * 2014-07-08 2014-10-02 Fujikura Ltd Method of manufacturing through wiring board
JP2022520481A (en) * 2019-02-18 2022-03-30 長江存儲科技有限責任公司 New Silicon Penetration Contact Structure and How to Form It
US11710679B2 (en) 2019-02-18 2023-07-25 Yangtze Memory Technologies Co., Ltd. Through silicon contact structure and method of forming the same
US11721609B2 (en) 2019-02-18 2023-08-08 Yangtze Memory Technologies Co., Ltd. Through silicon contact structure and method of forming the same
US11721628B2 (en) 2019-07-23 2023-08-08 Samsung Electronics Co., Ltd. Semiconductor device

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