JP2009295570A - Electrostatic discharge protection device for low-temperature co-fire ceramic, and manufacturing method thereof - Google Patents

Electrostatic discharge protection device for low-temperature co-fire ceramic, and manufacturing method thereof Download PDF

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JP2009295570A
JP2009295570A JP2009057020A JP2009057020A JP2009295570A JP 2009295570 A JP2009295570 A JP 2009295570A JP 2009057020 A JP2009057020 A JP 2009057020A JP 2009057020 A JP2009057020 A JP 2009057020A JP 2009295570 A JP2009295570 A JP 2009295570A
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patterned conductor
material layer
electrode material
conductor electrode
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Te-Pang Liu
テパン リュ，
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Inpaq Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01T—SPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES
    • H01T4/00—Overvoltage arresters using spark gaps
    • H01T4/10—Overvoltage arresters using spark gaps having a single gap or a plurality of gaps in parallel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01T—SPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES
    • H01T4/00—Overvoltage arresters using spark gaps
    • H01T4/10—Overvoltage arresters using spark gaps having a single gap or a plurality of gaps in parallel
    • H01T4/12—Overvoltage arresters using spark gaps having a single gap or a plurality of gaps in parallel hermetically sealed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01T—SPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES
    • H01T21/00—Apparatus or processes specially adapted for the manufacture or maintenance of spark gaps or sparking plugs
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic discharge protection device for low-temperature co-fire ceramic (LTCC), and a manufacturing method thereof. <P>SOLUTION: The electrostatic discharge protection device comprises a low-temperature co-fire ceramic film including a first patterned conductor electrode material layer, a second patterned conductor electrode material layer, and at least one via hole for exposing both a part of the first patterned conductor electrode material layer and a part of the second patterned conductor electrode material. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、静電放電保護装置及びその製造方法に関し、特に、低温共焼結セラミックの静電放電保護装置及びその製造方法に関するものである。   The present invention relates to an electrostatic discharge protection device and a manufacturing method thereof, and more particularly, to an electrostatic discharge protection device of a low temperature co-sintered ceramic and a manufacturing method thereof.

過電圧保護や放電保護の素子は、電子製品を保護するために、又は電圧異常や静電放電(Ｅｌｅｃｔｒｏ−Ｓｔａｔｉｃ Ｄｉｓｃｈａｒｇｅ，ＥＳＤ)による電子製品における素子の破壊により電子製品が故障して寿命が短縮することを回避するために、様々な電子製品の電気回路に広く適用されている。特に、ＥＳＤに対する保護設計は、電子製品の基本的な共通要求となっている。   Overvoltage protection and discharge protection elements are used to protect electronic products, or due to breakdown of the electronic products due to voltage abnormalities or electrostatic discharge (Electro-Static Discharge, ESD), the electronic products fail and their life is shortened. In order to avoid this, it is widely applied to electric circuits of various electronic products. In particular, ESD protection design is a basic common requirement for electronic products.

電子製品において耐ＥＳＤ性を備えるために、電気回路の保護設計としては、例えば、過渡電圧抑制ダイオード(Ｔｒａｎｓｉｅｎｔ Ｖｏｌｔａｇｅ Ｓｕｐｐｒｅｓｓ Ｄｉｏｄｅ，ＴＶＳＤ)素子や、積層バリスタ(Ｍｕｌｔｉ−Ｌａｙｅｒ Ｖａｒｉｓｔｏｒ，ＭＬＶ)素子等の種々のＥＳＤ保護素子が開発されている。さらに、ＥＳＤに対する保護設計上の各種各様の課題を解決するために、電気回路の設計としては、例えば、シールド(Ｓｈｉｅｌｄｉｎｇ)保護、ギャップ放電(Ｇａｐ Ｄｉｓｃｈａｒｇｅ)や、キャパシタ(Ｃａｐａｃｉｔｏｒ)充放電などの様々な手段が開発されている。特開ＪＰ１９９５−２４５８７８号公報においても、電子製品を保護するためのマイクロギャップを有する過電圧保護装置が開示されている。   In order to provide ESD resistance in electronic products, examples of protection designs for electric circuits include various elements such as a transient voltage suppression diode (TVSD) element and a multi-layer varistor (MLV) element. ESD protection elements have been developed. Furthermore, in order to solve various problems related to ESD protection design, electrical circuit design includes, for example, shielding protection, gap discharge, and capacitor charging / discharging. Various means have been developed. Japanese Patent Application Laid-Open No. JP-P1995-245878 also discloses an overvoltage protection device having a micro gap for protecting an electronic product.

本発明は、第１のパターン化された導体電極材料層と、第２のパターン化された導体電極材料層と、上記第１のパターン化された導体電極材料層の一部及び上記第２のパターン化された導体電極材料層の一部をともに露出させる少なくとも一つのビアホールとを有する低温共焼結セラミックフィルムを備える静電放電保護装置を提供することを目的の一つとする。   The present invention provides a first patterned conductor electrode material layer, a second patterned conductor electrode material layer, a part of the first patterned conductor electrode material layer, and the second It is an object of the present invention to provide an electrostatic discharge protection device including a low-temperature co-sintered ceramic film having at least one via hole exposing a part of a patterned conductor electrode material layer together.

また、本発明は、第１のパターン化された導体電極材料層を有する第１の低温共焼結セラミックフィルムを用意する工程と、少なくとも一つのビアホールを有する第２の低温共焼結セラミックフィルムを用意する工程と、上記第２の低温共焼結セラミックフィルムを上記第１の低温共焼結セラミックフィルムに被覆する工程と、上記少なくとも一つのビアホールの中に揮発性材料を充填する工程と、第２のパターン化された導体電極材料層を有する第３の低温共焼結セラミックフィルムを用意する工程と、上記第３の低温共焼結セラミックフィルムを上記第２の低温共焼結セラミックフィルムに被覆する工程と、上記揮発性材料を揮発させて、上記第１のパターン化導体電極材料層の一部及び上記第２のパターン化導体電極材料層の一部を露出させる少なくとも一つのガスギャップが形成されるように、上記第１の低温共焼結セラミックフィルム、上記第２の低温共焼結セラミックフィルム、及び上記第３の低温共焼結セラミックフィルムを共焼結する工程とを含む静電放電保護装置の製造方法を提供する。   The present invention also includes a step of preparing a first low temperature co-sintered ceramic film having a first patterned conductor electrode material layer, and a second low temperature co-sintered ceramic film having at least one via hole. A step of preparing, a step of coating the first low-temperature co-sintered ceramic film with the second low-temperature co-sintered ceramic film, a step of filling the at least one via hole with a volatile material, Preparing a third low-temperature co-sintered ceramic film having two patterned conductor electrode material layers, and coating the second low-temperature co-sintered ceramic film on the second low-temperature co-sintered ceramic film And volatilizing the volatile material to expose part of the first patterned conductor electrode material layer and part of the second patterned conductor electrode material layer. Co-sintering the first low-temperature co-sintered ceramic film, the second low-temperature co-sintered ceramic film, and the third low-temperature co-sintered ceramic film so that at least one gas gap is formed. The manufacturing method of the electrostatic discharge protection apparatus including the process to perform is provided.

本発明の一つの特徴によれば、本発明に係る静電放電保護装置は、電極間のピッチを５〜３０μｍという寸法範囲に容易に制御することができる。   According to one aspect of the present invention, the electrostatic discharge protection device according to the present invention can easily control the pitch between the electrodes to a dimensional range of 5 to 30 μm.

本発明の他の特徴によれば、本発明に係る静電放電保護装置のガスギャップは、第１のパターン化された導体電極の一端及び第２のパターン化された導体電極の一端を露出させるもので、上記第１のパターン化された導体電極の一端の長さ(Ｌ２)よりも、そして上記第２のパターン化された導体電極の一端の長さ(図示せず)よりも大きい長さ(Ｌ１)を有するとともに、上記第１のパターン化された導体電極の一端の幅(Ｗ２)よりも、そして上記第２のパターン化された導体電極の一端の幅(図示せず)よりも大きい幅(Ｗ１)を有する。これにより、それらの電極が上記ガスギャップにおいて放電することができ、電子製品が保護される。   According to another aspect of the present invention, the gas gap of the electrostatic discharge protection device according to the present invention exposes one end of the first patterned conductor electrode and one end of the second patterned conductor electrode. And a length greater than the length (L2) of one end of the first patterned conductor electrode and greater than the length (not shown) of one end of the second patterned conductor electrode. (L1) and larger than the width (W2) of one end of the first patterned conductor electrode and larger than the width (not shown) of one end of the second patterned conductor electrode. It has a width (W1). Thereby, those electrodes can discharge in the said gas gap, and an electronic product is protected.

本発明の他の特徴によれば、本発明に係る静電放電保護装置は、上記第１のパターン化された導体電極材料層のパターン及び上記第２のパターン化された導体電極材料層のパターンを、様々な寸法の要求に対応できるように変化させてもよい。   According to another aspect of the present invention, an electrostatic discharge protection device according to the present invention includes a pattern of the first patterned conductor electrode material layer and a pattern of the second patterned conductor electrode material layer. May be varied to accommodate various dimensional requirements.

本発明の他の特徴によれば、本発明に係る静電放電保護装置は、ガスギャップの寸法が非常に微小であるので、ブレークダウン電圧が有効に低減でき、このような簡単な構造により、ＥＳＤの低圧保護の設計要求が達成される。   According to another aspect of the present invention, the electrostatic discharge protection device according to the present invention has a very small gas gap dimension, so that the breakdown voltage can be effectively reduced. With such a simple structure, The design requirements for ESD low pressure protection are achieved.

本発明の更なる特徴及び機能は、以下の実施形態及び図面の説明によりさらに明らかになるであろう。   Further features and functions of the present invention will become more apparent from the following description of embodiments and drawings.

Ａ及びＢはそれぞれ、本発明に係る第１の実施形態における第１の低温セラミック共焼結フィルムを示す平面図及び断面図である。A and B are a plan view and a cross-sectional view, respectively, showing a first low-temperature ceramic co-sintered film in the first embodiment according to the present invention. Ａ及びＢはそれぞれ、本発明に係る第１の実施形態における第２の低温セラミック共焼結フィルムを示す平面図及び側断面図である。A and B are respectively a plan view and a side sectional view showing a second low-temperature ceramic co-sintered film in the first embodiment according to the present invention. Ａ及びＢはそれぞれ、本発明に係る第１の実施形態により、揮発性材料が充填された後、上記第２の低温セラミック共焼結フィルムが上記第１の低温セラミック共焼結フィルムに被覆していることを示す平面図及び側断面図である。A and B are respectively coated with the first low-temperature ceramic co-sintered film by the second low-temperature ceramic co-sintered film after being filled with a volatile material according to the first embodiment of the present invention. It is the top view and side sectional view which show that it is. Ａ及びＢはそれぞれ、本発明に係る第１の実施形態により、第３の低温セラミック共焼結フィルムが上記第２の低温セラミック共焼結フィルムに被覆していることを示す平面図及び側断面図である。A and B are respectively a plan view and a side cross-section showing that a third low-temperature ceramic co-sintered film is coated on the second low-temperature ceramic co-sintered film according to the first embodiment of the present invention. FIG. Ａ及びＢはそれぞれ、本発明に係る第１の実施形態における静電放電保護装置のチップを示す平面図及び側断面図である。A and B are a plan view and a side sectional view, respectively, showing a chip of the electrostatic discharge protection device according to the first embodiment of the present invention. Ａ及びＢはそれぞれ、本発明に係る第１の実施形態における少なくとも一つの第１の端部電極及び少なくとも一つの第２の端部電極を示す平面図及び正面図である。A and B are a plan view and a front view, respectively, showing at least one first end electrode and at least one second end electrode in the first embodiment according to the present invention. Ａ及びＢはそれぞれ、本発明に係る第２の実施形態における第１の低温セラミック共焼結フィルムを示す平面図及び側断面図である。A and B are respectively a plan view and a side sectional view showing a first low-temperature ceramic co-sintered film in the second embodiment according to the present invention. Ａ及びＢはそれぞれ、本発明に係る第２の実施形態における第２の低温セラミック共焼結フィルムを示す平面図及び側断面図である。A and B are a plan view and a side sectional view, respectively, showing a second low-temperature ceramic co-sintered film according to the second embodiment of the present invention. Ａ及びＢはそれぞれ、本発明に係る第２の実施形態により、揮発性材料が充填された後、上記第２の低温セラミック共焼結フィルムが上記第１の低温セラミック共焼結フィルムに被覆していることを示す平面図及び側断面図である。A and B are respectively coated with the first low-temperature ceramic co-sintered film by the second low-temperature ceramic co-sintered film after being filled with a volatile material according to the second embodiment of the present invention. It is the top view and side sectional view which show that it is. Ａ及びＢはそれぞれ、本発明に係る第２の実施形態により、第３の低温セラミック共焼結フィルムが上記第２の低温セラミック共焼結フィルムに被覆していることを示す平面図及び側断面図である。A and B are a plan view and a side cross-sectional view, respectively, showing that the third low-temperature ceramic co-sintered film is coated on the second low-temperature ceramic co-sintered film according to the second embodiment of the present invention. FIG. Ａ及びＢはそれぞれ、本発明に係る第２の実施形態における静電放電保護装置のチップを示す平面図及び側断面図である。A and B are respectively a plan view and a side sectional view showing a chip of an electrostatic discharge protection device according to a second embodiment of the present invention. Ａ及びＢはそれぞれ、本発明に係る上記第２の実施形態における少なくとも一つの第１の端部電極及び少なくとも一つの第２の端部電極を示す平面図及び正面図である。A and B are respectively a plan view and a front view showing at least one first end electrode and at least one second end electrode in the second embodiment according to the present invention. Ａ及びＢはそれぞれ、本発明による静電放電保護装置のガスギャップを示す拡大図である。A and B are enlarged views each showing a gas gap of the electrostatic discharge protection device according to the present invention.

１００…第１の低温共焼結セラミックフィルム、１０１…第１のパターン化された導体電極材料層、１０２…第２の低温共焼結セラミックフィルム、１０３…ビアホール、１０４…揮発性材料、１０５…第３の低温共焼結セラミックフィルム、１０６…第２のパターン化された導体電極材料層、１０７ａ，１０７ｂ…端部電極、１０８…ガスギャップ、２００…第１の低温共焼結セラミックフィルム、２０１…第１のパターン化された導体電極材料層、２０２…第２の低温共焼結セラミックフィルム、２０３…ビアホール、２０４…揮発性材料、２０５…第３の低温共焼結セラミックフィルム、２０６…第２のパターン化された導体電極材料層、２０７ａ，２０７ｂ…端部電極、２０８…ガスギャップ、３０８…ガスギャップ DESCRIPTION OF SYMBOLS 100 ... 1st low temperature co-sintered ceramic film, 101 ... 1st patterned conductor electrode material layer, 102 ... 2nd low temperature co-sintered ceramic film, 103 ... Via hole, 104 ... Volatile material, 105 ... Third low temperature co-sintered ceramic film, 106 ... second patterned conductor electrode material layer, 107a, 107b ... end electrodes, 108 ... gas gap, 200 ... first low temperature co-sintered ceramic film, 201 ... first patterned conductor electrode material layer, 202 ... second low temperature co-sintered ceramic film, 203 ... via hole, 204 ... volatile material, 205 ... third low temperature co-sintered ceramic film, 206 ... first 2 patterned conductor electrode material layers, 207a, 207b ... end electrodes, 208 ... gas gap, 308 ... gas gap

図１Ａ〜６Ｂは本発明の第１の実施形態における静電放電保護装置の構成を模式的に示す図である。   1A to 6B are diagrams schematically showing a configuration of an electrostatic discharge protection device according to a first embodiment of the present invention.

図１Ａ及び１Ｂに示すように、上記静電放電保護装置は、第１のパターン化された導体電極材料層１０１を有する第１の低温セラミック共焼結フィルム１００を備えている。上記第１のパターン化された導体電極材料層１０１は、印刷により上記第１の低温セラミック共焼結フィルム１００に形成されており、第１の方向に配置されている。   As shown in FIGS. 1A and 1B, the electrostatic discharge protection device includes a first low-temperature ceramic co-sintered film 100 having a first patterned conductor electrode material layer 101. The first patterned conductor electrode material layer 101 is formed on the first low-temperature ceramic co-sintered film 100 by printing, and is disposed in the first direction.

さらに、上記静電放電保護装置は、図２Ａ及び２Ｂに示すように、少なくとも一つのビアホール１０３を有する第２の低温共焼結セラミックフィルム１０２を備えている。上記少なくとも一つのビアホール１０３は予めパンチャーでフィルムを打ち抜くことにより形成されている。また、上記第２の低温共焼結セラミックフィルム１０２は上記第１の低温共焼結セラミックフィルム１００に被覆する。上記第１の低温共焼結セラミックフィルム１００と上記第２の低温共焼結セラミックフィルム１０２は、位置を合わせて積層されている。   Further, the electrostatic discharge protection device includes a second low-temperature co-sintered ceramic film 102 having at least one via hole 103, as shown in FIGS. 2A and 2B. The at least one via hole 103 is formed by punching a film with a puncher in advance. The second low temperature co-sintered ceramic film 102 is coated on the first low temperature co-sintered ceramic film 100. The first low-temperature co-sintered ceramic film 100 and the second low-temperature co-sintered ceramic film 102 are laminated at the same position.

図３Ａ及び３Ｂに示すように、上記少なくとも一つのビアホール１０３の中に揮発性材料１０４が充填されている。   As shown in FIGS. 3A and 3B, the at least one via hole 103 is filled with a volatile material 104.

上記静電放電保護装置は、図４Ａ及び４Ｂに示すように、第２のパターン化された導体電極材料層１０６を有する第３の低温共焼結セラミックフィルム１０５を備えている。上記第２のパターン化された導体電極材料層１０６は、印刷により上記第３の低温セラミック共焼結フィルム１０５に形成されており、上記第１の方向と同様な第２の方向に配置されている。また、上記第３の低温共焼結セラミックフィルム１０５は上記第２の低温共焼結セラミックフィルム１０２に被覆しており、上記第２の低温共焼結セラミックフィルム１０２と上記第３の低温共焼結セラミックフィルム１０５とが、位置を合わせて積層されている。圧力（例えば、水圧）により、上記第１の低温共焼結セラミックフィルム１００、上記第２の低温共焼結セラミックフィルム１０２、及び上記第３の低温共焼結セラミックフィルム１０５を緊密に結合させる。   The electrostatic discharge protection apparatus includes a third low-temperature co-sintered ceramic film 105 having a second patterned conductor electrode material layer 106 as shown in FIGS. 4A and 4B. The second patterned conductor electrode material layer 106 is formed on the third low-temperature ceramic co-sintered film 105 by printing, and is arranged in a second direction similar to the first direction. Yes. The third low-temperature co-sintered ceramic film 105 is coated on the second low-temperature co-sintered ceramic film 102, and the second low-temperature co-sintered ceramic film 102 and the third low-temperature co-sintered ceramic film 102 The sintered ceramic film 105 is laminated with the same position. The first low-temperature co-sintered ceramic film 100, the second low-temperature co-sintered ceramic film 102, and the third low-temperature co-sintered ceramic film 105 are tightly bonded by pressure (for example, water pressure).

図５Ａ及び５Ｂに示すように、形成されたフィルム構造を複数のチップの形態に分割し、分割成型後に上記チップを共焼結し、この燒結中に、上記揮発性材料１０４が揮発して、ガスギャップ１０８が形成される。上記ガスギャップ１０８は上記フィルム構造に完全に包囲され、上記第１のパターン化された導体電極材料層１０１の一部と上記第２のパターン化された導体電極材料層１０６の一部を露出させる。   As shown in FIGS. 5A and 5B, the formed film structure is divided into a plurality of chip forms, the chips are co-sintered after divided molding, and during the sintering, the volatile material 104 is volatilized, A gas gap 108 is formed. The gas gap 108 is completely surrounded by the film structure, exposing a portion of the first patterned conductor electrode material layer 101 and a portion of the second patterned conductor electrode material layer 106. .

図６Ａ及び６Ｂに示すように、上記チップの両側において、電気メッキにより、上記第１のパターン化された導体電極材料層１０１に接続されている少なくとも一つの第１の端部電極１０７ａが形成され、また、上記第２のパターン化された導体電極材料層に接続されている少なくとも一つの第２の端部電極１０７ｂが形成されている。上記少なくとも一つの第１の端部電極１０７ａ及び上記少なくとも一つの第２の端部電極１０７ｂに、それぞれ少なくとも一つの半田界面層(図示せず)を形成することにより、上記静電放電保護装置を完成させる。   As shown in FIGS. 6A and 6B, at least one first end electrode 107a connected to the first patterned conductor electrode material layer 101 is formed on both sides of the chip by electroplating. Also, at least one second end electrode 107b connected to the second patterned conductor electrode material layer is formed. The electrostatic discharge protection device is formed by forming at least one solder interface layer (not shown) on each of the at least one first end electrode 107a and the at least one second end electrode 107b. Finalize.

図７Ａ〜１２Ｂは、本発明の第２の実施形態における静電放電保護装置の構成を模式的に示す図である。   7A to 12B are diagrams schematically illustrating the configuration of the electrostatic discharge protection device according to the second embodiment of the present invention.

図７Ａ及び７Ｂに示すように、上記静電放電保護装置は、第１のパターン化された導体電極材料層２０１を有する第１の低温セラミック共焼結フィルム２００を備えている。上記第１のパターン化された導体電極材料層２０１は、印刷により上記第１の低温セラミック共焼結フィルム２００に形成されており、第１の方向に配置されている。   As shown in FIGS. 7A and 7B, the electrostatic discharge protection device includes a first low-temperature ceramic co-sintered film 200 having a first patterned conductor electrode material layer 201. The first patterned conductor electrode material layer 201 is formed on the first low-temperature ceramic co-sintered film 200 by printing, and is disposed in the first direction.

上記静電放電保護装置は、さらに、図８Ａ及び８Ｂに示すように、少なくとも一つのビアホール２０３を有する第２の低温共焼結セラミックフィルム２０２を備えている。上記少なくとも一つのビアホール２０３は、予めパンチャーによりフィルムを打ち抜くことにより形成されている。また、上記第２の低温共焼結セラミックフィルム２０２は上記第１の低温共焼結セラミックフィルム２００に被覆する。上記第１の低温共焼結セラミックフィルム２００と上記第２の低温共焼結セラミックフィルム２０２は、位置を合わせて積層される。   The electrostatic discharge protection device further includes a second low-temperature co-sintered ceramic film 202 having at least one via hole 203 as shown in FIGS. 8A and 8B. The at least one via hole 203 is formed by punching a film in advance with a puncher. Further, the second low-temperature co-sintered ceramic film 202 is coated on the first low-temperature co-sintered ceramic film 200. The first low-temperature co-sintered ceramic film 200 and the second low-temperature co-sintered ceramic film 202 are laminated at the same position.

図９Ａ及び９Ｂに示すように、上記少なくとも一つのビアホール２０３の中に揮発性材料２０４が充填されている。   As shown in FIGS. 9A and 9B, the at least one via hole 203 is filled with a volatile material 204.

図１０Ａ及び１０Ｂに示すように、上記静電放電保護装置は、第２のパターン化された導体電極材料層２０６を有する第３の低温共焼結セラミックフィルム２０５も備えている。上記第２のパターン化された導体電極材料層２０６は印刷により上記第３の低温セラミック共焼結フィルム２０５に形成されており、上記第１の方向と異なっている第２の方向に配置されている。また、上記第３の低温共焼結セラミックフィルム２０５は上記第２の低温共焼結セラミックフィルム２０２に被覆する。上記第２の低温共焼結セラミックフィルム２０２と上記第３の低温共焼結セラミックフィルム２０５は、位置を合わせて積層されている。水圧により、上記第１の低温共焼結セラミックフィルム２００、上記第２の低温共焼結セラミックフィルム２０２、及び上記第３の低温共焼結セラミックフィルム２０５を緊密に結合させる。   As shown in FIGS. 10A and 10B, the electrostatic discharge protection device also includes a third low temperature co-sintered ceramic film 205 having a second patterned conductor electrode material layer 206. The second patterned conductor electrode material layer 206 is formed on the third low-temperature ceramic co-sintered film 205 by printing, and is disposed in a second direction different from the first direction. Yes. The third low temperature co-sintered ceramic film 205 is coated on the second low temperature co-sintered ceramic film 202. The second low-temperature co-sintered ceramic film 202 and the third low-temperature co-sintered ceramic film 205 are laminated at the same position. The first low-temperature co-sintered ceramic film 200, the second low-temperature co-sintered ceramic film 202, and the third low-temperature co-sintered ceramic film 205 are tightly bonded by water pressure.

図１１Ａ及び１１Ｂに示すように、形成されたフィルム結構を複数のチップの形態に分割し、分割成型後に上記チップを共焼結し、この燒結中に、上記揮発性材料２０４が揮発して、ガスギャップ２０８が形成される。上記ガスギャップ２０８は上記フィルム結構に完全に包囲され、上記第１のパターン化された導体電極材料層２０１の一部と上記第２のパターン化された導体電極材料層２０６の一部を露出させる。   As shown in FIGS. 11A and 11B, the formed film structure is divided into a plurality of chip forms, the chips are co-sintered after divided molding, and during the sintering, the volatile material 204 is volatilized, A gas gap 208 is formed. The gas gap 208 is completely surrounded by the film structure and exposes a portion of the first patterned conductor electrode material layer 201 and a portion of the second patterned conductor electrode material layer 206. .

図１２Ａ及び１２Ｂに示すように、上記チップの両側において、電気メッキにより、上記第１のパターン化された導体電極材料層２０１に接続されている少なくとも一つの第１の端部電極２０７ａが形成され、また、上記第２のパターン化された導体電極材料層２０６に接続されている少なくとも一つの第２の端部電極２０７ｂが形成されている。上記少なくとも一つの第１の端部電極２０７ａと上記少なくとも一つの第２の端部電極２０７ｂに、それぞれ少なくとも一つの半田界面層(図示せず)を形成することにより、上記静電放電保護装置を完成させる。   As shown in FIGS. 12A and 12B, at least one first end electrode 207a connected to the first patterned conductor electrode material layer 201 is formed by electroplating on both sides of the chip. Also, at least one second end electrode 207b connected to the second patterned conductor electrode material layer 206 is formed. The electrostatic discharge protection device is formed by forming at least one solder interface layer (not shown) on each of the at least one first end electrode 207a and the at least one second end electrode 207b. Finalize.

本発明による静電放電保護装置は、電極間のピッチを５〜３０μｍという寸法範囲に容易に制御することができる。   The electrostatic discharge protection device according to the present invention can easily control the pitch between the electrodes within a dimensional range of 5 to 30 μm.

図１３Ａ及び１３Ｂは、本発明による静電放電保護装置のガスギャップの拡大図である。上記ガスギャップ(３０８)は、図１３Ａに示すように、第１のパターン化された導体電極の一端及び第２のパターン化された導体電極の一端を露出させるものであり、上記第１のパターン化された導体電極の一端の長さ(Ｌ２)よりも、そして上記第２のパターン化された導体電極の一端の長さ(図示せず)よりも大きい長さ(Ｌ１)を有するとともに、図１３Ｂに示すように、上記該第１のパターン化された導体電極の一端の幅(Ｗ２)よりも、そして上記第２のパターン化された導体電極の一端の幅(図示せず)よりも大きい幅(Ｗ１)を有する。   13A and 13B are enlarged views of a gas gap of the electrostatic discharge protection device according to the present invention. The gas gap 308 exposes one end of the first patterned conductor electrode and one end of the second patterned conductor electrode, as shown in FIG. 13A. A length (L1) greater than the length (L2) of one end of the formed conductor electrode and a length (L1) of one end of the second patterned conductor electrode (not shown); 13B, the width of one end of the first patterned conductor electrode (W2) is larger than the width of one end of the second patterned conductor electrode (not shown). It has a width (W1).

本発明による静電放電保護装置は、必要に応じて、上記第１のパターン化された導体電極材料層のパターン及び上記第２のパターン化された導体電極材料層のパターンを、様々な寸法の要求に対応できるように変化させてもよい。   The electrostatic discharge protection device according to the present invention can be configured to allow the pattern of the first patterned conductor electrode material layer and the pattern of the second patterned conductor electrode material layer to have various dimensions as necessary. It may be changed to meet the demand.

また、本発明による静電放電保護装置は、ガスギャップの寸法が非常に微小であるので、ブレークダウン電圧が有効に低減でき、このような簡単な構造により、ＥＳＤの低圧保護の設計要求が達成される。   In addition, since the electrostatic discharge protection device according to the present invention has a very small gas gap size, the breakdown voltage can be effectively reduced, and such a simple structure achieves the design requirements for ESD low voltage protection. Is done.

以上に説明したのは、本発明に係る好適な実施形態に過ぎず、本発明の請求の範囲を限定するものではない。本発明に記載の要旨から逸脱しない範囲で達成された他の等価な変更や修飾は、すべて後述する請求の範囲内に含まれるべきである。   What has been described above is only a preferred embodiment of the present invention, and does not limit the scope of the present invention. All other equivalent changes and modifications achieved without departing from the scope of the present invention should be included within the scope of the following claims.

Claims (16)

第１のパターン化された導体電極材料層と、第２のパターン化された導体電極材料層と、前記第１のパターン化された導体電極材料層と前記第２のパターン化された導体電極材料層を連通させ、前記第１のパターン化された導体電極材料層の一部及び前記第２のパターン化された導体電極材料層の一部を露出させる少なくとも一つのビアホールとを有する低温共焼結セラミックフィルムを備える静電放電保護装置。 A first patterned conductor electrode material layer; a second patterned conductor electrode material layer; the first patterned conductor electrode material layer; and the second patterned conductor electrode material. Low temperature co-sintering having at least one via hole communicating the layers and exposing a portion of the first patterned conductor electrode material layer and a portion of the second patterned conductor electrode material layer An electrostatic discharge protection device comprising a ceramic film. さらに、前記第１のパターン化された導体電極材料層に接続されている少なくとも一つの第１の端部電極を備える請求項１に記載の装置。 The apparatus of claim 1, further comprising at least one first end electrode connected to the first patterned conductor electrode material layer. さらに、前記第２のパターン化された導体電極材料層に接続されている少なくとも一つの第２の端部電極を備える請求項１に記載の装置。 The apparatus of claim 1, further comprising at least one second end electrode connected to the second patterned conductor electrode material layer. 前記第１のパターン化された導体電極材料層が第１の方向に配置され、前記第２のパターン化された導体電極材料層が第２の方向に配置される請求項１に記載の装置。 The apparatus of claim 1, wherein the first patterned conductor electrode material layer is disposed in a first direction and the second patterned conductor electrode material layer is disposed in a second direction. 前記第１の方向が前記第２の方向と同じである請求項４に記載の装置。 The apparatus of claim 4, wherein the first direction is the same as the second direction. 前記第１の方向が前記第２の方向と異なっている請求項４に記載の装置。 The apparatus of claim 4, wherein the first direction is different from the second direction. 前記少なくとも一つのビアホールは、前記第１のパターン化された導体電極材料層の電極の一部及び前記第２のパターン化された導体電極材料層の電極の一部を露出させる請求項１に記載の装置。 The said at least one via hole exposes a part of the electrode of the first patterned conductor electrode material layer and a part of the electrode of the second patterned conductor electrode material layer. Equipment. 前記少なくとも一つのビアホールは、前記第１のパターン化された導体電極材料層の電極の一部の長さよりも、そして前記第２のパターン化された導体電極材料層の電極の一部の長さよりも大きい長さを有するとともに、前記第１のパターン化された導体電極材料層の電極の一部の幅よりも、そして前記第２のパターン化された導体電極材料層の電極の一部の幅よりも大きい幅を有する請求項７に記載の装置。 The at least one via hole is longer than the length of a part of the electrode of the first patterned conductor electrode material layer and from the length of a part of the electrode of the second patterned conductor electrode material layer. And a width of a part of the electrode of the second patterned conductor electrode material layer and a width of a part of the electrode of the second patterned conductor electrode material layer. The device of claim 7 having a greater width. 第１のパターン化された導体電極材料層を有する第１の低温共焼結セラミックフィルムを用意する工程と、
少なくとも一つのビアホールを有する第２の低温共焼結セラミックフィルムを用意する工程と、
前記第２の低温共焼結セラミックフィルムを前記第１の低温共焼結セラミックフィルムに被覆する工程と、
前記少なくとも一つのビアホールの中に揮発性材料を充填する工程と、
第２のパターン化された導体電極材料層を有する第３の低温共焼結セラミックフィルムを用意する工程と、
前記第３の低温共焼結セラミックフィルムを前記第２の低温共焼結セラミックフィルムに被覆する工程と、
前記揮発性材料を揮発させて、前記第１のパターン化導体電極材料層の一部及び前記第２のパターン化導体電極材料層の一部を露出させる少なくとも一つのガスギャップが形成されるように、前記第１の低温共焼結セラミックフィルム、前記第２の低温共焼結セラミックフィルム、及び前記第３の低温共焼結セラミックフィルムを共焼結する工程と、
を含む静電放電保護装置の製造方法。 Providing a first low temperature co-sintered ceramic film having a first patterned conductor electrode material layer;
Providing a second low temperature co-sintered ceramic film having at least one via hole;
Coating the second low-temperature co-sintered ceramic film on the first low-temperature co-sintered ceramic film;
Filling the at least one via hole with a volatile material;
Providing a third low temperature co-sintered ceramic film having a second patterned conductor electrode material layer;
Coating the third low-temperature co-sintered ceramic film on the second low-temperature co-sintered ceramic film;
Volatilizing the volatile material to form at least one gas gap exposing a part of the first patterned conductor electrode material layer and a part of the second patterned conductor electrode material layer. Co-sintering the first low-temperature co-sintered ceramic film, the second low-temperature co-sintered ceramic film, and the third low-temperature co-sintered ceramic film;
The manufacturing method of the electrostatic discharge protection apparatus containing this. さらに、前記第１のパターン化導体電極材料層に接続されている少なくとも一つの第１の端部電極を形成する工程を含む請求項９に記載の方法。 The method of claim 9, further comprising forming at least one first end electrode connected to the first patterned conductor electrode material layer. さらに、前記第２のパターン化導体電極材料層に接続されている少なくとも一つの第２の端部電極を形成する工程を含む請求項９に記載の方法。 The method of claim 9, further comprising forming at least one second end electrode connected to the second patterned conductor electrode material layer. 前記第１のパターン化導体電極材料層が第１の方向に配置され、前記第２のパターン化導体電極材料層が第２の方向に配置される請求項９に記載の方法。 The method of claim 9, wherein the first patterned conductor electrode material layer is disposed in a first direction and the second patterned conductor electrode material layer is disposed in a second direction. 前記第１の方向が前記第２の方向と同じである請求項１２に記載の方法。 The method of claim 12, wherein the first direction is the same as the second direction. 前記第１の方向が前記第２の方向と異なっている請求項１２に記載の方法。 The method of claim 12, wherein the first direction is different from the second direction. 前記第１のパターン化導体電極材料層の一部に電極の一部が含まれ、前記第２のパターン化導体電極材料層の一部に電極の一部が含まれる請求項９に記載の方法。 The method according to claim 9, wherein a part of the first patterned conductor electrode material layer includes a part of an electrode, and a part of the second patterned conductor electrode material layer includes a part of an electrode. . 前記少なくとも一つのガスギャップは、前記第１のパターン化された導体電極材料層の前記電極の一部の長さよりも、そして前記第２のパターン化された導体電極材料層の前記電極の一部の長さよりも大きい長さを有するとともに、前記第１のパターン化された導体電極材料層の前記電極の一部の幅よりも、そして前記第２のパターン化された導体電極材料層の前記電極の一部の幅よりも大きい幅を有する請求項１５に記載の方法。 The at least one gas gap is greater than the length of a portion of the electrode of the first patterned conductor electrode material layer and a portion of the electrode of the second patterned conductor electrode material layer. The electrode of the second patterned conductor electrode material layer having a length greater than the length of the first patterned conductor electrode material layer and a width of a portion of the electrode of the first patterned conductor electrode material layer. The method of claim 15 having a width that is greater than a width of a portion of the.
JP2009057020A 2008-06-02 2009-03-10 Electrostatic discharge protection device for low-temperature co-fire ceramic, and manufacturing method thereof Pending JP2009295570A (en)

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JP2019509607A (en) * 2016-03-24 2019-04-04 ティーディーケイ・エレクトロニクス・アクチェンゲゼルシャフトＴｄｋ Ｅｌｅｃｔｒｏｎｉｃｓ Ａｇ Lightning arrester manufacturing method and lightning arrester
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JP2019509607A (en) * 2016-03-24 2019-04-04 ティーディーケイ・エレクトロニクス・アクチェンゲゼルシャフトＴｄｋ Ｅｌｅｃｔｒｏｎｉｃｓ Ａｇ Lightning arrester manufacturing method and lightning arrester
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