JP2009290545A - Information processing device and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a processing rate in communication by SBP2 in compliance with IEEE1394. <P>SOLUTION: An OHCI section of LSI includes an OHCI unit corresponding to an earlier version of OHCI, and an SBP2 unit for data transmission and reception via hardware specialized for SBP2. Then, when transferring Read data and Write data by SBP2, a predetermined sequence in its transaction is executed by inter-hardware communication between the SBP2 unit and an Initiator with no help by software. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus configured to execute data transfer under a data interface standard such as IEEE 1394, and an information processing method corresponding to such an information processing apparatus.

IEEE 1394 is known as one of data interface standards.
In addition, at present, OHCI (Open Host Controller Interface) is often implemented on IEEE1394. For example, by making the IEEE 1394 hardware configuration (such as a communication board) included in a device compliant with OHCI, the register configuration, data structure, and the like are shared, and for example, data transfer is controlled in an equivalent manner from the viewpoint of software. In addition, depending on the driver, various higher-level communication protocols that operate on IEEE 1394 can be supported, thereby having a wide versatility.

Patent Document 1 discloses a technique that uses an existing large capacity holding circuit as a buffer in order to improve the speed of asynchronous transfer in IEEE1394.
Patent Document 2 describes an interface device for IEEE1394 digital serial data using OHCI (1394OHCI).

JP 2002-135270 A JP 2001-326670 A

For example, as disclosed in Patent Document 1, in the data transfer by the data interface, improvement and speeding up of the transfer speed are always one main problem.
The object of the present invention is to improve the data transfer rate in a data interface environment according to a predetermined standard, for example.

In view of the above-described problems, the present invention is configured as an information processing apparatus as follows.
That is, data is transmitted between an external bus corresponding to the data interface standard and an internal bus according to the predetermined standard, which is formed in accordance with a predetermined common standard defined under a predetermined data interface standard. The first transmission unit provided in this way, and provided between the external bus and the internal bus, performs data transmission corresponding to a predetermined communication protocol defined in the upper level of the data interface standard. When the first transmission unit is used, data transmission between hardware is performed between the self and the external bus without intervention of software for a predetermined sequence involving software processing. The second transmission unit configured as described above is provided.

  In the above configuration, first, by providing a first transmission unit corresponding to a predetermined common standard, software control of the first transmission unit enables versatile data transmission and communication. At the same time, by providing the second transmission unit, for a predetermined sequence corresponding to the higher-level communication protocol of the data interface standard of the present application, hardware that does not involve software between the second transmission unit and the external bus Inter-data transmission was performed.

  That is, in communication using the higher-level communication protocol, data transmission between hardware by the second transmission unit is appropriately executed, but this eliminates the software processing executed so far. . As a result, the data transfer rate is greatly improved.

  In this embodiment, the information processing apparatus according to the present invention is provided with a data transfer (transmission / reception) function corresponding to IEEE 1394 as a data communication (data interface) standard. In addition, it is assumed that a configuration conforming to a standardized standard called OHCI (Open Host Controller Interface) is adopted.

FIG. 1 shows an example of construction of a data transmission / reception system corresponding to the present embodiment.
The data transmission / reception system shown in this figure is composed of a video camera device 1 and an editing device 2.
The video camera device 1 includes an imaging unit, a video signal processing unit, a media drive, and the like. The video camera device 1 generates moving image data in a predetermined format from an image captured by the imaging unit, and the moving image data is stored in a predetermined medium (storage medium). ) Can be stored.
Furthermore, by implementing a data interface function according to a predetermined standard, data transfer including the moving image data and the like can be performed with other devices connected via the data interface. As one of such data interface functions, IEEE 1394 is implemented.
This figure shows a mode in which the video camera device 1 and the editing device 2 are connected by an IEEE 1394 data interface.

In this case, the editing apparatus 2 is a personal computer (hereinafter, the personal computer may be referred to as a PC), and has a video editing function by installing predetermined application software, for example. The editing apparatus 2 also has IEEE 1394 mounted as one of the data interface functions, and here is connected to the video camera apparatus 1 via IEEE 1394 as described above.
Note that the editing device 2 may be a dedicated editing device that is compatible with the video camera device 1, for example.

In this way, between the video camera device 1 and the editing device 2 connected via the IEEE 1394 in this way, for example, the editing device 2 side receives moving image data recorded on a medium loaded on the video camera device 1 side. Can be stored in a storage device such as an HDD (hard disk drive). On the editing apparatus 2 side, the moving image data stored in the HDD can be edited by using editing application software.
Conversely, data such as moving image data stored in the storage device on the editing device 2 side can be transferred to the video camera device 1 side and stored in, for example, a medium loaded in the video camera device 1. It is said.
In addition to video data transmission / reception, still image data and audio data can also be transmitted / received. In addition to such content data, various data and information such as programs and setting information are also available. It is possible to transmit and receive as necessary.

FIG. 2 shows a configuration example of a part related to the data interface function of IEEE 1394 in the video camera apparatus 1.
The CPU (Central Processing Unit) 11 is a so-called arithmetic device, and executes at least IEEE 1394 by executing a program stored in a secondary storage device represented by a ROM or HDD (not shown), for example. Executes control and processing related to communication. For this purpose, the video camera device 1 is installed with a driver (software) corresponding to, for example, IEEE 1394 (OHCI compliant) communication.

  The memory 12 is a RAM or the like, for example, and appropriately stores data to be handled by the CPU 11 according to the arithmetic processing of the CPU 11.

  In the video camera apparatus 1, the CPU 11 and the OHCI unit 13 correspond to the communication function based on IEEE1394. The buffer memory 15 is connected by the PCU bus 14.

The OHCI unit 13 is a part that controls data transmission and reception between, for example, a self-side node (in this case, the video camera device 1) on which the OHCI unit 13 is mounted and an external node connected by the IEEE 1394 bus 3. The That is, in this case, bidirectional data transmission is performed between the PCI bus 14 (internal bus) and the IEEE 1394 bus 3 (external bus). In addition, the OHCI unit 13 is configured to perform communication complying with and complying with OHCI.
The buffer memory 15 is a storage area in which data exchanged via the OHCI unit 13 can be written as necessary.
In practice, for example, the portion shown in this figure can be configured as a hardware component such as an LSI (Large Scale Integration).

  OHCI is, for example, a standardization standard (common standard) defined for the purpose of enabling communication by a general-purpose driver on the IEEE 1394 data interface standard, for example, without depending on a controller chip of a specific manufacturer (vendor). It is.

FIG. 3 shows a general internal configuration example as the OHCI unit 13.
As shown in this figure, the OHCI unit 13 includes an OHCI unit 21, a PCI bus interface block (PCI bus interface) 22, and an IEEE 1394 link layer / physical layer block (IEEE1394 Link and PHY) 23.

The PCI bus interface block 22 executes data input / output corresponding to the PCI bus standard between the PCI bus 14 and the OHCI unit 21.
The IEEE 1394 link layer / physical layer block (IEEE1394 Link and PHY) 23 executes data input / output corresponding to the IEEE 1394 standard between the OHCI unit 21 and the IEEE 1394 bus 3.

  As shown in the figure, the OHCI unit 21 includes an IT (Isochronous Transmit) DMA (Direct Memory Access) block, an IT FIFO (First-In First-Out) block, an AT (Asynchronous Transmit) Request DMA block, an AT Request FIFO block, AT Response DMA block, AT Response FIFO block, Physical Response Unit, AT Physical Response FIFO block, Physical Read Request Receive block, Physical Read Request FIFO block, Physical Write Request Receive block, Physical Write Request FIFO block, General Request Receive DMA block, AR (Asynchronous Receive) Request FIFO block, General Response Receive DMA block, AR Response FIFO block, IR (Isochronous Receive) DMA block, IR FIFO block, Self-ID Receive DMA block, Self-ID Receive FIFO block, internal register (Internal Registers) block is provided as shown. Here, a block having a DMA name (DMA block) is a DMA controller that executes DMA transfer, and a block having a FIFO name (FIFO block) is a controller that can execute data input / output by FIFO. .

The part composed of the IT DMA block and the IT FIFO block is a system that executes an operation corresponding to transmission by isochronous communication.
The part composed of the AT Request DMA block and the AT Request FIFO block is a system that executes an operation corresponding to the transmission of a request in asynchronous communication.
The part composed of the AT Response DMA block and the AT Response FIFO block is a system that executes an operation corresponding to the transmission of a response in asynchronous communication.
A part composed of the Physical Response Unit and the AT Physical Response FIFO block is a system that executes an operation corresponding to the transmission of Physical Response defined by OHCI.
The part composed of the Physical Read Request Receive block and the Physical Read Request FIFO block is a system that executes an operation corresponding to the reception of the Physical Read Request.
The part composed of the Physical Write Request Receive block and the Physical Write Request FIFO block is a system that executes an operation corresponding to the reception of the Physical Write Request.
The part composed of the General Request Receive DMA block and the AR Request FIFO block is a system for executing an operation corresponding to the asynchronous request reception.
The part composed of the General Response Receive DMA block and the AR Response FIFO block is a system that executes an operation corresponding to the response reception in the asynchronous mode.
The part composed of the IR DMA block and the IR FIFO block is a system that executes an operation corresponding to reception by isochronous communication.
The part composed of the Self-ID Receive DMA block and the Self-ID Receive FIFO block is a system that executes an operation corresponding to reception of Self-ID defined by OHCI.
An internal register is a part in which a predetermined value to be used for this operation is set according to transmission / reception of a request and a response.
These parts are controlled by software (driver). Note that the processing as software is realized by the CPU 11 executing the program, for example.

  As described above, when the IEEE 1394 data interface adopts a configuration compliant with OHCI, the software executes communication control using the OHCI unit 13 as described above. For this reason, since various communication methods and functions can be supported by software, this embodiment has very wide versatility and multifunctionality. This is one of the great advantages of adopting OHCI along with standardization.

  For example, a data communication protocol corresponding to a command set based on SCSI (Small Computer System Interface) called SBP (Serial Bus Protocol) -2 is known as one of the upper communication protocols of IEEE1394. In SBP-2, data transmission is performed by asynchronous communication. There is also known a communication protocol called AV / C Command that realizes synchronous transmission of video / audio data between AV devices by isochronous communication. If the OHCI unit 13 as shown in FIG. 3 is provided, for example, by installing (installing) software (driver) corresponding to SBP2, data communication by SBP-2 becomes possible, and AV / C Command By installing corresponding software, data transmission and communication according to AV / C Command can be executed.

However, data processing by the OHCI unit 13 involves software processing. For example, in the case of the SBP-2, it is necessary to form individual IEEE 1394 packets on the system memory. In this manner, software processing is involved in data transmission, so that, for example, the processing burden on the CPU becomes heavy, and the transfer speed is reduced accordingly.
This problem can be solved, for example, by adopting a high-performance CPU set that can execute processing at high speed. However, in devices such as the video camera device 1 of the present embodiment, for example, a low power consumption specification embedded device CPU is adopted with priority given to low power consumption. Such a CPU has a limit in processing performance, so the problem of a decrease in data transfer speed cannot be ignored.

Therefore, the present embodiment is configured such that, for example, a sufficiently high data transfer rate can be achieved even when a CPU with limited processing performance such as that for an embedded device with low power consumption is used. It was decided to. Hereinafter, this point will be described.
In the following description, a configuration corresponding to a case where communication is performed by SBP-2 in an OHCI-compliant IEEE 1394 data interface environment by the video camera device 1 of the present embodiment will be described as an example.

FIG. 4 shows an internal configuration example of the OHCI unit 13 provided in the present embodiment. In this figure, the same parts as those in FIG.
As shown in this figure, the OHCI unit 13 in this embodiment is a system corresponding to the OHCI bus between the PCI bus interface block 22 and the IEEE 1394 link layer / physical layer block (IEEE1394 Link and PHY) 23. In addition to the OHCI unit 21 (first transmission unit) shown in FIG. 3, an SBP2 unit 30 (second transmission unit) is provided.

The SBP2 unit 30 is a part configured to realize a predetermined function corresponding to the SBP2 by hardware.
In SBP2, with respect to a node referred to in IEEE 1394, a node that issues a command is referred to as an initiator, and a node that responds to the command is defined as a target. In SBP2, Command Block Agent and Management Agent are defined as an Agent function in Target. In the SBP2 unit 30 of the present embodiment, among these Agent functions, a function corresponding to the Command Block Agent is given.
In addition, although it is possible to give the SBP2 unit 30 a configuration corresponding to the Management Agent, in this case, the hardware configuration becomes complicated and the design / manufacturing becomes difficult. Therefore, the SBP2 unit 30 of the present embodiment has a hardware configuration that supports only the Command Block Agent in consideration of the balance between the complexity of the hardware configuration and the effectiveness of the data transfer rate improvement effect described later. It is said.

  As shown in the figure, the SBP2 unit 30 includes a Command Block Agent Unit 31, an AT FAM (File Access Mode) DMA block 32, a Header / Footer Add Block 33, an AT FAM FIFO block 34, an AR_FAM DMA block 35, a Header / Footer Remove Block 36, An AR_FAM FIFO block 37 is provided.

  The Command Block Agent Unit 31 is a core part of the SBP-2 compatible block 30 and is configured to execute processing corresponding to the Command Block Agent by hardware. For example, the Command Block Agent Unit 31 has a hardware configuration corresponding to the Fetch Agent State Machine and the Page Table FIFO in order to support the Command Block Agent.

The AT FAM DMA block 32, as a DMA controller, reads command block agent compatible data (Read data, etc.) to be transmitted in the file access mode by asynchronous transfer from the PCI bus side by DMA (Direct Memory Access), and the Header / Footer Pass to Add Block 33.
The header / footer add block 33 adds a header and a footer to the input data to form a packet structure defined by IEEE 1394, and outputs the packet structure to the AT FAM FIFO block 34. The footer includes a CRC which is an error check code. This CRC is also generated by, for example, the Header / Footer Add Block 33.
The AT FAM FIFO block 34 passes the input data as serial data to the IEEE 1394 link layer / physical layer block 23 to be transmitted on the IEEE 1394 bus 3.

Further, the AR_FAM FIFO block 37 inputs a command block agent compatible packet (Write data, Command Block ORB, Page Table, etc.) obtained from the IEEE 1394 bus 3 through the IEEE 1394 link layer / physical layer block 23, and generates a header / footer. Pass to Remove Block 36.
The Header / Footer Remove Block 36 removes the header and footer from the passed packet, extracts the data portion, and passes it to the AR_FAM DMA block 35.
The AR_FAM DMA block 35 passes the passed data to the PCI bus interface block 22 by DMA transfer. As a result, for example, data is written to the system memory (memory 12) connected to the PCI bus 14 by DMA without using the CPU 11.

  As can be seen from the above description, in the present embodiment, processing of adding and removing headers and footers of IEEE 1394 packets can be performed by hardware (Header / Footer Add Block 33, Header / Footer Remove Block 36). For example, when the OHCI unit 21 is used, this header and footer addition / removal processing also involves software processing. In other words, the processing for the header and footer is performed by hardware in this way, so that the time required for interrupt processing by software is shortened, thereby contributing to the improvement of the data transfer rate.

  Here, in the case of the present embodiment, as described above, the SBP2 unit 30 has a hardware configuration that supports only the Command Block Agent and does not support other Agents such as Management Agent, for example. Yes. For this reason, the OHCI unit 13 including the SBP2 unit 30 passes the packet corresponding to the Command Block Agent to the SBP2 unit 30, and appropriately handles the packet corresponding to the other Management Agent and the like. A mechanism is required to pass it to the OHCI unit 21 for processing without acceptance. In the present embodiment, this mechanism is given as follows.

First, in this embodiment, the Command Block Agent Unit 31 corresponding to the Command Block Agent (target agent function corresponding register) defined in the SBP 2 is processed.
The Command Block Agent Register is shown in FIG. As the Command Block Agent Register, AGENT_STATE, AGENT_RESET, ORB_POINTER, DOORBELL, and UNSOLICITED_STATUS_ENABLE are defined. Each register defines an offset address (Relative offset). AGENT_STATE is 00h, AGENT_RESET is 04h, ORB_POINTER is 08h, DOORBELL is 10h, and UNSOLICITED_STATUS_ENABLE is 14h.

The actual address of the Command Block Agent Register is obtained by adding the corresponding offset address shown in FIG. 5 to the command block agent (Fetch Agent CSR Base Address) in the Login Response defined by SBP2. That is, for example, in the case of DOORBELL, the value obtained by adding 10h to the value stored in the command block agent in Login Response is the address of the DOORBELL.
Management Agent controlled by software sets necessary register including Fetch Agent CSR base address register and sets start bit (login flag). The Command Block Agent Unit 31 of the SBP2 unit 30 is set in a receivable state according to the start bit being set.
Thereafter, the Command Block Agent Unit 31 determines whether or not the following conditions are satisfied, for example, in response to reception of a packet (quadlet write).
(Source ID == Initiator) && (Fetch Agent CSR base address + 00h ~ 1Ch)
That is, whether the received packet (quadlet write) is from the initiator node and whether it corresponds to the Command Block Agent Register, or whether it corresponds to a Register other than the Command Block Agent Register View.

Refer to the Fetch Agent CSR base address register for the above judgment. FIG. 6 shows the Fetch Agent CSR base address register (s) defined corresponding to the present embodiment.
The CSR base address register includes a Fetch Agent CSR base address Hi register shown in FIG. 6A and a Fetch Agent CSR base address Lo register shown in FIG.
The Fetch Agent CSR base address Hi register in FIG. 6A is 32 bits, and the upper 16 bits are a Node ID area and indicate the Node ID of the initiator currently logged in. The lower 16 bits of offset_hi are the upper 16 bits of the 48-bit Fetch Agent CSR base address. The 32 bits of the Fetch Agent CSR base address Lo register in FIG. 6B are set to offset_lo and become the lower 32 bits of the Fetch Agent CSR base address. That is, the Fetch Agent CSR base address Hi register offset_hi and the Fetch Agent CSR base address Lo register offset_lo represent the Fetch Agent CSR base address.

In the above condition determination, for example, first, the Node ID indicated by the upper 16 bits of the Fetch Agent CSR base address Hi register is compared with the source ID to determine whether or not they match.
Here, if the Node ID and the source ID do not match, the condition is not satisfied at this stage. Therefore, the received packet is passed to the OHCI unit 21 assuming that it corresponds to the Management Agent, for example.
On the other hand, if the Node ID and source ID match, it is next determined whether the address indicated by the received packet (quadlet write) is within the range of Fetch Agent CSR base address + 00h to 1Ch. . Also at this time, refer to the Fetch Agent CSR base address register, obtain the Fetch Agent CSR base address, and add 00h and 1Ch to this to identify the actual address as Fetch Agent CSR base address + 00h to 1Ch it can. Then, when the determination result that the address indicated by the received packet (quadlet write) is within the range of Fetch Agent CSR base address + 00h to 1Ch is obtained, the condition is satisfied for the first time, so the Command Block Agent Unit 31 The received packet is received and the process is executed. On the other hand, if it is determined that the address indicated by the received packet (quadlet write) is outside the range of Fetch Agent CSR base address + 00h to 1Ch, the condition will not be met. The packet is passed to the OHCI unit 21.
In the present embodiment, packet distribution is performed in this way.

  By providing the SBP2 unit 30 in the OHCI unit 13 as described above, the processing speed when executing data transfer according to Read, Write, etc. in the SBP2 is greatly improved as described below. Is.

Here, the sequence diagrams of FIG. 7 and FIG. 8 show the PC (editing apparatus 2) when the OHCI unit 13 of the embodiment shown in FIG. 4 above, that is, the OHCI unit 13 including the SBP corresponding block 30 is mounted. A transaction according to a Read command (File read Command) with the video camera device 1 is shown.
On the other hand, FIG. 9 and FIG. 10 show a PC and a video camera apparatus in the case of the example (general example) in which the general OHCI unit 13 not provided with the SBP2 unit 30 shown in FIG. The transaction according to File read Command with 1 is shown.
The file read command is a command for the initiator to read data from the target, and therefore the file data is transferred from the target to the initiator.

First, in FIG. 7 and FIG. 8 corresponding to the embodiment, PC Initiator, OHCI Unit, CBA Unit, Interrupt Handler, OHCI Task, Transaction Task, CBA Task, and other task are used as parts for executing each process constituting a transaction. It is shown.
In SBP2, an initiator that issues a command and a target that responds to the command are defined. In this case, the PC (editing device 2) is the initiator, and the video camera device 1 is the target.
PC Initiator represents a PC that is an initiator. Note that the PC Initiator here corresponds to hardware such as an IEEE1394 compatible communication board compliant with OHCI.

  The OHCI Unit is a part corresponding to the OHCI unit 21 in the OHCI unit 13 and is a process in the hardware layer. Therefore, data transmission (transfer) between the PC Initiator and the OHCI Unit is exchanged between hardware.

  The CBA Unit corresponds to the Command Block Agent (CBA) Unit 31, but may be treated as a corresponding part in the SBP 2 unit 21 of the OHCI unit 13 here. Since the SBP2 unit 21 is also configured by hardware (H / W), data transmission between the PC Initiator and the CBA Unit is also exchanged between the hardware.

  Interrupt Handler, OHCI Task, Transaction Task, CBA Task, and other task are tasks executed by the SBP2-compatible driver. Other task is a predetermined task other than Interrupt Handler, OHCI Task, Transaction Task, and CBA Task. That is, Interrupt Handler, OHCI Task, Transaction Task, CBA Task, and other task are software processes (tasks) corresponding to SBP2. Note that the Interrupt Handler, OHCI Task, Transaction Task, CBA Task, and other task are also referred to as OHCI software (OHCI S / W).

In FIG. 7 and FIG. 8, transactions corresponding to the File Read Command are sequentially divided by sequences seq1 to seq4.
First, the sequence seq1 is a process from when the PC Initiator transmits DoorBell to the Target until an ORB (Operation Request Block) is acquired on the Target side and held in the register.
In the sequence seq1, first, the PC Initiator transmits DoorBell. The OHCI unit 13 includes an OHCI unit 21 (OHCI Unit) and an SBP2 unit 30 (CBA Unit). The DoorBell receives the SBP2 unit 30 (CBA Unit). Subsequent transmission and reception with the PC Initiator side is also executed by the SBP2 unit 30 (CBA Unit) side.

Upon receiving DoorBell, the CBA Unit immediately returns a response to DoorBell to the PC Initiator without software intervention.
Next, the CBA Unit transmits an ORB Pointer Read Request (ORB Ptr Read Req). The PC Initiator returns an ORB Pointer Read Response as a response to the ORB Pointer Read Request. The CBA Unit receives this. In this ORB Pointer Read Response, a Memory Address on the PC Initiator side that fetches (or fetches) the ORB is shown.
Therefore, the CBA Unit transmits an ORB Read Request.
As a response to the ORB Read Request (ORB Read Response (ORB Read Resp)), the PC Initiator returns a Command Block ORB as a File Read Command.

FIG. 25 shows the structure of a Command Block ORB as a File Read Command.
4'hC3 is stored in cdb [0] of this Command Block ORB as shown in the figure, which indicates that the current Command Block ORB is a File Read Command.

  Here, it is assumed that 1 is stored in the area of p (page_table_present_bit: 1 bit) in the Command Block ORB. When p = 1, this indicates that the Page Table is held at the address indicated by data_descriptor in the current Command Block ORB.

The sequence seq2 is a process for the Target to acquire the Page Table from the PC Initiator side in response to the reception of the Command Block ORB.
Here, first, the CBA Unit transmits a Page Table Request to the address indicated by the data_descriptor.
In response to this, a Command Block ORB (ORB_page_table) of Page Table List is returned as a Page Table Response from the PC Initiator to the CBA Unit.
The CBA Unit holds the received Page Table List. At the same time, after setting a value according to the command, for example, DMA transfer is executed and written and held in the memory 12 (or buffer memory 15).
FIG. 26 shows the structure of the ORB_page_table. In this structure, at least the Command ORB and Page Table List shown in the figure are held in the memory 12 (or the buffer memory 15). This allows Target software to directly reference the Command ORB and Page Table List. For example, in the past, when the OHCI software tried to refer to the Command ORB and Page Table List, it was necessary to check and interpret the IEEE 1394 asynchronous packet. On the other hand, in this embodiment, the OHCI software accesses the memory area for the Command ORB and Page Table List specified in the memory 12, for example, what command is requested. Can recognize the contents of Page Table List.

Thereafter, the CBA Unit outputs (asserts) an Interrupt (interrupt request) to the Interrupt Handler of the OHCI software.
In response to this interrupt request, the OHCI software executes processing as shown. The OHCI software reads the Command ORB and Page Table List and performs error checking. Also, the memory address on the target side where the transmission descriptor and transmission data are stored is set. Use Output More descriptor to set this memory address. At this time, depending on the Output More descriptor, the memory address and the transfer data size are specified. In the present embodiment, the transmission destination address and the packet length are specified by the CBA Unit, and need not be specified by the OHCI software.
And set run bit. The context used at this time is SBP2 transmit Context.

The sequence seq3 (FIGS. 7 to 8) is a process for transferring file data (Read data: read data).
Read data is written into the buffer memory 15 without the addition of the header and footer of the IEEE 1394 packet by the processing of the OHCI software in the sequence seq2.
The CBA Unit reads the specified size of read data from the buffer memory 15 and transmits it to the PC Initiator as a Data Write Request. At this time, the read data passes through the AT FAM (File Access Mode) DMA block 32, the Header / Footer Add Block 33, and the AT FAM FIFO block 34 in the SBP2 unit 30, so that the header and footer of the IEEE 1394 packet are added. Thus, the data is transmitted to the PC Initiator via the IEEE 1394 bus 3.
When receiving the Data Write Request, the PC Initiator returns a Data Write Response (ACK: Acknowledge). In response to receiving this Data Write Response, the CBA Unit transmits the next Read data (Data Write Request). This is repeated according to the necessary read data transfer amount.

  When the CBA Unit completes the transmission of the last Read data (Data Write Request) and the reception of the Data Write Response in response thereto, it notifies the OHCI software of the normal end of the data transfer according to the File Read Command. For this purpose, the CBA Unit makes an interrupt request by Desc (Descriptor) Complete to the Interrupt Handler. In response to this, the OHCI software executes processing between tasks shown in the figure. Thereby, the read data in the memory is released.

  Also, as a sequence seq4, the CBA Unit returns a status (status block notice) to the PC Initiator after interruption by Desc (Descriptor) Complete. Next, when receiving the ACK in response to the status block notice from the PC Initiator, the CBA Unit outputs an interrupt request as ORB Complete to the Interrupt Handler. In response to this, a predetermined task in the OHCI software executes a process corresponding to ORB Complete as shown in the figure. Thereby, the transaction according to the File Read Command is completed.

  Next, as a comparison with the present embodiment shown in FIGS. 7 and 8, the same File Read Command in the case of the general example corresponding to the configuration of the OHCI unit 13 in FIG. The corresponding transaction will be described. For confirmation, the OHCI unit 13 as a general example shown in FIG. 3 includes only the OHCI unit 21 in which the SBP2 unit 30 is omitted. In the configuration of FIG. 4 corresponding to the embodiment, according to the fact that the OHCI unit 13 is provided with the OHCI unit 21 and the SBP2 unit 30, in FIG. 7 and FIG. Unit and CBA Unit were shown. On the other hand, in the general configuration of FIG. 3, as described above, the SBP2 unit 30 is omitted and only the OHCI unit 21 is provided, so that the hardware on the target side is only the OHCI unit.

9 and 10 also show the transactions corresponding to the File Read Command sequentially divided by sequences seq1 to seq4.
Similar to FIGS. 7 and 8, the sequence seq1 is used to acquire an ORB (Operation Request Block) on the Target side and hold it in the register in response to the PC Initiator sending DoorBell to the Target. It is processing.
Also in the sequence seq1 of FIG. 9, first, the PC Initiator transmits DoorBell.
In response to receiving DoorBell, the OHCI Unit outputs an interrupt request (Interrupt) to the Interrupt Handler. In response to this, the OHCI software executes processing as shown. In this process, according to the Write Response from the Transaction Task, the OHCI Unit returns a response (Write Response) in response to DoorBell to the PC Initiator.
Also, the CBA Task passes an ORB Pointer Request to the OHCI Unit in response to the TR_DATA.indicate being passed. In response to this, the OHCI Unit transmits an ORB Pointer Read to the PC Initiator. The PC Initiator returns an ORB Pointer Read Response as a response to the ORB Pointer Read Request. In response to receiving this, the OHCI Unit outputs an Interrupt to the Interrupt Handler. In response to this interrupt, the OHCI software executes the processing corresponding to the reception of the ORB Pointer Read Response as shown in the figure, and when it reaches the stage where TR_DATA.confirmation is received in the CBA Task, the CBA Task next Output ORB Read Request to OHCI Unit. In response to this, the OHCI Unit transmits an ORB Read Request to the PC Initiator.

As a response to the ORB Read Request (ORB Read Response (ORB Read Resp)), the PC Initiator returns a Command Block ORB as a File Read Command. The structure of the Command Block ORB as the File Read Command is as described above with reference to FIG.
Again, 1 is stored in the area of p (page_table_present_bit: 1bit) in the above Command Block ORB, indicating that the Page Table is held at the address indicated by the data_descriptor in the current Command Block ORB. It shall be.

  The OHCI Unit that has received the Command Block ORB also outputs an Interrupt to the Interrupt Handler. In response to this, the OHCI software executes processing corresponding to the reception of the Command Block ORB, and when it reaches the stage where TR_DATA.confirmation is received by the CBA Task, the next page table read request is sent from the CBA Task to the OHCI Unit. Send.

In sequence seq2 (Process for Target to acquire Page Table from PC Initiator side), OHCI Unit first sends Page Table Read Request to PC Initiator in response to receiving Page Table Read Request from CBA Task. Send.
In response to this, a Command Block ORB (ORB_page_table) of Page Table List is returned as a Page Table Response from the PC Initiator to the OHCI Unit.
The OHCI unit outputs an interrupt in response to reception of the command block ORB (page table list), and causes the OHCI software to execute processing in response to reception of the command block ORB (page table list). The OHCI software reads the Command ORB and Page Table List and performs error checking. Also, the memory address on the target side where the transmission descriptor and transmission data are stored is set. Next, CBA Task sets run Bit for OHCI Unit.
The structure of ORB_page_table is as shown in FIG.

The sequence seq3 (FIGS. 9 to 10) is a process for transferring file data (Read data).
Read data is written to the buffer memory 15 with the header and footer of the IEEE 1394 packet added by the processing of the OHCI software in the sequence seq2.
The OHCI unit reads the read data from the buffer memory 15 and transmits it to the PC Initiator as a data write request. When receiving the Data Write Request, the PC Initiator returns a Data Write Response (ACK: Acknowledge). The OHCI Unit transmits the next read data (Data Write Request) in response to receiving this Data Write Response. This is repeated according to the necessary read data transfer amount.

  When the OHCI unit completes the transmission of the last read data (Data Write Request) and the reception of the Data Write Response in response to this, the OHCI Unit sends an interrupt request by the Interrupt Handler to the data corresponding to the File Read Command. Notify the OHCI software of the successful completion of the transfer. In response to this, the OHCI software executes processing between tasks shown in the figure (delivery of RQPkt (DataQueue), Req Receive (Mailbox), TR_DATA.indicate (EventFlag)).

In the sequence seq4, first, in response to the CBA Task receiving TR_DATA.indicate (EventFlag), a Status Block Notice packet is generated and passed to the OHCI Unit. The OHCI Unit transmits this Status Block Notice packet to the PC Initiator.
When receiving the ACK in response to the status block notice from the PC Initiator, the OHCI Unit outputs an Interrupt as ReqTxComplete to the Interrupt Handler. In response to this, the predetermined task in the OHCI software executes the processing corresponding to ORB Complete as shown in the figure, and the Read Complete Notice is output from the CBA Task to the other Task. The corresponding transaction ends.

Here, the present embodiment corresponding to FIG. 7 and FIG. 8 will be compared with the general example corresponding to FIG. 9 and FIG.
First, in the general example, in the processing from the transmission of the response to the PC Initiator in response to the reception of DoorBell in the sequence seq1 of FIG. 9 to the subsequent transmission of the Page Table Read Request to the PC Initiator in the sequence seq2, the PC Initiator Every time a DoorBell, ORB Pointer Read Response, or ORB Read Response transmitted from is received, OHCI software processing is involved.
On the other hand, in FIG. 7 and FIG. 8, the process from the transmission of the response to the PC Initiator in response to the reception of DoorBell in the same sequence seq1 to the subsequent transmission of the Page Table Read Request to the PC Initiator in the sequence seq2 Are executed as hardware processing by the SBP2 unit 30 (CBA Unit) without intervening OHCI software processing (inter-hardware data transmission).

  Also, in sequence seq4, in FIG. 10, in response to receiving the last Data Write Response, the OHCI Unit outputs Interrupt, causes the OHCI software to execute the process, and generates and outputs the Status generated by the CBA Task. The status block notice can only be sent to the PC Initiator after receiving the block notice (packet). On the other hand, in this embodiment, as shown in FIG. 8, the CBA Unit outputs an Interrupt in response to the reception of the last Data Write Response, but the transmission of the Status Block Notice to the PC Initiator is It can execute itself at the timing after receiving Data Write Response without waiting for packet reception from OHCI software (data transmission between hardware).

In this way, in the present embodiment, the processing in the software layer is greatly reduced for the transaction according to the File Read Command, as compared with the past. As a result, in the present embodiment, the time required to transfer the Read data can be significantly reduced as compared with the conventional method, and as a result, the data transfer speed can be greatly increased.
As can be understood from the above description, this effect can be obtained by providing the OHCI unit 13 with the SBP2 unit 30 in addition to the OHCI unit 20. In other words, the specific sequence described above can be communicated with the initiator side only by the SBP2 unit 30 which is hardware.
For example, the procedure of the OHCI software corresponding to the sequence seq1 of FIGS. 7 and 8 is typical in SBP2 and is routine. For this reason, even if the processing of the software layer is omitted, there is no problem in subsequent Page Table List acquisition and Read data transfer as long as it is guaranteed that commands are exchanged normally with the initiator. . In the present embodiment, paying attention to this, the above-described specific procedure and the like are configured to be executed by the SBP2 unit 30 (CBA Unit).

  In the present embodiment, a configuration in which processing by software is replaced with hardware processing by the SBP2 unit 30 (CBA Unit) during communication by SBP2 is not limited to a transaction corresponding to the above File Read Command, but also by File Write Command (file writing). The transaction corresponding to the command) is also given. Then, subsequently, with reference to FIG. 11, FIG. 12, FIG. 13, and FIG. 14, each transaction of embodiment corresponding to File Write Command and a general example is demonstrated.

First, FIG. 11 and FIG. 12 corresponding to the embodiment will be described.
Also in this figure, the transactions corresponding to the File Write Command are shown divided by sequences seq1 to seq4.

First, for the sequence seq1, the sequence flow is the same as in FIG. 7 ([Embodiment: Transaction corresponding to File Read Command]).
However, the Command Block ORB as a response (ORB Read Response) to the ORB Read Request from the PC Initiator is a File Write Command in this case.
The structure of the Command Block ORB as this File Write Command is as shown in FIG. The structure itself is the same as the Command Block ORB as the File Read Command shown in FIG. 25, but 4'hC4 is stored as shown in cdb [0], so that the current Command Block ORB is stored. Indicates File Write Command.
Also in this case, it is assumed that 1 is stored in the area of p (page_table_present_bit: 1 bit) in the Command Block ORB.

Further, the sequence seq2 that follows is the same as the flow of the sequence in FIG. 7, and the target is processing for acquiring the page table from the PC Initiator side.
Also in this case, the CBA Unit holds the received Page Table List (FIG. 26) in the buffer memory 15, for example, and writes and holds it in the memory 12 by DMA transfer. Accordingly, as in the case shown in FIGS. 7 and 8, the OHCI software only needs to access the memory area for the Command ORB and Page Table List specified in the memory 12, so that these Command ORB, Page The contents of Table List can be recognized.
Further, as processing of the OHCI software in the sequence seq2, the Command ORB and the Page Table List are read and an error check is executed. Also, using the Input More descriptor, set the memory address (transfer destination buffer address) and transfer data size (receive data size). And set run bit. The Context used at this time is SBP2 receive Context.

  Even with the above File Write Command sequences seq1 and seq2, the processing from when the CBA Unit receives DoorBell until it issues a page table request to the PC Initiator does not involve OHCI software processing. It can be seen that it is only executed by.

Sequence seq3 (FIGS. 11 and 12) is processing for receiving data (Write data: write data) of a file transferred from the PC Initiator on the Target side.
In the sequence seq3, first, the CBA Unit outputs a Data Read Request to the PC Initiator. In response to this, Write data having a size corresponding to the previously specified received data size is transmitted from the PC Initiator to the CBA Unit as a Data Read Response in the IEEE 1394 packet format.
In the SBP2 unit 30 of FIG. 4, when the CBA unit receives the write data in the IEEE 1394 packet format transmitted as described above from the IEEE 1394 link layer / physical layer block 23, the AR_FAM FIFO block 37, Header / Footer Remove Block 36 and AR_FAM DMA block 35 are passed in this order. As a result, the header and footer of the IEEE 1394 packet are removed from the write data by hardware processing by the header / footer remove block 36. Then, the data from which the header and footer are removed in this way is transferred to, for example, the buffer memory 15. This sequence is repeated according to the required write data transfer amount.
When it is assumed that the reception of the write data corresponding to the last data read request has been normally completed, the CBA Unit notifies the OHCI software of this by making an interrupt request by DescComplete to the Interrupt Handler. In response to this, the OHCI software executes processing between tasks and copies data in the same manner as in the case of the transactions in FIGS.
Note that in the sequence seq3 of FIGS. 11 and 12, the OHCI software process is not executed every time Write data is received as Data Read Response, and data transmission between hardware is performed. I want.

The sequence procedure in the sequence seq4 is the same as that of the transaction shown in FIGS.
That is, after making an interrupt request by DescComplete, the CBA Unit generates a status (status block notice) by itself and transmits it to the PC Initiator without waiting for a response from the OHCI software. Next, when an ACK transmitted from the PC Initiator is received, an interrupt request as ORB Complete is output to the Interrupt Handler, and a process corresponding to ORB Complete is executed by a predetermined task in the OHCI software.
Thus far, the transaction corresponding to the File Write Command as the embodiment is completed.

  Next, a general example transaction corresponding to File Write Command will be described with reference to FIGS. Also in this figure, the transactions corresponding to the File Read Command are shown sequentially divided by sequences seq1 to seq4.

Also in the sequence seq1 of FIG. 13, first, the PC Initiator transmits DoorBell. In response to this, the OHCI Unit and the OHCI task as the Target perform the same sequence as in FIG. 9 and finally execute the processing from the CBA Task to the Page Table Read Request transmission to the OHCI Unit. . However, the Command Block ORB as a response (ORB Read Response) to the ORB Read Request from the PC Initiator is the same as the File Write Command (FIG. 27) as in FIG.
Also in this case, it is assumed that 1 is stored in the area of p (page_table_present_bit: 1 bit) in the Command Block ORB.

  For the subsequent sequence seq2, the same procedure as in FIG. 9 is executed, and Target acquires the Page Table from the PC Initiator side. Also, CBA Task sets run Bit for OHCI Unit.

The sequence seq3 (FIGS. 13 and 14) is a process for receiving data (Write data) of a file transferred from the PC Initiator on the Target side.
Also in this case, in the sequence seq3, first, the OHCI Unit outputs a Data Read Request to the PC Initiator. In response to this, Write data having a size corresponding to the previously specified received data size is transmitted from the PC Initiator to the OHCI Unit as a Data Read Response in the IEEE 1394 packet format.
In response to receiving Data Read Response which is Write data, the OHCI Unit outputs an Interrupt to the Interrupt Handler, and passes the Write data packet to the OHCI software. At this time, the write data packet has a structure including a header and a footer.
Each task of OHCI software executes RSPkt (DataQueue), Resp Receive (Mailbox), TR_DATA.confirmation (EventFlag), and Notify (Mailbox) as shown in the figure, so that the header and footer are removed from the packet. Thus, the entity of the write data is taken out and copied to the memory. Then, CBA Task receives Callback (EventFlag) and outputs Status Bock Notice to OHCI Unit to set the run bit (set AT Request Data Transmit ContextControl.run)
The OHCI Unit transmits a Data Read Request to the PC Initiator and receives a Data Read Response (Write data) from the PC Initiator in response to the run bit being set (Receiving Status Bock Notice). In this manner, the Target repeats a transaction including transmission of Data Read Request and packet processing by the OHCI software in response to reception of Data Read Response as a sequence seq3 according to the write data transfer amount.

Then, when the above transaction by the OHCI software in response to the transmission of the last Data Read Request and the reception of the Data Read Response in response thereto is completed, the processing proceeds to the sequence seq4.
In the sequence seq4, first, the CBA Task that has received Callback (EventFlag) generates a Status Block Notice packet and passes it to the OHCI Unit. The OHCI Unit transmits this Status Block Notice packet to the PC Initiator. Next, when ACK is received in response to Status Block Notice, a process corresponding to ORB Complete is executed as shown in the figure by a predetermined task in the OHCI software. This ends the transaction corresponding to the File Write Command in the general example.

As can be seen by comparing FIGS. 11 and 12 with FIGS. 13 and 14, in the transaction corresponding to the File Write Command, in the embodiment, the DoorBell in the sequence seq1 is the same as in the case of the File Read Command. In the processing from the transmission of the response to the PC Initiator in response to the reception of the data to the transmission of the Page Table Read Request to the PC Initiator in the subsequent sequence seq2, the processing of the OHCI software is not interposed.
Also in the sequence seq4, in the embodiment, the status block notice can be transmitted to the PC Initiator at the timing after receiving the Data Write Response without waiting for the CBA Unit to receive the packet from the OHCI software. It is like that.

Further, in the transaction corresponding to the File Write Command, in the general example, as shown in FIGS. 13 and 14, the OHCI software is returned every time the data read response of the write data is returned when the write data is transferred in the sequence seq3. It is necessary to execute interrupt processing to perform packet processing such as header / footer removal and data copy, and transmission of Data Read Request to the PC Initiator must wait for a response from the CBA Task.
On the other hand, in the present embodiment, as shown as the sequence seq3 in FIGS. 11 and 12, the transaction consisting of the transmission of the Data Read Request to the PC Initiator and the reception of the Data Read Response does not involve the OHCI software. This is done in hardware (data transmission between hardware).

  As described above, according to the present embodiment, even in a transaction corresponding to File Write Command, a specific sequence can be independently executed by a CBA unit, that is, hardware without intervention of software. As a result, the data transfer speed can be increased.

By the way, as understood from the above description, in this embodiment, it is possible to receive Command Block ORB and Page Table (Page Table List) transmitted from the initiator by the SBP2 unit 30 (CBA Unit). Has been.
Here, the total data size of the Page Table varies depending on the state (discrete number) of the data buffer of the data on the initiator side. Therefore, it is necessary to assume that the total data size of the Page Table may exceed the buffer size for the SBP2 ORB_Page Table receive DMA and the size of the Page Table FIFO that the Command Block Agent Unit 31 is supposed to have. .

Therefore, the present embodiment corresponds to the above case as described below.
FIG. 28A shows a Command Block (CB) ORB corresponding to a File Read Command or File Write Command, and the entire Page Table to be transferred together with the Command Block ORB (Page Table elements). For example, on the Target side, the Command Block ORB and Page Table shown here need to be fetched.
This Page Table can be divided into N groups (division units) as shown in FIG. Here, IDs (PgTbID [1] to PgTbID [N] are given to the division units obtained in this way to distinguish them.
Here, how many groups the Page Table is divided into, that is, how many divisions N, is based on the total data size of the Page Table set on the Initiator side and the SBP2 ORB_Page Table Receive DMA controller. For example, it can be obtained on the Target side according to the total buffer size.
In the present embodiment, the division number N is configured to be obtained by a CBA Unit (Command Block Agent Unit 31), that is, by hardware.

When transferring N division units of the Page Table divided as shown in FIG. 28B to the buffer of the SBP2 ORB_Page Table Receive DMA controller, the component shown in FIG. Form. As shown in the figure, this component is formed by connecting one division unit to the Command Block ORB.
As shown in FIG. 26, this component has a structure of ORB_page_table. The Command Block ORB in the component corresponds to the area from the top this_ORB to Cdb [11], and the page table division unit (group) corresponds to the area from data_length (page table length, data length) to the end. One division unit includes page_table_length and data_length following the Command Block ORB, and a Page Table List following this. Note that the Page Table List has a structure in which one or more 8-byte page_elements composed of segment_length, segment_bass_hi, and segment_bass_lo are continuously arranged according to the format of the ORB_page_table as shown in the figure. .

  Then, the component formed in this way is transferred from the initiator to the buffer of the SBP2 ORB_Page Table Receive DMA controller. Therefore, in order to transfer the entire page table, the component transfer is repeated N times.

  Further, when all the page table division units of a certain component cannot be transferred and written to the buffer at one time, as shown in the example of the group having PgTbID [j] in FIG. Then, the remaining group portion (PgTbID [j ′]) that cannot be written is further componentized and transferred to the buffer again.

Then, as described with reference to FIG. 28, when the Page Table is divided into N pieces, the transfer of the Page Table List from the Initiator to the Target is also executed N times according to the division unit. Examples of transactions according to the File Read Command in the embodiment in this case are shown in FIGS.
15 and 16 exemplify a case where the Page Table is divided into 2 (N = 2).

The sequence seq1 in FIG. 15 is the same as that in FIG.
The processing for acquiring the Page Table by the subsequent sequence seq2 is the same as in FIG. 7 and FIG. 8, but here, the CBA Unit is the division unit of the first half of the Page Table divided into two. A Page Table Request for requesting a Command Block ORB (ORB_page_table) that stores a Page Table List consisting of is sent to the Initiator. In response to this, the Initiator returns a Command Block ORB (ORB_page_table) that stores a Page Table List consisting of the division units of the first half of the Page Table.

  The sequence seq3 (FIGS. 15 to 16) is a sequence for transferring file data (Read data), and the sequence procedure itself is the same as that in FIGS. However, the sequence seq3 in this case transfers data only to the data buffer indicated by the Page Table List (Page Table element) acquired by the sequence seq2 among the read data. When this data transfer is completed, as shown in the figure, the CBA Unit releases the memory data by making an interrupt request by DescComplete to the Interrupt Handler and causing the OHCI software to execute the necessary processing. To do.

  Then, if the CBA Unit in this case outputs DescComplete to the Interrupt Handler in the sequence seq3, it transmits a Page Table Request to the Initiator again as a sequence seq4. The Page Table Request at this time is a request for a Command Block ORB (ORB_page_table) of the Page Table List that is composed of the remaining second half of the Page Table. In response to this, the Initiator returns a Command Block ORB (ORB_page_table) that stores a Page Table List composed of division units of the latter half of the Page Table.

  The sequence seq5 transfers data to a Data buffer indicated by the Page Table List (Page Table element) acquired by the sequence seq4 as a sequence for transferring Read data. As a result, all the read data is written in the data buffer on the initiator side.

  The subsequent sequence seq6 executes the same end processing procedure as the sequence seq4 of FIGS. Upon completion of this sequence seq6, the transaction corresponding to the File Read Command is completed.

As a comparison with FIGS. 15 and 16, FIGS. 17 and 18 show an example in which the Page table is divided into 2 (N = 2) pieces in the transaction according to the File Read Command in the general example. .
First, the sequences seq1 and seq2 in FIGS. 17 and 18 are the same as those in the case of the transaction corresponding to the File Read Command in the general example shown in FIGS. However, in the sequence seq2, as in FIG. 15 and FIG. 16, the Target side sets the Command Block ORB of the Page Table List corresponding to the division unit of the first Page Table among the Page Tables divided into two. (ORB_page_table) is received from the initiator.
In sequence seq3 (FIGS. 17 to 18), Read data is transferred in the same sequence as in FIGS. 9 and 10. Here, as in FIGS. 15 and 16, the read data is also acquired by the sequence seq2. Data is transferred only to the data buffer indicated by the Page Table List (Page Table element).
In the sequence seq4, a process for receiving a Command Block ORB (ORB_page_table) that stores a Page Table List composed of the remaining Page Table division units in the latter half from the initiator is executed.
In sequence seq5, data is transferred to the data buffer indicated by the page table list (page table element) acquired in sequence seq4 in the same procedure as sequence seq2.
Subsequent sequence seq6 executes the same end processing as sequence seq4 in FIGS. The transaction corresponding to the File Read Command is completed with the end of the sequence seq6.

  Further, as an example in which the page table is divided into 2 (N = 2), an example of a transaction according to the File Write Command in this embodiment is also shown in FIGS.

  First, the sequence seq1 and the sequence seq2 in FIG. 19 are the same as those in FIG. However, in the sequence seq2 here, the CBA Unit requests the Command Block ORB (ORB_page_table) that stores the Page Table List consisting of the division units of the first half of the Page Table divided into two. Send Request to Initiator. In response to this, the Initiator returns a Command Block ORB (ORB_page_table) that stores a Page Table List consisting of the division units of the first half of the Page Table.

  The sequence seq3 (FIGS. 19 to 20) is a sequence for receiving write data from the initiator, and the sequence procedure itself is the same as that in FIGS. However, the sequence seq3 in this case is a process for receiving data only from the data buffer indicated by the Page Table List (Page Table element) acquired by the sequence seq2 among the write data. When the reception of this data is completed, as shown in the figure, the CBA Unit makes an interrupt request by DescComplete to the Interrupt Handler, and copies the data to the memory by causing the OHCI software to execute the necessary processing.

  Then, if the CBA Unit in this case outputs DescComplete to the Interrupt Handler in the sequence seq3, it transmits a Page Table Request to the Initiator again as a sequence seq4. As a result, a sequence for receiving the Command Block ORB (ORB_page_table) storing the Page Table List including the remaining page table division units from the initiator is executed.

  The sequence seq5 receives data from the data buffer indicated by the Page Table List (Page Table element) corresponding to the division unit of the latter half of the Page Table obtained by the sequence seq4 as a sequence for receiving Write data on the Target side. Execute the process for

  The subsequent sequence seq6 executes the same end processing procedure as the sequence seq4 of FIGS. Upon completion of this sequence seq6, the transaction corresponding to the File Write Command is completed.

Further, as a comparison with FIG. 19 and FIG. 20, for the transaction according to the File Write Command in the general example, an example in which the Page Table is similarly divided into 2 (N = 2) is shown in FIG. It shows in FIG.
In FIG. 21, the first sequences seq1 and seq2 are the same as those in the case of the transaction according to the File Write Command in the general example shown in FIG. However, in the sequence seq2, as in the case of FIG. 19 and FIG. 20, the Target side stores a Page Table List corresponding to the division unit of the first half of the Page Tables divided into two. Receive Command Block ORB (ORB_page_table) from Initiator.
In the sequence seq3 (FIGS. 21 to 22), Write data is received on the Target side in the same sequence as in FIGS. 13 and 14. Here, as in the sequence seq3 in FIGS. The data is received only from the data buffer indicated by the Page element of the Page Table List acquired by the sequence seq2.
In the sequence seq4 (FIG. 22), the process for receiving the Command Block ORB (ORB_page_table) of the Page Table List composed of the remaining division units of the Page Table from the Initiator is executed by the same procedure as the previous sequence seq2. In the sequence seq5 (FIGS. 22 to 23), the Target receives data from the Data buffer indicated by the Page element of the Page Table List acquired by the sequence seq4 in the same procedure as the sequence seq2.
The subsequent sequence seq6 performs the same end processing as the sequence seq4 in FIGS. With the end of this sequence seq6, the transaction corresponding to the File Write Command is completed.

  In the transaction according to the present embodiment, the page table is divided into N pieces as described with reference to FIG. 28, although it is not reflected in FIGS. 15, 16, 19, and 20. Is configured to be executed by the SBP2 unit 30 (Command Block Agent Unit 31) which is hardware, not software. Similarly, the Command Block Agent Unit 31 generates and transmits a Page Table Request to be transmitted in the sequences seq2 and seq4 in FIG. 15, FIG. 16, FIG. 19, and FIG. is there.

  15 and 16 corresponding to the above File Read Command, and FIGS. 17 and 18, the same as FIGS. 7, 8, 9, and 10, In the present embodiment, the CBA Unit, which is hardware, executes the process for a specific sequence without interposing the process of the OHCI software. The same can be said from a comparison between FIG. 19 and FIG. 20 corresponding to the File Write Command and FIG. 21, FIG. 22, and FIG.

  By the way, up to now, transactions that do not intervene OHCI software processing for a specific sequence using the SBP2 unit 30 (SBP2 unit compatible transactions) may correspond to File Read Command and File Write Command. I have explained it with an example.

Under the present embodiment, the SBP2 unit compatible transaction can be applied to all commands other than the File Read Command and File Write Command defined by SBP2.
However, in actuality, the SBP2 unit compatible transaction is applied only to the File Read Command and the File Write Command. This is due to the following reason.
For example, as described above, it is possible to apply the SBP2 unit compatible transaction to all commands, but in this case, it is necessary to configure the SBP2 unit 30 to be compatible with all these commands. However, as the number of commands to be associated with the SBP2 unit compatible transaction increases, the hardware configuration of the SBP2 unit 30 becomes more complex and the design of circuits and processes becomes more difficult.

  So, for example, if you consider what is the priority for high-speed processing among transactions according to various commands specified in SBP2, first, the above File Read Command and File Write Command are Raise. The Read data or Write data exchanged under File Read Command and File Write Command is file data, so the size is large. Especially, in the system having the configuration shown in FIG. This is because it becomes a very large size. In fact, it has been confirmed through experiments that, for example, when the transaction corresponding to the File Read Command and the File Write Command is the SBP2 unit compatible transaction of the present embodiment, the speed is increased by a factor of three or more. On the other hand, even if the SBP2 unit compatible transaction is applied to other commands, it is unlikely that the speedup will be noticeable.

  In addition, the general OHCI unit 13 which is not provided with the SBP2 unit 30 and is composed only of the OHCI unit 21 is actually widely used as a general-purpose chip for IEEE1394 communication conforming to OHCI. There is a situation in which a technique for executing communication and transactions (transactions corresponding to OHCI units) in accordance with SBP2 under the control of SBP2 has been established. In consideration of this, it is preferable to apply the SBP2 unit 30 to a command that does not show a noticeable speedup and to eliminate the need for the OHCI unit 21 from the viewpoint of making it impossible to utilize the existing software assets. I can't say that. In other words, it can be said that it is more efficient to properly use the SBP2 unit compatible transaction and the OHCI unit compatible transaction depending on the command.

As a result of considering this, in the present embodiment, the SBP2 unit compatible transaction is applied only to the transaction corresponding to the File Read Command and the File Write Command, and the remaining command is, for example, at least regarding the exchange of data. The same transaction for OHCI units as before will be applied at least in part.
However, if necessary, some considerations other than File Read Command and File Write Command will be taken into consideration, such as the above-mentioned saliency of speedup, utilization of software assets, and complicated hardware configuration as SBP2 unit 30. The transaction corresponding to the command should not be particularly hindered from applying the SBP2 unit compatible transaction.

Here, as an example of a command to which an OHCI unit compatible transaction is applied, File Open Command is given as an example, and FIG. 24 shows an example of the transaction.
In this figure, the entire transaction is shown in the order of sequences seq1, seq2, and seq3.

First, in sequence seq1, PC Initiator transmits DoorBell to Target. In response to this, when the OHCI unit 13 includes the SBP2 unit 30 as in the present embodiment, DoorBell is accepted by the CBA Unit on the SBP2 unit 30 side as described above. In response to the reception of DoorBell, the CBA Unit immediately returns Response to the Target without intervening OHCI software processing. Further, an ORB Pointer Read Request is subsequently transmitted to the PC Initiator. In response to receiving the ORB Pointer Read Request, the PC Initiator returns an ORB Pointer Read Response to the CBA Unit. In this ORB Pointer Read Response, a Memory Address on the PC Initiator side that fetches (or fetches) the ORB is shown.
Therefore, the CBA Unit transmits an ORB Read Request to the PC Initiator in response to receiving the ORB Read Request. The PC Initiator returns a Command Block ORB as a File Open Command as an ORB Read Response in response to the ORB Read Request. The Command Block ORB as the File Open Command stores C0h for cdb [0] in the structure shown in FIG. 25, for example.

In this case, the CBA Unit issues an interrupt request by outputting ORBfetch to the Interrupt Handler in response to receiving the Command Block ORB. In response to this, the OHCI software executes the illustrated process.
As you can see from the processing so far, the processing from the reception of DoorBell (access to the Command Block Agent Register) to the reception of the Command Block ORB corresponds to the previous File Read Command and File Write Command. Similar to transactions, the processing is performed by hardware between the CBA Unit and the PC Initiator without software intervention.

In the subsequent sequence seq2, in response to the execution of ORB: OPEN: EV_ORBFCH (EventFlag) from the OHCI Task to the CBA Task by the sequence seq1, the File Name Read from the CBA Task to the OHCI Unit (OHCI unit 21). Outputs Request.
In response to accepting the File Name Read Request, the OHCI Task transmits a Read Request Block to the PC Initiator.
The PC Initiator first returns an Acknowledge (ACK) in response to receiving the Read Request Block. In response to the reception of the ACK, the OHCI Unit interrupts the Interrupt Handler using ReqTxComplete. As a result, as shown in the figure, by executing software processing between the Interrupt Handler and the OHCI Task and Transaction Task, the OHCI software recognizes that the Read Request Block has been successfully transmitted.
Next, the PC Initiator returns a Read Response Block following the output of ACK. The OHCI unit that has received this interrupts the interrupt handler by passing the read response block packet to the interrupt handler. In response to this, required processing (INT_RSPKT (DataQueue), RX: READ_B_RES, File Name Read Resp: EV_DONE (EventFlag), psmChkFileType, psmOpenFile) by the OHCI software is executed. By this OHCI software processing, for example, the file name can be acquired on the Target side.
The process as the sequence seq2 is a process in which software is interposed in the same manner as before. For this reason, in the sequence seq2, in place of the CBA Unit (SBP2 unit 30), an OHCI Unit (OHCI) Unit 21) is executing the process.

  When the OHCI software process in the sequence seq2 is completed, the CBA Task returns a status block notice to the OHCI Unit as the sequence seq3. In response, the OHCI Unit sends a status block notice to the PC Initiator. The PC Initiator returns an ACK in response to receiving the status block notice. The OHCI Unit interrupts in response to the reception of this ACK, causes the OHCI software to execute the processing shown in the figure, and finally the sequence end notification is sent from the CBA Task to the CBA Unit. The transaction corresponding to is terminated.

In the embodiment described so far, the node corresponding to the target is the video camera device 1, but is not limited to this. As a matter of course, the present invention can be applied to an IEEE 1394 data interface function implemented other than other video camera apparatuses.
In the above-described embodiment, IEEE 1394 is taken as an example of the data interface standard, OHCI is taken as a common standard in IEEE 1394, and SBP2 is taken as an upper-layer communication protocol of IEEE 1394. However, under the present invention, these data interface standards, common standards, and higher-level communication protocols are not particularly limited.

It is a figure which shows the system configuration example corresponding to embodiment of this invention. It is a block diagram which shows the site | part relevant to the IEEE1394 data interface in the video camera apparatus of embodiment. It is a block diagram which shows the structural example of the OHCI part corresponding to a general example. It is a block diagram which shows the structural example of the OHCI part corresponding to embodiment. It is a figure which shows Command Block Agent Register. It is a figure which shows Fetch Agent CSR base address register. It is a sequence diagram which shows the transaction according to the Read command (File read Command) corresponding to embodiment. FIG. 8 is a sequence diagram illustrating a transaction following FIG. 7. It is a sequence diagram which shows the transaction according to the Read command (File read Command) corresponding to a general example. FIG. 10 is a sequence diagram illustrating a transaction following FIG. 9. It is a sequence diagram which shows the transaction according to Write command (File Write Command) corresponding to embodiment. FIG. 12 is a sequence diagram illustrating a transaction following FIG. 11. It is a sequence diagram which shows the transaction according to the Write command (File Write Command) corresponding to a general example. It is a sequence diagram which shows the transaction following FIG. It is a sequence diagram which shows the transaction at the time of dividing | segmenting Page Table List as a transaction according to the Read command (File read Command) corresponding to embodiment. FIG. 16 is a sequence diagram illustrating a transaction following FIG. 15. It is a sequence diagram which shows the transaction at the time of dividing | segmenting Page Table List as a transaction according to the Read command (File read Command) corresponding to a general example. FIG. 18 is a sequence diagram illustrating a transaction following FIG. 17. It is a sequence diagram which shows the transaction at the time of dividing | segmenting Page Table List as a transaction according to Write command (File Write Command) corresponding to embodiment. FIG. 20 is a sequence diagram illustrating a transaction following FIG. 19. It is a sequence diagram which shows the transaction at the time of dividing | segmenting Page Table List as a transaction according to the Write command (File Write Command) corresponding to a general example. It is a sequence diagram which shows the transaction following FIG. It is a sequence diagram which shows the transaction following FIG. It is a sequence diagram which shows the transaction according to File Open Command corresponding to embodiment. It is a figure which shows the structure of Command Block ORB as File Read Command. It is a figure which shows ORB_page_table. It is a figure which shows the structure of Command Block ORB as File Write Command. It is a figure which shows the concept of Page Table division | segmentation.

Explanation of symbols

  1 video camera device, 2 editing device (PC), 3 IEEE 1394 bus, 11 CPU, 12 memory, 13 OHCI section, 15 buffer memory, 21 OHCI unit, 22 PCI bus interface block, 23 IEEE 1394 link layer / physical layer block, 30SBP2 Unit, 31 Command Block Agent Unit, 32 AT FAM DMA block, 33 Header / Footer Add Block, 34 AT FAM FIFO block, 35 AR_FAM DMA block, 36 Header / Footer Remove Block, 37 AR_FAM FIFO block

Claims (11)

It is formed in accordance with a predetermined common standard defined under a predetermined data interface standard, and data transmission is performed between an external bus corresponding to the data interface standard and an internal bus according to the predetermined standard. A first transmission unit provided;
Provided between the external bus and the internal bus, and performs data transmission corresponding to a predetermined communication protocol defined at a higher level of the data interface standard, formed by hardware, and the first transmission Second transmission configured to perform hardware-to-hardware data transmission between itself and an external bus without intervention of software for a predetermined sequence in which processing by software is involved And
An information processing apparatus comprising: The second transmission unit is
The hardware-to-hardware data transmission is executed for a predetermined sequence in a transaction corresponding to a predetermined command defined by the communication protocol.
The information processing apparatus according to claim 1. The second transmission unit is
At least hardware-to-hardware data transmission is performed for a sequence for transferring read data in a transaction corresponding to a file read command defined by the communication protocol.
The information processing apparatus according to claim 2. The second transmission unit is
At least hardware-to-hardware data transmission is performed for a sequence for transferring write data in a transaction corresponding to a file write command defined in the communication protocol.
The information processing apparatus according to claim 2. The second transmission unit is
At least hardware-to-hardware data transmission is executed with respect to a response to access to a register corresponding to a predetermined agent function in the communication protocol to be supported by itself and processing subsequent to reception of data indicating command contents. ,
The information processing apparatus according to claim 1. The second transmission unit is
Header / footer adding means for adding a header and footer of a packet defined by the data interface standard to data to be transmitted to the external bus;
The information processing apparatus according to claim 1. The second transmission unit is
Header / footer removing means for removing the header and footer from the packet format data defined by the data interface standard transmitted from the external bus;
The information processing apparatus according to claim 1. The second transmission unit is
Data transmission between hardware corresponding to only a predetermined agent function defined in the communication protocol is performed.
The information processing apparatus according to claim 1. The second transmission unit is
At least when the address indicated by the access to the register corresponding to the agent function received by the information processing apparatus via the external bus is the same as the address of the target agent function corresponding register corresponding to the predetermined agent function, To perform hardware-to-hardware data transmission,
The information processing apparatus according to claim 8. The second transmission unit is
When the total size of the page table indicating the discrete buffer area for data transmitted by the inter-hardware data transmission of the counterpart information processing apparatus connected to the external bus is greater than or equal to a predetermined value, the page table Is divided into multiple page table parts,
When making a page table request to the counterpart information processing apparatus, it is configured to make a request separately for each page table part,
The information processing apparatus according to claim 1. Data is transmitted between an external bus corresponding to the data interface standard and an internal bus according to the predetermined standard, which is formed in accordance with a predetermined common standard defined under a predetermined data interface standard. A first transmission unit provided by
A second transmission formed by hardware, which is provided between the external bus and the internal bus and transmits data corresponding to a predetermined communication protocol defined by the upper level of the data interface standard. An information processing method in an information processing apparatus comprising a unit,
When the first transmission unit is used, when a predetermined sequence involving software processing is to be executed, hardware between the second transmission unit and the external bus without software intervention is used. Information processing method for performing inter-data transmission.

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