JP2009288731A - Image display device and signal processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device and a signal processing device which can efficiently detect whether an operation state of an image output part operated synchronizing with a clock signal input from the outside is normal or not. <P>SOLUTION: When an image display device 20 is started, a display control part 28 reads out a register value of a data register 45 being a register for check of an image output part 24, and discriminates whether read out data is normal or not. When the read out register value is normal, a control command for the image output part 24 is output, image display conditions including the read out data are set, then discrimination operation of the display control part 28 is finished. When the register value is determined as being not normal, it is discriminated whether the number of times (n) in which the register value is not normal reaches a previously decided value stored in the display control part 28 or not, when it is the value previously decided, a reset signal is output to the image output part 24 and it is reset. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image display device and a signal processing device capable of detecting whether or not an operation state of a drive unit that outputs information to an output unit such as a liquid crystal display panel is normal in synchronization with a clock signal input from the outside. About.

  FIG. 1 is a block diagram showing a schematic configuration of a conventional image display device 1. For example, an image display device 1 also called a multi-view display device mounted on a vehicle includes a navigation unit 2 that outputs road information and GPS reception information together with map information and a route guidance image, and a camera that images the front and rear of the vehicle. Main control for overall control of image signal, radio receiver for receiving radio broadcast waves, TV receiver for receiving TV broadcast waves, CD / DVD playback section for playing music and images recorded on CD or DVD Unit 3 and a display unit 4 for displaying an image signal from the main control unit 3.

  The navigation unit 2 operates in synchronization with the clock signal from the crystal oscillator, and outputs a synchronization signal, an image signal, and an image mute signal V-MUTE, and the synchronization signal and the image from the navigation control unit 10. There is provided a low voltage differential signaling (abbreviated as LVDS) transceiver 11 for inputting a signal and transmitting the signal to the display unit 4 through the main control unit 3. The LVDS transceiver 11 outputs a differential synchronization signal and a differential image signal obtained by combining the synchronization signal and the image signal.

  The display unit 4 inputs the differential output signal and the differential image signal from the image output unit 7, the liquid crystal display panel 8, and the LVDS transceiver 11, and outputs the clock signal and the image signal to the image output unit 7. And a display control unit 13 for outputting a control timing signal to the image output unit 7 and causing the image output unit 7 to output a black image signal by serial communication. The display control unit 13 is realized by a microcomputer.

  The display unit 4 performs saturation correction on the image signal input from the navigation unit 2 by an image output unit 7 that operates in synchronization with a clock signal CLK from a crystal oscillator provided outside the display unit 4. After performing hue correction, contrast correction, gamma correction, and the like, a drive signal and an image signal for the liquid crystal display panel 8 are generated, and an image is displayed on the liquid crystal display panel 8.

  The main control unit 3 is provided with an audio microcomputer 15, and in response to the TAB communication signal output from the navigation control unit 2, the audio microcomputer 15 causes the display control unit 13 to perform various operations such as image enlargement ratio. It is configured to set a set value and an operation mode.

  The image output unit 7 is realized by an application specific integration circuit (ASIC). The liquid crystal display panel 8 includes a liquid crystal display element and a backlight that irradiates the liquid crystal display element with light from behind. When the display control unit 13 inputs the image mute signal V-MUTE from the navigation unit 2, the backlight outputs a backlight control signal for reducing the luminance to the backlight control unit 16, and the luminance of the backlight is increased. Decrease to display black.

  The image output unit 7 operates by inputting a clock signal from a crystal oscillator provided outside the display unit 4. In this case, when the power is turned on, the image output unit 7 performs a normal operation and transmits the horizontal synchronization signal HSY and the vertical synchronization signal VSY generated by the clock signal CLK to the navigation unit 2, thereby causing the liquid crystal display element to The timing of the on / off operation of the switching elements provided in a matrix and the image display operation are adjusted.

  In this prior art, the image output unit 7 operates in synchronization with the clock signal input from the navigation unit 2 via the main control unit 3, so that when the clock signal is stopped, the image output unit 7 does not operate, It cannot be output. Such a stop of the clock signal is caused by the supply of the clock signal being stopped during the reset period because the navigation control unit 10 always resets at the transition from the loading screen to the opening screen.

  As another conventional technique for monitoring such an operation state, for example, Patent Document 1 discloses an analog processor for converting an output from a CCD image sensor into a video signal in an image forming apparatus such as a copying machine and a facsimile, and a CCD image. A CCD analog processor having a CCD driver for driving the sensor is provided as an image output unit. In this CCD analog processor, since the pulse detection unit monitors a clock signal such as a reader synchronization signal output from the pulse generation unit, when the state of the clock signal does not return normally within a predetermined time, An error is displayed and the image forming process is stopped.

JP 2001-77955 A

  In the prior art disclosed in Patent Document 1, even if the clock signal is stopped during communication between the image output unit and the display control unit that controls the image output unit, the operation is performed using the clock signal acquired from the image output unit. There is a problem that it is difficult to determine whether or not the operation state of the image output unit is normal.

  An object of the present invention is to provide an image display device and a signal processing device capable of efficiently detecting whether or not the operation state of an image output unit that operates in synchronization with a clock signal input from the outside is normal. It is.

The present invention (1) includes an image signal source that outputs an image signal together with a clock signal;
An image output unit that outputs an image signal input from the image signal source together with a display control signal in synchronization with the clock signal;
In response to the display control signal, an image display unit that displays an image signal from the image output unit as an image;
The image signal input from the image signal source is displayed according to the transition of the display image displayed by the image display unit, and the operation state of the image output unit is determined from the information stored in the image output unit, and the image output And a display control unit that stops the operation of the image output unit when it is determined that the unit is not operating.

The present invention (4) includes a first processing unit that operates in synchronization with an externally input clock signal;
And a second processing unit that controls the operation of the first processing unit and detects the presence or absence of a clock signal input to the first processing unit.

  According to the present invention (1), the operation state of the image output unit is displayed by the display control unit that displays the image signal input from the image signal source according to the transition of the display image displayed by the image display unit. Therefore, even if the clock signal stops during communication between the image output unit and the display control unit, the stop of the clock signal is reliably detected and the image output unit operates normally. It can be determined whether or not. In addition, when the display control unit determines that the image output unit is not operating, the operation of the image output unit is stopped. Therefore, the display control is continued while the set value of the image output unit remains abnormal due to the stop of the clock. It is possible to prevent malfunctions such as the occurrence of an abnormal image.

  Further, since the display control unit directly monitors the image output unit, it is not necessary to provide a separate circuit for monitoring the operation state of the image output unit, and the substrate is compared with the case where the circuit for monitoring is provided. Therefore, the monitoring function of the image output unit can be realized with a simple configuration.

  According to the present invention (4), the second processing unit detects the presence or absence of the clock signal input to the first processing unit, so that the clock signal is stopped and input again to the first processing unit. Even if one processing unit operates, it is possible to easily determine whether or not the operation state is normal.

  FIG. 2 is a block diagram showing a schematic configuration of the image display apparatus 20 according to the embodiment of the present invention. The image display device 20 according to the present embodiment is a signal processing device called a multi-view display device mounted on a vehicle, for example, and is an image signal source that outputs road information and GPS reception information together with map information and route guidance images. As a navigation unit 21, an image signal from a camera that captures the front and rear of the vehicle, a radio reception unit that receives radio broadcast waves, a TV reception unit that receives television broadcast waves, and music and images recorded on a CD or DVD A main control unit 22 that comprehensively controls a CD / DVD reproduction unit to be reproduced and a display unit 23 that displays an image signal from the main control unit 22 are included.

  The navigation unit 21 outputs an image signal to the display unit 23 together with the clock signal CLK in synchronization with the clock signal CLK, outputs an image mute signal V-MUTE for changing the image to a black image, and further, a TAB communication signal. Is output to the audio microcomputer 35. The audio microcomputer 35 that receives the TAB communication signal from the navigation unit 21 outputs the TAB communication signal to the display control unit 28.

  The display unit 23 responds to the image output unit 24 that outputs the image signal input from the navigation unit 21 together with the display control signal in synchronization with the clock signal CLK, and the image signal and display control signal from the image output unit 24. Driven liquid crystal display element 25, a backlight 26 that irradiates the liquid crystal display element 25 from behind, a backlight control unit 27 that controls the luminance of the backlight 26, and an image mute signal V− from the navigation unit 21. And a display control unit 28 that outputs a backlight control signal for lowering the luminance to the backlight control unit 27 when MUTE is input.

  The navigation unit 21 operates in synchronization with a clock signal CLK from an external crystal oscillator, and outputs a synchronization signal, an image signal, and an image mute signal V-MUTE, and the navigation control unit 30 synchronizes with the navigation control unit 30. A low voltage differential signaling (abbreviated as LVDS) transceiver 31 that receives a signal and an image signal and transmits them to the display output unit 24 via the main control unit 22. The image output unit 24 receives a clock signal CLK from the outside of the image output unit 24, that is, from the outside of the display unit 23.

  The LVDS transceiver 31 outputs a differential synchronization signal and a differential image signal obtained by combining the synchronization signal and the image signal. Such a navigation unit 21 is configured to output a map and route guidance information based on road information received by the VICS information receiving unit and geographic information received by the GPS information receiving unit.

  The main control unit 22 is provided with an audio microcomputer 35, and in response to a TAB communication signal output from the navigation control unit 30, the display control unit 28 has various setting values such as an image enlargement ratio and an operation mode. Is configured to be set. The audio microcomputer 35 transmits a button operation signal of the user, for example, a signal for switching to DTV (Digital Television) to the display control unit 28, and transmits an initial setting command signal when setting the image quality. At this time, the navigation control unit 30 is reset after reading map data from an HDD (Hard Disk Drive), and the clock signal from the navigation control unit 30 may stop.

  The liquid crystal display element 25 and the backlight 26 constitute a liquid crystal display panel 33. The display unit 23 includes an image output unit 24 as a first processing unit that operates in synchronization with an externally input clock signal, a liquid crystal display panel 33, a differential synchronization signal and a differential image signal from the LVDS transceiver 31. , An LVDS receiver 34 that outputs a clock signal CLK and an image signal to the image output unit 24, a control timing signal to the image output unit 24, and a black image signal to the image output unit 24 by serial communication And the display control unit 28. The display control unit 28 constitutes a second processing unit that controls the operation of the first processing unit and detects a clock signal input to the first processing unit.

  The display control unit 28 displays the image signal input from the navigation unit 21 serving as the image signal source according to the transition of the display image displayed on the liquid crystal display panel 33, and determines the operation state of the image output unit 24. When it is determined that the image output unit 24 is not operating, a reset signal for resetting the image output unit 24 is output. Such a function of the display control unit 28 is realized by a program executable by a computer. The display control unit 28 is realized by a microcomputer as a hardware resource in which the program is stored in a storage area realized by, for example, a ROM (Read Only Memory).

  The navigation unit 21 includes a camera that captures the vehicle periphery such as the front and rear of the vehicle, a television receiver that receives television broadcast waves via an antenna, and CD / DVD reproduction that reproduces music information and images stored in CDs and DVDs. The apparatus may include a hard disk playback device that plays back image and music information recorded on the hard disk.

  The liquid crystal display element 25 has, in order from the backlight 26 side, a polarizing plate, an individual electrode side glass substrate on which TFTs (Thin Film Transistors) as switching elements are formed in a matrix, a liquid crystal layer, and pixels of three primary colors RGB A structure in which a color filter substrate, a parallax barrier layer, a common electrode side glass plate, a polarizing plate, and the like are laminated may be used. Such a liquid crystal display element constitutes, for example, a display screen in which 800 pixels are arranged in the horizontal direction and 480 pixels are arranged in the vertical direction.

  For example, the image output unit 24 includes a plurality of analog / digital converters, a luminance / color separation circuit, an RGB decoder, a switching circuit, a resolution conversion circuit, a writing circuit, a reading circuit, an output timing control circuit, a memory IF, and a VRAM. , C / B adjustment circuit, RGB rearrangement circuit, gamma table, gamma correction circuit, TFT timing control circuit, and the like. Such an image output unit 24 is realized by, for example, an ASIC (Application Specific Integrated Circuit).

  FIG. 3 is a block diagram illustrating a basic configuration of the arithmetic processing unit 40 provided in the image output unit 24. The image output unit 24 includes an arithmetic processing unit 40 that controls the display operation of the liquid crystal display panel 33 in response to a control signal from the display control unit 28. The arithmetic processing unit 40 is realized by a central processing unit (abbreviated as CPU), and executes arithmetic processing while sequentially reading a program stored in a memory. First, when an instruction read operation called fetch is executed, the contents of the program counter 41 are transferred to the address register 42 and an address signal is output to the address bus 43. Data input from the data bus 44 is sent to the instruction register 46 via the data register 45 and analyzed by the instruction decoder 47.

  The instruction is executed according to an instruction from the control circuit 48. The control circuit 48 executes data transfer, calculation, etc. between the registers 42, 45, 46, 47 and the logical operation unit (abbreviated as ALU) 49 according to the operation procedure assigned in advance to the analyzed instruction. In particular, the arithmetic processing is performed via the accumulator 50. The contents of the accumulator 50 and the contents of the other registers 42, 45, 46, 47 are input to the logical operation unit 49, and the operation results are stored in the accumulator 50 again.

  With respect to the arithmetic processing unit 40 configured in this way, the display control unit 28 outputs a determination readout signal to the control circuit 48 only when communication for setting is performed with respect to the image output unit 24. In response to this read signal, for example, the data register 45 is accessed, and data stored in the data register 45 (hereinafter sometimes referred to as a register value), for example, hexadecimal “3A” is read, and the control circuit The output is made from 48 to the display control unit 28. The data read in this way is determined by the display control unit 28, and if it is initial data, the image output unit 24 determines that it is normal, and if it is not predetermined data or data does not come, it is abnormal. And reset the image control unit 24 by outputting a reset signal.

  The determination to the image output unit 24 by the display control unit 28 may employ a checksum which is one of error detection methods when transmitting / receiving data. In this method, before transmitting data from the data register 45, the data to be transmitted is divided into a plurality of blocks, and a total value in which the data in each block is regarded as a numerical value, that is, a checksum is combined with the data. Send. The display control unit 28 on the receiving side similarly calculates a checksum from the transmitted data string, and checks whether or not it matches the checksum sent from the transmitting side. If the two are different, it can be determined that the image output unit 24 is abnormal.

  FIG. 4 is a flowchart for explaining the operation of the display control unit 28 provided in the display unit 23 of the image display device 20. For example, when the display control unit 28 performs communication for mode setting or initial value setting to the image output unit 24 (step s0), the display control unit 28 uses the check register of the image output unit 24, for example, the data register 45 described above. Reading (that is, reading) is performed (step s1), and it is determined whether or not the read data is normal (step s2). When the read register value is normal, a control command is output to the image output unit 24 to set image display conditions such as saturation correction, hue correction, contrast correction, and gamma correction including the read data. When the operation is started (step s3) and the setting operation is ended (step s4), the register value of the data register 45 is read again (step s5), and it is determined whether or not the register value is normal ( Step s6) If the read register value is normal, the determination operation of the display control unit 28 is terminated (Step s7).

  When it is determined that the register value is not normal before setting the image display condition on the image output unit 24 (step s2) and when the register value is not normal after setting (step s6), the register value is not normal. It is determined whether or not the number of occurrences, for example, the number n of mismatches, has reached a predetermined value stored in the display control unit 28 (step s8), and if it is a predetermined value, the image output unit 24 is reset. A signal is output and reset, the display on the liquid crystal display panel 33 is switched to a black screen, the display of a distorted image is avoided (step s9), and the determination operation is terminated (step s7). If the number n of register values is not normal is less than the predetermined number of times, the determination operation is stopped for a predetermined time W (step s10), and then the determination operation is started again (step s1). A similar routine is repeated n times, for example, every time interval W.

  The time interval W is selected to be 200 ms, for example, and the number of times n is selected to be 3 times. Such a time interval W is set so that the clock period is stopped.

  The operation state of the image output unit 24 is displayed by the display control unit 28 that displays the image signal input from the navigation unit 21 according to the transition of the display image displayed on the liquid crystal display panel 33 by the image display device 20 configured as described above. Is determined based on the information stored in the image output unit 24. Therefore, even if the clock signal is stopped during communication between the image output unit 24 and the display control unit 28, the stop of the clock signal is reliably detected. Thus, it can be determined whether or not the image output unit 24 is operating normally.

  Further, when the display control unit 28 determines that the image output unit 24 is not operating, the display control unit 28 stops the operation of the image output unit 24. Therefore, the display value is displayed while the set value of the image output unit 24 remains abnormal due to the stop of the clock. It is possible to prevent a malfunction that the control is continued, thereby preventing an abnormal image from being displayed.

  In addition, since the display control unit 28 directly monitors the image output unit 24, it is not necessary to provide a separate circuit for monitoring the operation state of the image output unit 24, and when the monitoring circuit is provided. In comparison with this, the mounting area of the board can be reduced, the manufacturing cost can be reduced, and the monitoring function of the image output unit 24 can be realized with a simple configuration.

  In addition, the display control unit 28 that is the second processing unit detects the presence or absence of the clock signal input to the image output unit 24 that is the first processing unit, so that the display control unit 28 stops the clock signal, Even if the image output unit 24 is input again and operates, it can be easily determined whether or not the operation state is normal.

It is a block diagram which shows schematic structure of the image display apparatus 1 of a prior art. It is a block diagram which shows schematic structure of the image display apparatus 20 of one Embodiment of this invention. 3 is a block diagram illustrating a basic configuration of an arithmetic processing unit 40 provided in the image output unit 24. FIG. 4 is a flowchart for explaining an operation of a display control unit 28 provided in the display unit 23 of the image display device 20.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 Image display apparatus 21 Navigation part 22 Main control part 23 Display part 24 Image output part 25 Liquid crystal display element 26 Backlight 27 Backlight control part 28 Display control part 30 Navigation control part 31 LVDS transceiver

Claims (4)

An image signal source for outputting an image signal together with a clock signal;
An image output unit that outputs an image signal input from the image signal source together with a display control signal in synchronization with the clock signal;
In response to the display control signal, an image display unit that displays an image signal from the image output unit as an image;
The image signal input from the image signal source is displayed according to the transition of the display image displayed by the image display unit, and the operation state of the image output unit is determined from the information stored in the image output unit, and the image output And a display control unit that stops the operation of the image output unit when it is determined that the unit is not operating.   The display control unit reads information stored in a register provided in the image output unit, and determines whether the image output unit is normal based on the read information. Item 4. The image display device according to Item 1.   The image display device according to claim 2, wherein the display control unit executes reading to the register of the image output unit a plurality of times at predetermined time intervals. A first processing unit that operates in synchronization with an externally input clock signal;
And a second processing unit that controls the operation of the first processing unit and detects the presence or absence of a clock signal input to the first processing unit.

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