JP2009284673A - Synchronous rectification bridge - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous rectification bridge which suppresses power loss. <P>SOLUTION: The synchronous rectification bridge 100 includes MOS transistors Q1, Q2 in which an AC voltage is input to the connection node N1; MOS transistors Q3, Q4 in which the AC voltage is input to the connection node N2; a first driving circuit 110 which outputs a gate signal to each gate of the MOS transistors Q1, Q2; and a second driving circuit 120 which outputs a gate signal to the gates of the MOS transistors Q3, Q4. Synchronizing with the input AC voltage, the bridge is driven so as to cause a current to flow in the MOS transistors Q1, Q4 when the AC voltage is in a first half-wave period and to flow in the MOS transistors Q2, Q3 when the voltage is in a second half-wave period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a synchronous rectification bridge that converts an AC power source into a DC power source.

  As an AC-DC converter for converting an AC power generated by a commercial AC power supply or a switching power supply into a DC power supply, a converter using a diode bridge is known. For example, Patent Document 1 discloses an AC-DC converter in which an inductor 6 and a capacitor 9 are connected in series between a rectifying diode bridge 2, 3, 4, 5 and an output capacitor 7 as shown in FIG. Yes. In this AC-DC converter, the first and second periods are set by the setting means 14 and 17, and the switching means 10, 11, 12, and 13 are connected to the capacitor 9, the inductor, Switching loss between the output capacitors is reduced by switching the connection between the output capacitors.

Japanese Patent Laid-Open No. 10-304670

  However, the converter using a diode bridge as shown in Patent Document 1 for the rectifier circuit has a problem that power loss due to the forward voltage of the diode is large. In particular, if the voltage or current of the input AC power supply increases, a large amount of power is lost accordingly, which cannot be ignored at all.

  The present invention solves such a conventional problem, and an object of the present invention is to provide a synchronous rectification bridge that suppresses power loss.

  The synchronous rectification bridge according to the present invention converts an input AC voltage into a DC voltage and outputs the DC voltage, and is connected in series between a DC output of a first potential and a DC output of a second potential. The third and fourth MOS transistors connected in series between the connected first and second MOS transistors and the first and second potential DC outputs, and the current flowing through the DC output. Driving means for outputting a gate signal to each gate of the first, second, third and fourth MOS transistors in response, and one input of the AC voltage is the first and second MOS transistors The other input of the AC voltage is connected to the second connection node that connects the third and fourth MOS transistors, and in response to the input AC voltage, In the first half-wave period, the first and fourth M A current flows through the OS transistor, and a current flows through the second and third MOS transistors during the second half-wave period.

  Preferably, the driving means includes a comparison circuit that detects a current flowing through the DC output, and controls each gate signal of the first, second, third, and fourth MOS transistors in response to a detection result of the comparison circuit. . The gate signals of the first, second, third, and fourth MOS transistors turn on the MOS transistors while the current is detected by the comparison circuit.

  Preferably, the driving means includes first and second comparison circuits, the first comparison circuit detects an operation state of the second MOS transistor, and the second comparison circuit is configured to detect the fourth MOS transistor. An operating state is detected, and the driving means controls the gate signals of the first, second, third, and fourth MOS transistors in response to detection results of the first and second comparison circuits.

  Preferably, one input of the first comparison circuit is connected to the source of the second MOS transistor, the other input is connected to the drain, and one input of the second comparison circuit is the fourth MOS transistor. The other input is connected to the drain, and the first and second comparison circuits detect the current flowing through the second and fourth MOS transistors.

  Preferably, the synchronous rectification bridge package according to the present invention includes a synchronous rectification bridge therein, and further includes two external terminals for inputting an AC voltage and two external terminals for outputting a DC output.

  According to the present invention, since the AC voltage is converted into the DC voltage using the first to fourth transistors (MOSFETs), the power loss is greatly reduced as compared with the rectification by the conventional diode bridge. be able to. In particular, when the load current increases, the effect of reducing power loss is great.

  The best mode for carrying out the present invention will be described in detail with reference to the drawings. In the following example, an AC-DC converter using a MOSFET (hereinafter abbreviated as FET) as a synchronous rectifier will be described as an example.

  FIG. 2 is a circuit diagram showing the configuration of the synchronous rectification bridge according to the first embodiment of the present invention. The synchronous rectification type bridge 100 includes a commercial AC voltage or an AC voltage converted by a switching power supply, for example, an AC input ACIN for inputting AC 24V, a DC output + DC for outputting a positive DC voltage, and a DC for outputting a negative DC voltage. Output-DC, N-channel type FETQ1, FETQ2, FETQ3, FETQ4, FETQ1, Q2 as a rectifying element, first driving circuit 110 for driving FETQ3, Q4, second driving circuit 120 for driving FETQ3, Q4, half of AC voltage And a comparison circuit (comparator) 130 for detecting a current in synchronization with the wave. In the figure, R1 to R4, R14 and R15 are resistors, C1 to C3 are capacitors, D1 to D4 are diodes, and D1p to D4p are parasitic diodes of FETs Q1, Q2, Q3 and Q4. The first and second drive circuits 110 and 120 are preferably constituted by a semiconductor integrated circuit, and preferably the synchronous rectification bridge 100 is housed in one module or package.

  A smoothing capacitor (not shown) is connected to the DC outputs + DC and -DC of the synchronous rectifier converter 100, and a load is further connected. An FET Q1 and an FET Q2, and an FET Q3 and an FET Q4 are connected in series between the direct current output + DC and the direct current output -DC. One AC input ACIN of the AC voltage is connected to the connection node N1 where the FET Q1 is connected to the FET Q2. A drive signal G1 output from the first drive circuit 110 is connected to the gate of the FET Q1, and a resistor R1 is connected between the gate and source of the FET Q1. A parasitic diode D1p is connected in parallel with the FET Q1 between the DC output DC + and the connection node N1.

  A drive signal G2 output from the first drive circuit 110 is connected to the gate of the FET Q2, and a resistor R2 is connected between the gate and source of the FET Q2. Between the DC output DC− and the connection node N1, a parasitic diode D2p is connected in parallel with the FET Q2.

  The other AC input ACIN of the AC voltage is connected to the connection node N2 where the FET Q3 is connected to the FET Q4. A drive signal G3 output from the second drive circuit 120 is connected to the gate of the FET Q3, and a resistor R3 is connected between the gate and source of the FET Q3. Between the DC output DC + and the node N2, a parasitic diode D3p is connected in parallel with the FET Q3.

  A drive signal G4 output from the drive circuit 120 is connected to the gate of the FET Q4, and a resistor R4 is connected between the gate and source of the FET Q4. A parasitic diode D4p is connected in parallel with the FET Q4 between the DC output DC− and the node N2.

  Resistors R 14 and R 15 are connected to the DC output DC−, and the resistor R 15 is connected to one input of the comparison circuit 130. The resistor R14 is connected to the node N3, and the capacitor C3 is connected between the node N3 and the resistor R15. The node N3 is connected to the other input of the comparison circuit 130.

  The comparison circuit 130 is synchronized with an input AC voltage, that is, a high level (positive voltage) or a low level (negative voltage) in response to a current flowing when the smoothing capacitor is charged or discharged. Outputs a voltage signal. This output is connected to the cathode of the diode D3, and the anode of the diode D3 is connected to the node N4. The node N4 is connected to the first input of the first drive circuit 110 and the second input of the second drive circuit 120, respectively.

  The output of comparison circuit 130 is further connected to the cathode of diode D4, and the anode of diode D4 is connected to node N5. The node N5 is connected to the second input of the first drive circuit 110 and the first IN of the second drive circuit 120, respectively.

  Next, the operation of the synchronous rectification bridge will be described. The comparison circuit 130 detects a current flowing when the smoothing capacitor is charged or discharged, and outputs a high level voltage when the current is detected. When the output of the comparison circuit 130 is at a high level, the diodes D3 and D4 are disabled, and a constant high voltage is held at the nodes N4 and N5. On the other hand, when no current is detected by the comparison circuit 130, the output of the comparison circuit 130 is a low level voltage, and the diodes D3 and D4 are conductive, so that the nodes N4 and N5 are at a low voltage.

  When the nodes N4 and N5 have a high voltage, a high voltage signal is input to the first and second inputs of the first and second drive circuits 110 and 120, and the corresponding drive signals G1, G2, and G3 , G4 becomes high level, and FETs Q1, Q2, Q3, Q4 are turned on. In other words, a high level gate signal is supplied to FETQ1, FETQ2, FETQ3, and FETQ4 during a period when a constant current is detected by the comparison circuit 130, and the FETQ1, FETQ2, FETQ3, and FETQ4 are in an operable on state. Placed.

  On the other hand, when the nodes N4 and N5 are at a low voltage, the first and second inputs of the first and second drive circuits 110 and 120 are at low level, and the corresponding drive signals G1, G2, G3, and G4 are at low level. The FETs Q1, Q2, Q3, and Q4 are turned off. That is, FETQ1, FETQ2, FETQ3, and FETQ4 are placed in an off state during a period when no current is detected by the comparison circuit 130.

  When a positive AC voltage is applied to the AC input ACIN while the output of the comparison circuit 130 is at a high level, the AC current is applied from the node N1 to the diode-connected FET Q1, DC output + DC, smoothing capacitor , DC output-DC, diode-connected FET Q4, and node N2. When a negative AC voltage is applied, the AC current flows through the path of node N2, diode-connected FET Q3, DC output + DC, smoothing capacitor, DC output -DC, diode-connected FET Q2, and node N1. . Thus, the AC voltage is rectified every half wave.

  In the above embodiment, since the FETs Q1 to Q4 are in the operating state during the period of current flow, the AC voltage can be rectified safely and efficiently. In addition, although the example which converts the AC voltage of AC24V into the DC voltage was shown in the said Example, it is applicable also to the AC voltage of AC100V. In particular, in the case of a converter having a large input of 10 amperes or more, the effect of reducing the power loss by using the FET is great.

  Furthermore, although the power supply system of the gaming machine uses an AC power supply of 24V AC, the load is very large and the input current is also very large. For this reason, if the AC-DC converter of the present embodiment is applied to a power supply system, it is possible to significantly reduce power loss as compared with conventional rectification by a diode bridge.

  In the first embodiment, the example in which the current flowing through the smoothing capacitor is detected by the comparison circuit 130 and the FETs Q1 to Q4 are operated in synchronization with this is shown. However, the current is detected by other means. Also good. Also

  Next, a synchronous rectification type bridge according to a second embodiment of the present invention is shown in FIG. The basic operation of the synchronous rectification bridge 100A according to the second embodiment is the same as that of the synchronous rectification bridge 100 of the first embodiment. However, in the first embodiment, the comparison circuit flows through the resistor R14. Since the current is detected, if the current is large, power loss cannot be ignored. Therefore, in the second embodiment, instead of using the resistor R14 or the like, the on-resistance of the FETs Q2 and Q4 or the current flowing therethrough is detected.

  The drain and source of the FET Q2 are connected to each input of the comparison circuit 130A, and the output is connected to the node N6. The node N6 is connected to the first input of the first drive circuit 110 and the second input of the second drive circuit 120. Similarly, the drain and source of the FET Q4 are connected to each input of the comparison circuit 130B, and the output is connected to the node N7. The node N7 is connected to the second input of the first drive circuit 110 and the first input of the second drive circuit 120.

  As described above, when a current flows through the FET Q4, this current is detected by the comparison circuit 130B, the output of the comparison circuit 130B becomes a high level voltage, and the node N7 becomes a high level. As a result, the first input of the first drive circuit 110 and the second input of the second drive circuit 120 become high level, the drive signals G1 and G4 become high level, and the FETQ1 and FETQ4 are turned on.

  Similarly, when a current flows through the FET Q2, this current is detected by the comparison circuit 130A, the output of the comparison circuit 130A becomes high level, and the node N6 becomes high level. As a result, the second input of the first drive circuit 110 and the first input of the first drive circuit 120 are at the high level, the drive signals G2 and G4 are at the high level, and the FETs Q2 and Q4 are turned on.

  In the first and second embodiments, the first and second drive circuits 110 and 120 are configured by semiconductor integrated circuits. However, instead of the integrated circuits, a plurality of electronic components (resistors, capacitors, A similar drive circuit may be configured by discrete components such as transistors.

  Next, a synchronous rectification type bridge according to a third embodiment of the present invention is shown in FIG. The synchronous rectification bridge 100B according to the third embodiment uses a current transformer 200 to control switching of the FETs Q1 to Q4. The current transformer 200 converts a current into a voltage according to the winding and supplies a gate signal to each of the FETs Q1 to Q4. The current transformer 200 preferably includes a plurality of low frequency transformers, and converts the current into a voltage corresponding to the winding. The operations of the FETs Q1 to Q4 are the same as in the first embodiment.

  Next, the power loss of the synchronous rectification bridge according to the present embodiment and the conventional diode bridge will be compared. FIG. 5A shows a rectifier circuit using a conventional diode bridge, and FIG. 5B shows a synchronous rectifier bridge using a transistor of the present invention. Here, it is assumed that the AC voltage input to the diode bridge in FIG. 5A is 24 V and the output is 300 W. Since the input current is 300/24 = 12.5 A and the forward voltage drop of the Schottky diode is about 0.6 V, the loss due to the diode bridge is 0.6 × 2 × 12.5 = 15 W.

On the other hand, it is assumed that the AC voltage input to the synchronous rectification bridge in FIG. 5B is 24 V and the output is 300 W. The input current is 300/24 = 12.5 A, and the on-resistance of the MOSFET is 3 mΩ × 2 (for series connection). Therefore, loss due to the synchronous rectification bridge becomes 12.5 ² × 0.006 = 0.9375W. As described above, the synchronous rectification type bridge according to this embodiment can significantly reduce the power loss as compared with the conventional rectifier circuit using the diode bridge. These comparisons are examples, but it goes without saying that even if the input AC voltage is 100 V, the power loss can be similarly reduced. Further, since the MOSFET itself used for the synchronous rectification type bridge can be made to have a very small on-resistance (about 1/10) as compared with the conventional MOEFET, the synchronous rectification as in this embodiment is performed. The effectiveness of the type bridge is significantly improved.

  FIG. 6 is a diagram showing a preferred package example of the synchronous rectification bridge of the present embodiment. As shown in FIG. 6A, a package (semiconductor device) 300 including a synchronous rectification bridge includes a synchronous rectification bridge shown in FIG. Lead terminals 320, 324, 326, and 328 extend from the bottom surface of the mold resin 310 to the outside. The lead terminals 320 to 328 are connected to an AC input ACIN and DC outputs DC + and DC−. As shown in FIG. 6B, the package 300A may be provided with a heat sink 330 so that the heat generated by the synchronous rectification bridge is released to the outside. The synchronous rectification type bridge can be modularized or packaged using other members such as ceramic in addition to the mold resin.

  The synchronous rectifier bridge according to the present invention is used in a power supply device or a power supply system that converts an AC power generated by a commercial AC power supply or a switching power supply into a DC power supply.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to specific embodiments, and various modifications may be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

  For example, MOSFETs, capacitors, and resistors can be changed as appropriate in order to achieve a circuit configuration equivalent to the operation of the synchronous rectification bridge shown in FIG. Furthermore, the present invention does not limit the AC voltage, DC voltage, or load to a specific magnitude.

It is a figure which shows the structure of the conventional AC-DC converter. It is a circuit diagram which shows the structure of the synchronous rectification type bridge | bridging which concerns on 1st Example of this invention. It is a circuit diagram which shows the structure of the synchronous rectification type bridge | bridging concerning 2nd Example of this invention. It is a circuit diagram which shows the structure of the synchronous rectification type bridge | bridging which concerns on 3rd Example of this invention. It is a figure explaining the loss comparison of the synchronous rectification type bridge | bridging of a present Example, and the conventional diode bridge. It is a figure which shows the structural example of the package which incorporates the synchronous rectification type bridge | bridging of a present Example.

Explanation of symbols

100: synchronous rectification type bridge 110, 120: driving circuit 130, 130A, 130B: comparison circuit 200: current transformer 300, 300A: package 310: mold resin 320, 322, 324, 326: lead terminal 330: heat sink ACIN: AC input DC +, DC-: DC output

Claims (6)

A synchronous rectification type bridge that converts an input AC voltage into a DC voltage and outputs the DC voltage,
First and second MOS transistors connected in series between a direct current output of a first potential and a direct current output of a second potential;
Third and fourth MOS transistors connected in series between the first and second potential DC outputs;
Driving means for outputting a gate signal to each gate of the first, second, third, and fourth MOS transistors in response to a current flowing through the DC output;
One input of the AC voltage is connected to a first connection node that connects the first and second MOS transistors, and the other input of the AC voltage is a second that connects the third and fourth MOS transistors. Connected to the connection node,
In response to the input AC voltage, current flows in the first and fourth MOS transistors during the first half-wave period, and in the second and third MOS transistors during the second half-wave period. Synchronous rectification type bridge through which current flows. The driving means includes a comparison circuit that detects a current flowing through the DC output, and controls each gate signal of the first, second, third, and fourth MOS transistors in response to a detection result of the comparison circuit. The synchronous rectification type bridge according to claim 1. 3. The synchronous rectification bridge according to claim 2, wherein each gate signal of the first, second, third, and fourth MOS transistors turns on each MOS transistor while a current is detected by the comparison circuit. . The driving means includes first and second comparison circuits, the first comparison circuit detects the operation state of the second MOS transistor, and the second comparison circuit operates in the operation state of the fourth MOS transistor. The driving means controls each gate signal of the first, second, third, and fourth MOS transistors in response to detection results of the first and second comparison circuits. The synchronous rectification type bridge described. One input of the first comparison circuit is connected to the source of the second MOS transistor, the other input is connected to the drain, and one input of the second comparison circuit is the source of the fourth MOS transistor. 5. The synchronous rectification bridge according to claim 4, wherein the other input is connected to the drain, and the first and second comparison circuits detect currents flowing through the second and fourth MOS transistors. 6. A package for a synchronous rectification type bridge including the synchronous rectification type bridge according to any one of claims 1 to 5 and further including two external terminals for inputting an AC voltage and two external terminals for outputting a DC output.

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