JP2009277138A - Semiconductor integrated circuit device, bus device, and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, a bus device, and a data transfer method which can correspond to a plurality of security categories while keeping data concealment. <P>SOLUTION: The semiconductor integrated circuit device comprises: semiconductor devices 2 to 5; decryption circuits 10, 11 which decrypt encrypted data including first attribute information Attr1 showing a transfer destination of the data and add second attribute information Attr2 showing a notice that the data have been decrypted; a bus device 14 which connects the semiconductor devices 2 to 5 and the decryption circuits 10, 11 so as to transfer data therebetween; a transfer circuit 3 which transfers the data decrypted by the decryption circuit 10 to the semiconductor devices 2 to 5; and interceptors 6 to 9 which intercept the transfer of the data to the semiconductor device in the case that when the first attribute information Attr1 and the second attribute information Attr2 are confirmed, the transfer destination as decrypted data shown by the first attribute information Attr1 does not agree with the semiconductor devices 2 to 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, a bus device, and a data transfer method. For example, the present invention relates to a method for protecting encrypted data.

  In recent semiconductor integrated circuits (LSIs), the importance of data protection technology is increasing. In particular, handling of data after decrypting the encrypted data is important.

  In this regard, a method has been proposed in which information indicating that the data is decoded data is added to the decoded data (see Non-Patent Document 1, for example). According to this method, when the above information is added to the data, the data blocker blocks the transfer of the data to the predetermined hardware. Therefore, it is possible to prevent the data to be protected from being inadvertently transferred to the hardware.

However, according to the conventional method, hardware capable of transferring data to be protected is determined at the time of manufacturing the LSI, and there is a problem that it is difficult to flexibly cope with each data. That is, for example, when there are a plurality of security categories, it is difficult to transfer data such as prohibiting the transfer of data in a certain security category and permitting the transfer of data in a lower category.
"Security Enhanced Embedded Processor using Local Memory Protection Mechanism", Takeshi Kawabata, Takanori Tamai, Mikio Hashimoto, and Takashi Miyamoti, Proceedings of the IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX), April 19-21, 2006, pp. 143-157.

  The present invention provides a semiconductor integrated circuit, a bus device, and a data transfer method that can handle a plurality of security classifications while ensuring data confidentiality.

  A semiconductor integrated circuit device according to an aspect of the present invention includes a semiconductor device, and second attribute information including first attribute information indicating a data transfer destination and decrypting the encrypted data and indicating that the data has been decrypted A decoding circuit for adding the decoded data to the semiconductor device, a transfer circuit for transferring the data decoded by the decoding circuit together with the second attribute information to the semiconductor device, the semiconductor device and the transfer circuit, The first attribute information and the second attribute information for the data transferred via the bus device by the transfer circuit, and the data is encrypted. And when the transfer destination indicated by the first attribute information is inconsistent with the semiconductor device, the data is decoded to the semiconductor device. ; And a blocking device for blocking the transfer.

  A bus device according to one aspect of the present invention is a bus device that is connectable to a semiconductor device and transfers data to the semiconductor device, the data transfer line transferring the data given from the outside, Based on information included in the data transferred by a data transfer line, the data is data that has been returned to plain text from an encrypted state and is prohibited from being transferred to the semiconductor device. And a blocking device that blocks transfer to the semiconductor device when it is determined.

  Furthermore, the data transfer method according to an aspect of the present invention includes the step of obtaining the second data by decrypting the encrypted first data including the first attribute information indicating the transfer destination, and the second data And adding the second attribute information indicating the decryption, obtaining the third data, transferring the third data to the bus device using the semiconductor device as the transfer destination, and transferring the data to the bus device. For the data, the first attribute information and the second attribute information are checked, and the first attribute information and the second attribute information are checked. As a result, the third data is decrypted from the encrypted state. If the transfer destination indicated by the first attribute information does not match the semiconductor device, the transfer of the third data to the semiconductor device is interrupted, and otherwise the third data Before And a step of allow transfer to the semiconductor device.

  According to the present invention, it is possible to provide a semiconductor integrated circuit, a bus device, and a data transfer method that can cope with a plurality of security classifications while ensuring data confidentiality.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor integrated circuit device, a bus device, and a data transfer method according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a semiconductor integrated circuit device according to this embodiment.

<Overall Configuration of Semiconductor Integrated Circuit Device>
As shown in the figure, a semiconductor integrated circuit device (LSI) 1 includes a RAM 2, a DMA (Direct Memory Access) controller 3, hardware engines 4 and 5, data blockers 6 to 9, a decoding circuit 10, an attribute adding device 11, and a memory 12. The selector device 13 and the bus 14 are provided. When the RAM 2, the DMA controller 3, and the hardware engines 4 and 5 are not distinguished from each other, they may be collectively referred to as “hardware”.

  The RAM 2 is a semiconductor memory such as a flash memory, and holds various data. Any of the data to be held is encrypted data. The encrypted data is net data and includes secret data to be protected and transfer destination information that is a transfer destination of the secret data, and is encrypted together.

  The DMA controller 3 controls data transfer between the RAM 2 and the hardware engines 4 and 5. The DMA controller 3 has two modes of data transfer mode, that is, protection transfer and normal transfer. The protected transfer is a mode for transferring plaintext data obtained by decrypting the encrypted data, and the normal transfer is a mode for other cases. That is, the transfer mode in the case of transferring data that should be considered confidentiality is protected transfer. The DMA controller 3 sets the transfer mode signal MODE to “1”, for example, when performing protected transfer, and “0” when performing normal transfer. The transfer mode signal MODE is given to the selector device 13. Details of the DMA controller 3 will be described later.

  The hardware engines 4 and 5 are functional blocks for executing predetermined functions such as image processing and wireless communication. And the process for performing a predetermined | prescribed function is performed using the data in RAM2.

  The data blockers 6 to 9 are provided in association with the RAM 2, the DMA controller 3, and the hardware engines 4 and 5, respectively. In addition, the transfer block identification number DstNo is input to the data blockers 6 to 9. The transfer destination identification number DstNo is a number added according to the hardware to which each data blocker 6-9 corresponds, and the transfer destination identification number DstNo for the RAM 2, the DMA controller 3, and the hardware engines 4, 5 is, for example, They are “1”, “2”, “3”, and “4”, respectively. Therefore, “1” to “4” are given to the data blockers 6 to 9 as transfer destination identification numbers DstNo, respectively. Each of the data blockers 6 to 9 is based on the transfer destination identification number DstNo, the first attribute information Attr1 and the second attribute information Attr2 transferred together with the data, the RAM 2, the DMA controller 3, and the hardware engines 4, 5 Block data transfer to. Details of the first attribute information Attr1, the second attribute information Attr2, and the data blockers 6 to 9 will be described later.

  The decryption circuit 10 decrypts the encrypted data provided from the DMA controller 3 using a decryption key. The decrypted data includes the above-described secret data and transfer destination information. Then, the decryption circuit 10 outputs the decrypted secret data and the transfer destination information to the attribute adding device 11.

  The memory 12 is a semiconductor memory, for example, and holds a decryption key table in which a decryption key used in the decryption circuit 10 is recorded. Then, the memory 12 outputs a necessary decryption key to the decryption circuit 10 in accordance with an instruction from the DMA controller 3.

  The attribute adding device 11 separates the secret data and the transfer destination information in the decrypted data given from the decryption circuit 10 and outputs the separated data to the selector device 13. At this time, the attribute adding device 11 outputs the transfer destination information to the selector device 13 as the first attribute information Attr1. Further, when receiving the secret data from the decryption circuit 10, the attribute adding device 11 asserts the second attribute information Attr2 (in this embodiment, “1”) and outputs it to the selector device 13. That is, the first attribute information Attr1 is information on hardware that is permitted as a destination of the secret data with respect to certain secret data. The second attribute information Attr2 is information indicating whether or not certain data is data decrypted from the encrypted state.

  The selector device 13 includes a first selector 20 and a second selector 21. The first selector 20 and the second selector 21 are, for example, multiplexers.

  The first selector 20 selects either the decrypted secret data given from the attribute adding device 11 or the data given directly from the DMA controller 3. More specifically, when the transfer mode signal MODE = “1”, the data given from the attribute adding device 11 is selected, and when it is “0”, the data given directly from the DMA controller 3 is selected. To do. Then, the selected data is output to the bus 14. That is, in the case of protected transfer, the decrypted secret data is output to the bus 14, and in the case of normal transfer, the data given from the RAM 2 to the DMA controller 3 is output to the bus 14 as it is.

  The second selector 21 selects either the first attribute information Attr1 and the second attribute information Attr2 given from the attribute adding device 11 or “0”. More specifically, when the transfer mode signal MODE = “1”, the first and second attribute information Attr 1 and Attr 2 given from the attribute adding device 11 are selected and output to the bus 14. On the other hand, when MODE = “0”, “0” is selected, and the first attribute information Attr1 = “0” and the second attribute information Attr2 = “0” are output to the bus 14.

  The bus 14 transfers data between the RAM 2, the DMA controller 3, and the hardware engines 4 and 5. The bus 14 has master interfaces IF1, IF3, IF4 and a slave interface IF2. The master interfaces IF1, IF3, and IF4 are connected to the RAM 2, the hardware engine 4, and the hardware engine 5, respectively. The slave interface IF2 is connected to the DMA controller 3. In each interface IF1 to IF4, signals output from outlets OUT1 to OUT4 described later are connected to data blockers 6 to 9, respectively.

<About bus 14>
Next, signals transmitted through the bus 14 will be described with reference to FIG. FIG. 2 is a conceptual diagram showing input / output signals of the bus. The master interfaces IF1, IF3, IF4 and the slave interface IF2 have signal transmission directions reversed. The slave interface IF2 can receive a transfer request from the outside of the bus 14, and can be connected to a DMA controller or the like that controls data transfer. Of the signals output from the bus 14, portions where data signals and first attribute information and second attribute information described later are output are referred to as outlets OUT <b> 1 to OUT <b> 4, respectively. In the figure, the description of the master interface IF1 is omitted, but it is equivalent to the master interface IF3 or IF4. Similarly to the outlets OUT3 and 4, the outlet OUT1 is also defined.

As shown in the figure, the bus 14 has roughly four signal sequences.
First, a control signal sequence. An example of the control signal is a request signal Request and an enable signal R / W_Enable, each of which is a 1-bit signal. The request signal Request is a signal for requesting transmission / reception of data to the transfer destination hardware, and the enable signal R / W_Enable is for enabling reading or writing of data to the transfer destination hardware. Signal.

Next, a series of data signals. There are two types of data signals, read-out read data Read_Data and write-in data Write_Data to be written, which are independent as signal lines. Each is a 32-bit signal, for example.
The write data output from the first selector 20 of the selector device 13 becomes the input signal Write_Data to the slave interface IF2. The data blockers 6, 8 and 9 respectively block or pass the data signal Write_Data supplied from the corresponding master interfaces IF1, IF3 and IF4. The data blocker 7 blocks or allows propagation of the data signal Read_Data of the slave interface IF2. The signals that the data blockers 6, 8 and 9 and the data blocker 7 block or pass are different from the signal Write_data and the signal Read_Data, respectively. This is whether the connected interface is the master interface or the slave interface. The only difference is whether it is an interface. Each data blocker has the same function.

  Next, an address signal Address. The address signal is a signal indicating an address of hardware that is a destination to which data is to be transferred.

  Finally, the first attribute information Attr1 and the second attribute information Attr2. Each attribute information is associated with each of the signal Read_Data and the signal Write_Data. In FIG. 2, a signal Attr1 (R), a signal Attr1 (W), a signal Attr2 (R), and a signal Attr2 (W) are signals that transmit attribute information. Note that the character string (R) or (W) of each signal name indicates which data attribute is Read_Data or Write_Data. In addition, a signal for transmitting the attribute information is transferred in synchronization with the signal Read_Data and the signal Write_Data. Hereinafter, Attr1 (R) and Attr1 (W) may be simply referred to as Attr1, and Attr2 (R) and Attr2 (W) may be simply referred to as Attr2.

The first attribute information Attr1 indicates information on hardware that is permitted to transfer data. More specifically, a hardware transfer destination identification number DstNo that permits transfer of decrypted data is set in the first attribute information Attr1. In the present embodiment, the first attribute information Attr1 is, for example, a 3-bit signal.
The second attribute information Attr2 indicates that the encrypted state is returned to plain text. More specifically, the second attribute information Attr2 is a 1-bit signal, and when it is “1”, it is determined that the data to which the second attribute information Attr2 is attached is the data returned to the plain text. Show. Note that “0” (zero) is input to the signal Attr1 (R) and the signal Attr2 (R) of the master interface 1 to which the RAM 2 is connected. Therefore, when data read from the RAM 2 is transferred, the second attribute information Attr2 for the data is “0”. Further, the first attribute information Attr1 has an effective meaning only when the second attribute information Attr2 is “1”.

<Details of DMA Controller 3>
Next, details of the DMA controller 3 will be described with reference to FIG. 3, particularly focusing on the handling of signals read from the RAM 2. FIG. 3 is a flowchart showing the operation of the DMA controller 3. Hereinafter, only signals related to the present embodiment among signals transmitted through the bus 14 will be described. For example, even when the description is omitted below, the address signal Address or the like is naturally required when transferring data.

  As shown in the figure, when the data is read from the RAM 2, the DMA controller 3 transfers the data to the decryption circuit 10 when the data is encrypted (step S10, YES). Then, the DMA controller 3 instructs the decoding circuit 10 to decode the data (step S11). At this time, the memory 12 is instructed to give the necessary decryption key to the decryption circuit 10. In response to the instruction in step S11, the decryption circuit 10 decrypts the data using the decryption key.

  Further, the DMA controller 3 sets the transfer mode signal MODE to “1” and performs protected transfer (step S12). By setting the transfer mode signal MODE to “1”, the DMA controller 3 instructs the first selector 20 of the selector device 13 to select the secret data output from the attribute adding device 11 (step S13). Further, the second selector 21 is instructed to select the first and second attribute information Attr1 and Attr2 output from the attribute adding device 11 (step S14).

  As a result, the secret data decrypted by the decryption circuit 10 is output to the bus 14 as the write data Write_Data, and the transfer destination information stored in the encrypted data is output as the first attribute information Attr1. 1 ″ is output as the second attribute information Attr2.

  In step S10, if the data is not encrypted (step S10, NO), the DMA controller 3 sets the transfer mode signal MODE to “0” and performs normal transfer (step S15). By setting the transfer mode signal MODE to “0”, the DMA controller 3 instructs the first selector 20 of the selector device 13 to select data output from the DMA controller 3 (step S16). Further, the second selector 21 is instructed to select “0” as the first and second attribute information Attr1 and Attr2 (step S17).

  As a result, the data read from the RAM 2 is output to the bus 14 as it is as the write data Write_Data, and “0” is output as the first attribute information Attr1 and the second attribute information Attr2.

<Details of data blockers 6-9>
Next, details of the data blockers 6 to 9 will be described with reference to FIG. FIG. 4 is a flowchart showing the operation of the data blockers 6-9.

  When the data blockers 6 to 9 receive the data of the signals output from the outlets OUT1 to OUT4 of the bus 14, respectively, the data blockers 6 to 9 first check whether or not the data is decrypted from the encrypted state. That is, it is confirmed whether or not the second attribute information Attr2 is “1”.

  When the data is not decrypted, that is, when Attr2 = "0" (step S20, NO), the data blockers 6 to 9 permit transfer of the data to the corresponding hardware (step S20). S21). That is, the data output from the bus 14 is transferred to the hardware connected to the data blockers 6-9.

  On the other hand, when the data is decrypted, that is, when Attr2 = “1” (step S20, YES), the data blockers 6 to 9 are next connected to the corresponding hardware. It is determined whether or not the transfer destination is permitted. That is, it is determined whether or not the second attribute information Attr1 matches the transfer destination identification number DstNo.

  When they match, that is, when Attr1 = DstNo (step S22, YES), the process of step S21 is performed. On the other hand, when there is a mismatch, that is, when Attr1 ≠ DstNo (step S22, NO), the data blockers 6 to 9 block the transfer of the data to the corresponding hardware (step S23).

  Through the above processing, the data blockers 6 to 9 prevent the decrypted secret data from being transferred to hardware that is not permitted to transfer.

<Operation of LSI 1>
Next, the data transfer method in the LSI 1 having the above configuration will be described below by taking the case of data transfer from the RAM 2 to the hardware engine 4 as an example and dividing it into the case of the protected transfer and the case of the normal transfer. The same applies to data transfer between other hardware.

<About protected transfer>
First, protected transfer will be described with reference to FIG. FIG. 5 is a flowchart showing the flow of processing in the LSI 1. The flow of processing is roughly as follows: transfer of encrypted data from the RAM 2 to the DMA controller 3, decryption and setting of attribute information, and transfer of the decrypted data from the DMA controller 3 to the hardware engine 4. Includes three steps. Hereinafter, description will be made sequentially.

  First, the encrypted data is transferred from the RAM 2 to the DMA controller 3. That is, the DMA controller 3 reads the encrypted data from the RAM 2 (step S30). At this time, it is assumed that the encrypted data is data permitted to be transferred to the hardware engine 4 and holds DstNo = “3” as transfer destination information. In response to the instruction from the DMA controller 3, the bus 14 sets Attr2 = "0" and transfers the encrypted data to the data blocker 7 (step S31). Since Attr2 = “0”, the data blocker 7 transfers the encrypted data as it is to the DMA controller 3 (step S32).

  Next, decoding and setting of attribute information are performed. That is, the DMA controller 3 instructs the decryption circuit 10 to decrypt the encrypted data (step S33). The DMA controller 3 starts protected transfer with MODE = "1" (step S34). Then, the decryption circuit 10 decrypts the encrypted data given from the DMA controller 3 and outputs it to the attribute adding device 11 (step S35). Subsequently, the attribute adding device 11 sets Attr2 = “1”. Further, the transfer destination information “3” of the data is set to Attr1 (step S36).

  Next, data transfer of the decoded data from the DMA controller 3 to the hardware engine 4 is performed. That is, the selector device 13 selects the secret data output from the attribute adding device 11, Attr1 = "3" and Attr2 = "1", and outputs the selected data to the bus 14. The bus 14 transfers the secret data (write data Write_Data) output from the selector device 13 and Attr1 and Attr2 to the data blocker 8 corresponding to the hardware engine 4 that is the transfer destination (step S38). Then, since the data blocker 8 is Attr2 = “1” and Attr2 = DstNo = “3”, the data blocker 8 recognizes that the secret data is permitted to be transferred and transfers the secret data to the hardware engine 4. (Step S39).

  Thus, the secret data encrypted in the RAM 2 is transferred to the hardware engine 4. Even if this secret data is transferred to the data blockers 6, 7, and 9, since Attr1 does not match DstNo in the data blockers 6, 7, and 9, the data blockers 6, 7, and 9 are stored in the RAM 2, DMA controller. 3 and the transfer of the secret data to the hardware engine 5 is blocked (step S40).

<Regarding normal transfer>
Next, normal transfer will be described. Also in the case of normal transfer, first, the processes of steps S30 to S32 are performed, and the data is transferred to the DMA controller 3. However, the data is unencrypted data.

  The selector device 13 sets Attr1 = “0” and Attr2 = “0”, and outputs the Attr1 and Attr2 and the data output from the DMA controller 3 to the bus 14. The data blocker 8 then transfers the data to the hardware engine 4 without confirming Attr1 because Attr2 = "0".

<Effect>
With the LSI 1 according to the present embodiment, the following effect (1) can be obtained.

(1) It is possible to cope with a plurality of security classifications while ensuring data confidentiality.
With the configuration disclosed in Non-Patent Document 1, the hardware capable of transferring data to be protected is determined when the LSI is manufactured, as described in the background art. Therefore, whether to allow or block data transfer to a certain hardware is determined only by whether or not the data is encrypted. Therefore, although secrecy can be sufficiently secured, it has been difficult to cope with a plurality of security classifications.

  In this respect, the configuration according to the present embodiment encrypts the transfer destination information together with the secret data. The transfer destination information is hardware information that permits transfer of the secret data. After further decryption, the transfer destination information is added to the secret data as the first attribute information Attr1, and is output to the bus 14. The data blockers 6 to 9 permit the transfer of the secret data only when the added first attribute information Attr1 matches each transfer destination identification number DstNo.

  Therefore, it is possible to freely determine hardware as a transfer destination for each encrypted data. In other words, it is possible to set such that transfer of certain encrypted data is permitted to a certain hardware, and transfer of another encrypted data is permitted to another hardware.

  Further, when the added first attribute information Attr1 does not match each transfer destination identification number DstNo, the data blockers 6 to 9 block the transfer of the secret data. Therefore, the confidentiality of the secret data can be sufficiently secured.

  Therefore, it is possible to cope with a plurality of security classifications while sufficiently securing data confidentiality.

[Second Embodiment]
Next explained is a semiconductor integrated circuit device, a bus device and a data transfer method according to the second embodiment of the invention. In the present embodiment, a hash is embedded in the encrypted data in the first embodiment. FIG. 6 is a block diagram of the LSI 1 according to the present embodiment. Hereinafter, only differences from the first embodiment will be described.

  As illustrated, the encrypted data according to the present embodiment includes a hash value in addition to the secret data and the transfer destination information (Attr1), and these are encrypted. Further, the LSI 1 according to the present embodiment includes a hash value confirmation circuit 15. The hash value confirmation circuit 15 will be described with reference to FIG. FIG. 7 is a flowchart showing the operation of the hash value confirmation circuit 15.

  As illustrated, the hash value confirmation circuit 15 first receives the decrypted data (secret data, transfer destination information, and hash value) from the decryption circuit 10 (step S50). Then, the hash value is confirmed in the decrypted data (step S51).

  As a result of step S51, when the decrypted secret data does not match the hash value (step S52, NO), the hash value confirmation circuit 15 prohibits the DMA controller 3 from transferring the data (step S53). ). In this case, the decrypted data may not be transferred to the attribute adding device 11.

  On the other hand, as a result of step S51, when the decrypted secret data matches the hash value (step S52, YES), the hash value confirmation circuit 15 permits the transfer of the data, and the decrypted secret data and the transfer destination The information is transferred to the attribute adding device 11 (step S54).

<Effect>
In the LSI 1 according to the present embodiment, the following effect (2) is obtained in addition to the effect (1) described in the first embodiment.

(2) The falsification resistance of data can be increased.
In the configuration according to the present embodiment, the hash value together with the secret data is encrypted. After the data is decrypted, the hash value confirmation circuit 15 compares the secret data with the hash value, and permits the transfer of the secret data only when they match. Therefore, when the secret data is falsified, the data transfer is blocked, and the data falsification resistance can be improved.

[Third Embodiment]
Next explained is a semiconductor integrated circuit device, a bus device and a data transfer method according to the third embodiment of the invention. This embodiment relates to the handling of the bus after the secret data transfer in the first and second embodiments. Hereinafter, only differences from the first and second embodiments will be described.

  FIG. 8 is a block diagram schematically showing the internal configuration of the bus 14 according to the present embodiment. As illustrated, the bus 14 has a configuration in which a plurality of flip-flops 30 are connected in series. Then, the data is sequentially transferred through the flip-flop 30 to be transmitted to the destination hardware. The bus 14 further includes a selector 31 provided in front of the front-stage flip-flop 30. The selector 31 selects either data to be transferred or “0” in accordance with the first attribute information Attr1, and inputs the selected data to the flip-flop 30 at the foremost stage. More specifically, “0” is selected when Attr1 = “7”, and data to be transferred is selected otherwise.

  Next, the operation of the DMA controller 3 according to the present embodiment will be described with reference to FIG. FIG. 9 is a flowchart showing the operation of the DMA controller 3 immediately after the transfer of the decoded data.

  As shown in the drawing, the DMA controller 3 starts the pseudo transfer when the transfer of the decrypted data is completed (step S60). The pseudo transfer is a process of transferring fixed data into the flip-flop 30 in the bus 14 without transferring data to any hardware. In order to instruct the pseudo transfer, the DMA controller 3 sets the first attribute information Attr1 to “7” (all bits of Attr1 are set to “1”), and outputs it from the selector device 13 to the bus 14 (step S61). When Attr1 is set to “7”, the selector device 13 recognizes that the pseudo transfer has started and does not output write data to the bus 14. Alternatively, even if write data is output by the selector device 13, the bus 14 does not accept the write data.

  In the bus 14 that has received Attr1 = "7", the selector 31 selects "0" and sequentially transfers it to the flip-flop 30 (step S62). As a result, “0” is stored in all the flip-flops 30 included in the bus 14 (step S63).

<Effect>
In the LSI 1 according to the present embodiment, the following effect (3) is obtained in addition to the effects (1) and (2) described in the first and second embodiments.

(3) The confidentiality of data can be further improved.
Usually, the bus 14 is constituted by a set of flip-flops. After the data transfer, the transferred data may remain in the flip-flop in some cases. Then, if the secret data remains in the flip-flop, the secret data may be leaked by forcibly accessing the bus from the outside.

  However, in the configuration according to the present embodiment, the DMA controller 3 stores the fixed value “0” in the flip-flop 30 in the bus 14 after transferring the secret data (pseudo transfer). That is, the bus 14 is initialized. Accordingly, it is possible to prevent the secret data from leaking from the flip-flop 30 and further improve the confidentiality of the data.

  Note that the data stored in the flip-flop 30 in the pseudo transfer is not limited to “0”, and may be “1” or random data, for example. In the above embodiment, when performing pseudo transfer, the case where all bits of Attr1 are set to “1” has been described as an example. However, of course, the present invention is not limited to this, and for example, a bit dedicated to pseudo transfer is added. Alternatively, a dedicated signal may be provided.

  The selector 31 may be provided for each flip-flop 30. The configuration in such a case is shown in FIG. FIG. 10 is a block diagram of the bus 14. As shown in the figure, a selector 31 is provided at the input stage of each flip-flop 30. With this configuration, it is not necessary to sequentially transfer “0” to the plurality of flip-flops 30 and pseudo transfer can be performed at high speed. Of course, it is not necessary to provide all the flip-flops 30, but it may be provided every other plurality.

  As described above, in the semiconductor integrated circuit device according to the first to third embodiments of the present invention, the secret data is encrypted together with the first attribute information indicating the transfer destination of the secret data. Further, the attribute adding device 11 adds the second attribute information indicating that the encrypted data has been decrypted and the first attribute information to the decrypted secret data. When the data blockers 6 to 9 are transferred data in plain text, and the transfer destination indicated by the first attribute information is inconsistent with the corresponding hardware 2 to 5, Block data transfer.

  Therefore, it is possible to freely determine hardware as a transfer destination for each encrypted data. As a result, it is possible to cope with a plurality of security classifications while sufficiently securing data confidentiality.

  In the first to third embodiments, the transfer destination identification number DstNo is described as an example in which the data blockers 6 to 9 are numbers added according to the corresponding hardware 2 to 5. However, the same applies to numbers added according to the outlets OUT1 to OUT4 of the bus 14 instead of depending on the hardware. If the first attribute information Attr1 is a hardware address itself, the data blockers 6 to 9 may compare the first attribute information Attr1 and the address signal Address.

  Further, the data blockers 6 to 9 may be provided inside the bus 14. The configuration of such a bus 14 is shown in FIG. In FIG. 11, only the exit of the bus 14 and the corresponding data blockers 6 to 9 are shown, and the description of the interface and the like is omitted. As shown in the figure, the bus 14 includes a data transfer line 40 for transferring data and the data blockers 6 to 9 described above. The data blockers 6 to 9 are data whose data has been returned to plaintext based on information (Attr1, Attr2) included in the data transferred by the data transfer line 40, and corresponding semiconductor devices (RAM2, When the data is prohibited from being transferred to the DMA controller 3 and the hardware engines 4 and 5), the transfer to the semiconductor device is blocked.

  Further, the first attribute information Attr1 indicating the transfer destination may not be the transfer destination identification number DstNo itself. That is, for example, Attr1 is a 4-bit signal, and each bit corresponds to RAM2, DMA controller 3, and hardware engines 4 and 5, and is transferred to the hardware corresponding to the bit set to “1”. It may be allowed. For example, it is assumed that Attr1 = (b1, b2, b3, b4), and each of b1 to b4 corresponds to the RAM 2, the DMA controller 3, and the hardware engines 4, 5. Then, if Attr1 = (1000), the transfer to the RAM 2 is permitted, and the transfer to the DMA controller 3 and the hardware engines 4 and 5 is blocked. If Attr1 = (1110), transfer to the RAM 2, the DMA controller 3, and the hardware engine 4 is permitted, and transfer to the hardware engine 5 is blocked. That is, the data blockers 6 to 9 check any of their corresponding bits b1 to b4, and if the bit is “1”, transfer is permitted, and if it is “0”, the data blocker 6 to 9 is blocked. In this case, for example, pseudo transfer may be performed when Attr1 = (0000).

  That is, the bus 14 includes a plurality of holding circuits 30 that sequentially transfer data input from the outside, and the transfer circuit 3 outputs a request (for example, a bus initialization command) to the bus 14 after the data transfer is completed. In accordance with this request, the bus 14 overwrites part or all of the holding circuit 30 with a predetermined value.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram of an LSI according to a first embodiment of the present invention. The conceptual diagram which shows the signal in the bus | bath which concerns on 1st Embodiment of this invention. 5 is a flowchart showing the operation of the DMA controller according to the first embodiment of the present invention. The flowchart which shows operation | movement of the data blocker which concerns on 1st Embodiment of this invention. 3 is a flowchart showing the operation of the LSI according to the first embodiment of the present invention. The block diagram of LSI concerning the 2nd Embodiment of this invention. The flowchart which shows operation | movement of the hash value confirmation circuit which concerns on 2nd Embodiment of this invention. The block diagram of the bus | bath which concerns on 3rd Embodiment of this invention. 10 is a flowchart showing operations of a DMA controller and a bus according to a third embodiment of the present invention. The block diagram of the bus | bath which concerns on the modification of 3rd Embodiment of this invention. The block diagram of the bus | bath which concerns on the modification of the 1st thru | or 3rd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... LSI, 2 ... RAM, 3 ... DMA controller 4, 5 ... Hardware engine 4, 6-9 ... Data blocker, 10 ... Decoding circuit, 11 ... Attribute addition apparatus, 12 ... Memory, 13 ... Selector apparatus, 14 ... Bus 15 ... Hash value confirmation circuit 20, 21, 31 ... Selector 30 ... Flip-flop 30, 40 ... Data transfer line

Claims (5)

A semiconductor device;
A decryption circuit including first attribute information indicating a data transfer destination and decrypting the encrypted data, and adding second attribute information indicating the decryption to the decrypted data;
A transfer circuit for transferring the data decoded by the decoding circuit to the semiconductor device together with the second attribute information;
A bus device that connects the semiconductor device and the transfer circuit so that data can be transferred;
For the data transferred via the bus device by the transfer circuit, the first attribute information and the second attribute information are confirmed, and the data is decrypted from an encrypted state, And a shut-off device that shuts off transfer of the data to the semiconductor device when the transfer destination indicated by the first attribute information does not match the semiconductor device. . The data further includes a hash value;
The hash value confirmation circuit that compares the data decrypted by the decryption circuit with the hash value and stops transfer of the data when they do not match is further provided. The semiconductor integrated circuit device described. The bus device includes a plurality of holding circuits that sequentially transfer data input from the outside,
The semiconductor integrated circuit device according to claim 1, wherein the transfer circuit transfers predetermined data to the bus device after completion of the data transfer. A bus device that is connectable to a semiconductor device and transfers data to the semiconductor device,
A data transfer line for transferring the data given from the outside;
Based on information included in the data transferred by the data transfer line, the data is returned to plain text from an encrypted state and is prohibited from being transferred to the semiconductor device. And a blocking device that blocks transfer to the semiconductor device when it is determined. Decrypting the encrypted first data including the first attribute information indicating the transfer destination to obtain the second data;
Adding second attribute information indicating decryption to the second data to obtain third data;
Transferring the third data to a bus device using a semiconductor device as a transfer destination;
Checking the first attribute information and the second attribute information for the data transferred to the bus device;
As a result of checking the first attribute information and the second attribute information, the third data is data decrypted from the encrypted state, and the transfer destination indicated by the first attribute information is the semiconductor device. A step of blocking the transfer of the third data to the semiconductor device if not, and a step of permitting transfer of the third data to the semiconductor device otherwise. Data transfer method.

Images