JP2009266994A - Semiconductor device, and mounting structure thereof - Google Patents

Semiconductor device, and mounting structure thereof Download PDF

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JP2009266994A
JP2009266994A JP2008113508A JP2008113508A JP2009266994A JP 2009266994 A JP2009266994 A JP 2009266994A JP 2008113508 A JP2008113508 A JP 2008113508A JP 2008113508 A JP2008113508 A JP 2008113508A JP 2009266994 A JP2009266994 A JP 2009266994A
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semiconductor device
dummy
columnar electrode
semiconductor substrate
columnar
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JP2009266994A5 (en
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Masahiro Ezuka
正博 江塚
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an arrangement region of existing columnar electrodes from being limited even if a dummy columnar electrode is included for enhancing joining force at mounting. <P>SOLUTION: In a semiconductor device 1, a dummy columnar electrode 15 is provided at the periphery under a silicon substrate 2, and a columnar electrode 14 is provided in the region other than the peripheral part under the silicon substrate 2. Therefore, the arrangement region for the existing columnar electrodes 14 is hard to be limited. By joining the dummy columnar electrode 15 of the semiconductor device 1 to a dummy connection pad 24 of a circuit board 21 through a solder 28, the joining force at mounting is raised. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は半導体装置およびその実装構造に関する。   The present invention relates to a semiconductor device and a mounting structure thereof.

従来の半導体装置には、ＣＳＰ(chip size package)と呼ばれるもので、半導体基板上に複数の配線が設けられ、配線の接続パッド部上に柱状電極が設けられ、柱状電極の周囲に封止膜が設けられ、柱状電極上に半田ボールが設けられたものがある。このような半導体装置を回路基板上に実装する場合は、回路基板の実装面に形成された接続端子に上記半導体装置の半田ボールを位置合せして搭載し、リフロー炉に導入して半田付けするのが一般的である。   A conventional semiconductor device is called a CSP (chip size package). A plurality of wirings are provided on a semiconductor substrate, columnar electrodes are provided on connection pads of the wirings, and a sealing film is formed around the columnar electrodes. And a solder ball is provided on the columnar electrode. When mounting such a semiconductor device on a circuit board, the solder balls of the semiconductor device are aligned and mounted on connection terminals formed on the mounting surface of the circuit board, and introduced into a reflow furnace and soldered. It is common.

しかるに、近年では、回路基板の実装密度が高まり、配線の幅および接続端子の径が小さくなっており、これに対応して半導体装置の外部接続用電極である柱状電極の径が小さくなり、これに合わせて、半田ボールの径も小さくなっている。このような場合、回路基板の接続端子と半導体装置との半田付けの総面積が小さくなるため、半田付けの接合強度が不足する傾向が生じている。   However, in recent years, the mounting density of circuit boards has increased, and the width of wiring and the diameter of connection terminals have been reduced. Correspondingly, the diameter of columnar electrodes as external connection electrodes of semiconductor devices has been reduced. Accordingly, the diameter of the solder ball is also reduced. In such a case, since the total area of soldering between the connection terminal of the circuit board and the semiconductor device is small, there is a tendency that the bonding strength of soldering is insufficient.

この対策として、半導体基板上の中央部に、半導体装置の集積回路に接続されないダミー外部端子を設け、このダミー外部端子上にダミー半田ボールを設け、このダミー半田ボールを回路基板のダミー接続端子に接合することにより半田付けの接合強度不足の解消を図ったものもある（例えば、特許文献１参照）。   As a countermeasure, a dummy external terminal that is not connected to the integrated circuit of the semiconductor device is provided at the center of the semiconductor substrate, a dummy solder ball is provided on the dummy external terminal, and the dummy solder ball is used as a dummy connection terminal of the circuit board. There is also a technique in which a lack of bonding strength of soldering is solved by bonding (for example, see Patent Document 1).

特開２００７−２８８０３８号公報JP 2007-288038 A

しかしながら、上記従来の半導体装置の実装構造では、半導体基板の中央部にダミー半田ボールを設けているので、本来の半田ボールつまり半導体装置の集積回路に接続された柱状電極の配置領域が半導体基板の中央部以外の領域に限定されてしまうという問題があった。   However, in the conventional mounting structure of the semiconductor device, since the dummy solder ball is provided in the central portion of the semiconductor substrate, the arrangement area of the columnar electrode connected to the original solder ball, that is, the integrated circuit of the semiconductor device is the semiconductor substrate. There was a problem that it was limited to the area other than the central part.

そこで、この発明は、柱状電極の配置領域に制限を受けにくいようにすることができる半導体装置およびその実装構造を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device and a mounting structure thereof that can prevent the arrangement region of the columnar electrodes from being restricted.

請求項１に記載の発明に係る半導体装置は、下面に集積回路を有する半導体基板と、前記半導体基板下の周辺部以外の領域に設けられ、それぞれ、前記集積回路に接続された複数の柱状電極と、前記半導体基板下の周辺部に設けられた複数のダミー柱状電極と、前記柱状電極および前記ダミー柱状電極の周囲に設けられた封止膜とを備え、前記ダミー柱状電極の側面は前記半導体基板および前記封止膜の側面と面一とされて外部に露出されていることを特徴とするものである。
請求項２に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記柱状電極は円柱形状であり、前記ダミー柱状電極は半円形の側面と平面状の側面とからなる外周を有する半円柱形状であり、前記ダミー柱状電極の平面状の側面が外部に露出されていることを特徴とするものである。
請求項３に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記柱状電極は前記半導体基板下の周辺部以外の領域に設けられた配線の接続パッド部下に設けられ、前記ダミー柱状電極は、前記半導体基板下の周辺部に設けられ、側面が前記半導体基板の側面と面一とされて外部に露出されたダミー接続パッド部下に設けられていることを特徴とするものである。
請求項４に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記柱状電極下に半田ボールが設けられていることを特徴とするものである。
請求項５に記載の発明に係る半導体装置は、請求項４に記載の発明において、前記ダミー柱状電極下には半田ボールが設けられていないことを特徴とするものである。
請求項６に記載の発明に係る半導体装置の実装構造は、半導体装置が回路基板上にフェースダウン方式で搭載された半導体装置の実装構造において、前記半導体装置は、下面に終戦回路を有する半導体基板と、前記半導体基板下の周辺部以外の領域に設けられ、それぞれ、前記集積回路に接続された複数の柱状電極と、前記半導体基板下の周辺部に設けられた複数のダミー柱状電極と、前記柱状電極および前記ダミー柱状電極の周囲に設けられた封止膜と、前記柱状電極下に設けられた半田ボールとを備え、前記ダミー柱状電極の側面が前記半導体基板および前記封止膜の側面と面一とされて外部に露出されたものからなり、前記回路基板は、絶縁基板と、前記絶縁基板上に設けられた複数の接続パッドと、前記接続パッドの配置領域の外側における前記絶縁基板上に設けられた複数のダミー接続パッドとを備えたものからなり、前記半導体装置は、その半田ボールが前記回路基板の接続パッドに接合され、且つ、そのダミー柱状電極が前記回路基板のダミー接続パッドに半田を介して接合されていることにより、前記回路基板上にフェースダウン方式で搭載されていることを特徴とするものである。
請求項７に記載の発明に係る半導体装置の実装構造は、請求項６に記載の発明において、前記半導体装置において、前記柱状電極は円柱形状であり、前記ダミー柱状電極は半円形の側面と平面状の側面とからなる外周を有する半円柱形状であり、前記ダミー柱状電極の平面状の側面が外部に露出されていることを特徴とするものである。
請求項８に記載の発明に係る半導体装置の実装構造は、請求項６または７に記載の発明において、前記半田は前記半導体装置のダミー柱状電極の露出された側面に傾斜状に形成されていることを特徴とするものである。
請求項９に記載の発明に係る半導体装置の実装構造は、請求項６に記載の発明において、前記半導体装置において、前記柱状電極は前記半導体基板下の周辺部以外の領域に設けられた配線の接続パッド部下に設けられ、前記ダミー柱状電極は、前記半導体基板下の周辺部に設けられ、側面が前記半導体基板の側面と面一とされて外部に露出されたダミー接続パッド部下に設けられていることを特徴とするものである。
請求項１０に記載の発明に係る半導体装置の実装構造は、請求項６に記載の発明において、前記回路基板において、前記接続パッドおよび前記ダミー接続パッドの中央部を除く前記絶縁基板上にオーバーコート膜が設けられていることを特徴とするものである。 According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having an integrated circuit on a lower surface; and a plurality of columnar electrodes provided in a region other than a peripheral portion under the semiconductor substrate, each connected to the integrated circuit And a plurality of dummy columnar electrodes provided in a peripheral portion under the semiconductor substrate, and a sealing film provided around the columnar electrode and the dummy columnar electrode, and a side surface of the dummy columnar electrode is the semiconductor The substrate and the side surface of the sealing film are flush with each other and exposed to the outside.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the columnar electrode has a cylindrical shape, and the dummy columnar electrode has an outer periphery composed of a semicircular side surface and a planar side surface. The dummy columnar electrode has a planar side surface exposed to the outside.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the columnar electrode is provided under a connection pad portion of a wiring provided in a region other than a peripheral portion under the semiconductor substrate, The dummy columnar electrode is provided in a peripheral portion under the semiconductor substrate, and a side surface of the dummy columnar electrode is provided under the dummy connection pad portion exposed to the outside with the side surface being flush with the side surface of the semiconductor substrate. is there.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein a solder ball is provided under the columnar electrode.
According to a fifth aspect of the present invention, there is provided a semiconductor device according to the fourth aspect, wherein no solder ball is provided below the dummy columnar electrode.
The semiconductor device mounting structure according to claim 6 is a semiconductor device mounting structure in which the semiconductor device is mounted on the circuit board in a face-down manner, wherein the semiconductor device has an end-of-war circuit on the lower surface. A plurality of columnar electrodes provided in a region other than the peripheral portion under the semiconductor substrate, each connected to the integrated circuit, a plurality of dummy columnar electrodes provided in the peripheral portion under the semiconductor substrate, A columnar electrode and a sealing film provided around the dummy columnar electrode; and a solder ball provided under the columnar electrode, wherein the side surface of the dummy columnar electrode is a side surface of the semiconductor substrate and the sealing film. The circuit board is formed to be flush with and exposed to the outside, and the circuit board includes an insulating substrate, a plurality of connection pads provided on the insulating substrate, and an outside of an arrangement region of the connection pads. The semiconductor device includes a plurality of dummy connection pads provided on the insulating substrate, the solder ball is bonded to the connection pad of the circuit board, and the dummy columnar electrode is the circuit. It is mounted on the circuit board in a face-down manner by being bonded to the dummy connection pads of the board via solder.
According to a seventh aspect of the present invention, in the semiconductor device mounting structure according to the sixth aspect, in the semiconductor device, the columnar electrode has a columnar shape, and the dummy columnar electrode has a semicircular side surface and a plane. It has a semi-cylindrical shape having an outer periphery formed of a side surface, and the planar side surface of the dummy columnar electrode is exposed to the outside.
According to an eighth aspect of the present invention, in the semiconductor device mounting structure according to the sixth or seventh aspect, the solder is formed in an inclined shape on the exposed side surface of the dummy columnar electrode of the semiconductor device. It is characterized by this.
A mounting structure of a semiconductor device according to a ninth aspect of the present invention is the mounting structure of the semiconductor device according to the sixth aspect, wherein the columnar electrode is a wiring provided in a region other than a peripheral portion under the semiconductor substrate. The dummy columnar electrode is provided under a connection pad portion, and the dummy columnar electrode is provided in a peripheral portion under the semiconductor substrate, and is provided under the dummy connection pad portion exposed to the outside with the side surface being flush with the side surface of the semiconductor substrate. It is characterized by being.
A mounting structure of a semiconductor device according to a tenth aspect of the present invention is the mounting structure of the semiconductor device according to the sixth aspect, wherein the circuit board is overcoated on the insulating substrate excluding a central portion of the connection pad and the dummy connection pad. A film is provided.

この発明によれば、半導体装置において、半導体基板下の周辺部にダミー柱状電極を設け、半導体基板下の周辺部以外の領域に柱状電極を設けているので、本来の柱状電極の配置領域に制限を受けにくいようにすることができる。そして、半導体装置のダミー柱状電極を回路基板のダミー接続パッドに半田を介して接合すると、実装時の接合力を高めることができる。   According to the present invention, in the semiconductor device, the dummy columnar electrode is provided in the peripheral portion under the semiconductor substrate, and the columnar electrode is provided in a region other than the peripheral portion under the semiconductor substrate. It can be made difficult to receive. When the dummy columnar electrodes of the semiconductor device are bonded to the dummy connection pads of the circuit board via solder, the bonding force at the time of mounting can be increased.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の実装構造の要部の平面図を示し、図２は図１のII−II線に沿う断面図を示す。まず、図２を参照して説明すると、半導体装置１は、一般的にはＣＳＰと呼ばれるものであり、平面長方形状のシリコン基板（半導体基板）２を備えている。シリコン基板２の一面側（図２では下面側）には所定の機能の集積回路（図示せず）が設けられ、下面周辺部にはアルミニウム系金属等からなる複数の接続パッド３が集積回路に接続されて設けられている。 (First embodiment)
FIG. 1 shows a plan view of the main part of a mounting structure of a semiconductor device as a first embodiment of the present invention, and FIG. 2 shows a cross-sectional view taken along line II-II in FIG. First, referring to FIG. 2, the semiconductor device 1 is generally called a CSP, and includes a planar rectangular silicon substrate (semiconductor substrate) 2. An integrated circuit (not shown) having a predetermined function is provided on one surface side (the lower surface side in FIG. 2) of the silicon substrate 2, and a plurality of connection pads 3 made of an aluminum-based metal or the like are provided on the integrated circuit on the periphery of the lower surface. Connected and provided.

接続パッド３の中央部を除くシリコン基板２の下面には酸化シリコン等からなる絶縁膜４が設けられ、接続パッド３の中央部は絶縁膜４に設けられた開口部５を介して露出されている。絶縁膜４の下面にはポリイミド系樹脂等からなる保護膜６が設けられている。絶縁膜４の開口部５に対応する部分における保護膜６には開口部７が設けられている。   An insulating film 4 made of silicon oxide or the like is provided on the lower surface of the silicon substrate 2 except for the central portion of the connection pad 3, and the central portion of the connection pad 3 is exposed through an opening 5 provided in the insulating film 4. Yes. A protective film 6 made of polyimide resin or the like is provided on the lower surface of the insulating film 4. An opening 7 is provided in the protective film 6 at a portion corresponding to the opening 5 of the insulating film 4.

保護膜６の下面には配線８が設けられている。配線８は、保護膜６の下面に設けられた銅等からなる下地金属層９と、下地金属層９の下面に設けられた銅からなる上部金属層１０との２層構造となっている。配線８の一端部は、絶縁膜４および保護膜６の開口部５、７を介して接続パッド３に接続されている。   A wiring 8 is provided on the lower surface of the protective film 6. The wiring 8 has a two-layer structure of a base metal layer 9 made of copper or the like provided on the lower surface of the protective film 6 and an upper metal layer 10 made of copper provided on the lower surface of the base metal layer 9. One end of the wiring 8 is connected to the connection pad 3 through the openings 5 and 7 of the insulating film 4 and the protective film 6.

ここで、図１に示すように、複数の配線８の他端部からなる円形状の接続パッド部８ａは、シリコン基板２下において左右辺部を除く領域にマトリクス状に配置されている。そして、図１および図２に示すように、保護膜６の下面の左右辺部にはそれぞれ複数の半円形状のダミー接続パッド部１１が設けられている。   Here, as shown in FIG. 1, circular connection pad portions 8 a made up of the other end portions of the plurality of wirings 8 are arranged in a matrix in a region under the silicon substrate 2 except for the left and right side portions. 1 and 2, a plurality of semicircular dummy connection pad portions 11 are provided on the left and right sides of the lower surface of the protective film 6, respectively.

図２に示すように、ダミー接続パッド部１１は、配線８と同様に、保護膜６の下面の左右辺部に設けられた銅等からなる下地金属層１２と、下地金属層１２の下面に設けられた銅からなる上部金属層１３との２層構造となっている。シリコン基板２上には、ダミー接続パッド部１１に接続される接続パッド３は形成されておらず、絶縁膜４および保護膜６にも、対応する開口部５、７は形成されていない。すなわち、ダミー接続パッド部１１は、島状に設けられ、シリコン基板１の下面側に設けられた図示しない集積回路には接続されていない。   As shown in FIG. 2, the dummy connection pad portion 11 is formed on the lower metal layer 12 made of copper or the like provided on the left and right sides of the lower surface of the protective film 6 and on the lower surface of the lower metal layer 12, similarly to the wiring 8. It has a two-layer structure with an upper metal layer 13 made of copper. On the silicon substrate 2, the connection pads 3 connected to the dummy connection pad portions 11 are not formed, and the corresponding openings 5 and 7 are not formed in the insulating film 4 and the protective film 6. That is, the dummy connection pad portion 11 is provided in an island shape and is not connected to an integrated circuit (not shown) provided on the lower surface side of the silicon substrate 1.

配線８の接続パッド部８ａの下面には銅からなる円柱形状の柱状電極１４が設けられている。この場合、図１に示すように、複数の配線８の接続パッド部８ａはシリコン基板２下において左右辺部を除く領域にマトリクス状に配置されているため、複数の柱状電極１４も同様に配置されている。ダミー接続パッド部１１の下面には銅からなる半円柱形状のダミー柱状電極１５が設けられている。半円柱形状のダミー柱状電極１５は、後述する如く、円柱状の電極を中心軸を通る面で切断したもので、半円形の側面と平面状の側面とからなる外周を有する。半円形の側面はシリコン基板２の内側に、平面状の側面はシリコン基板２の外側に向けて形成されている。   A columnar electrode 14 made of copper is provided on the lower surface of the connection pad portion 8 a of the wiring 8. In this case, as shown in FIG. 1, since the connection pad portions 8a of the plurality of wirings 8 are arranged in a matrix form in the region excluding the left and right side portions under the silicon substrate 2, the plurality of columnar electrodes 14 are similarly arranged. Has been. On the lower surface of the dummy connection pad portion 11, a semi-columnar dummy columnar electrode 15 made of copper is provided. As will be described later, the semi-columnar dummy columnar electrode 15 is obtained by cutting a columnar electrode along a plane passing through the central axis, and has an outer periphery composed of a semicircular side surface and a planar side surface. The semicircular side surface is formed on the inner side of the silicon substrate 2 and the planar side surface is formed on the outer side of the silicon substrate 2.

配線８を含む保護膜６の下面にはエポキシ系樹脂等からなる封止膜１６がその下面が柱状電極１４およびダミー柱状電極１５の下面と面一となるように設けられている。柱状電極１４の下面には半田ボール１７が設けられている。ダミー柱状電極１５の下面にはダミー半田ボールは設けられていない。   A sealing film 16 made of epoxy resin or the like is provided on the lower surface of the protective film 6 including the wiring 8 so that the lower surface is flush with the lower surfaces of the columnar electrode 14 and the dummy columnar electrode 15. A solder ball 17 is provided on the lower surface of the columnar electrode 14. Dummy solder balls are not provided on the lower surface of the dummy columnar electrode 15.

ここで、ダミー接続パッド部１１およびダミー柱状電極１５の半円形の下面および直線状の側面は、シリコン基板２、絶縁膜４、保護膜６および封止膜１６の側面と面一とされ、外部に露出されている。   Here, the semicircular lower surface and the straight side surface of the dummy connection pad portion 11 and the dummy columnar electrode 15 are flush with the side surfaces of the silicon substrate 2, the insulating film 4, the protective film 6, and the sealing film 16. Is exposed.

一方、回路基板２１は、ガラス布基材エポキシ樹脂等からなる絶縁基板２２を備えている。絶縁基板２２の上面には円形状の複数の接続パッド２３がマトリクス状に設けられている。接続パッド２３は、回路基板２１の上面に設けられた配線（図示せず）の一端部に接続されている。   On the other hand, the circuit board 21 includes an insulating substrate 22 made of glass cloth base epoxy resin or the like. A plurality of circular connection pads 23 are provided in a matrix on the upper surface of the insulating substrate 22. The connection pad 23 is connected to one end of a wiring (not shown) provided on the upper surface of the circuit board 21.

接続パッド２３の配置領域の図１の左右両側における絶縁基板２２の上面には複数のダミー接続パッド２４が設けられている。ダミー接続パッド２４は、接続パッド２３の配置領域側を半円形状とされ、その反対側を方形状とされている。ダミー接続パッド２４は、島状に設けられ、絶縁基板２２の上面においてはどことも接続されていない。   A plurality of dummy connection pads 24 are provided on the upper surface of the insulating substrate 22 on both the left and right sides in FIG. The dummy connection pad 24 has a semicircular shape on the arrangement region side of the connection pad 23 and a rectangular shape on the opposite side. The dummy connection pads 24 are provided in an island shape, and are not connected anywhere on the upper surface of the insulating substrate 22.

接続パッド２３およびダミー接続パッド２４の中央部を除く絶縁基板２２の上面にはソルダーレジスト等からなるオーバーコート膜２５が設けられ、接続パッド２３およびダミー接続パッド２４の中央部はオーバーコート膜２５に形成された開口部２６、２７を介して露出されている。この場合、開口部２６は円形状となっている。開口部２７は、接続パッド２３の配置領域側を半円形状とされ、その反対側を方形状とされている。   An overcoat film 25 made of a solder resist or the like is provided on the upper surface of the insulating substrate 22 except for the central part of the connection pad 23 and the dummy connection pad 24, and the central part of the connection pad 23 and the dummy connection pad 24 is formed on the overcoat film 25. It is exposed through the formed openings 26 and 27. In this case, the opening 26 has a circular shape. The opening 27 has a semicircular shape on the arrangement region side of the connection pad 23 and a rectangular shape on the opposite side.

そして、半導体装置１は、各半田ボール１７がそれぞれ対応する各接続パッド２３に接合され、且つ、各ダミー柱状電極１５がそれぞれ対応する各ダミー接続パッド２４に半田２８を介して接合されていることにより、回路基板２１上にフェースダウン方式で搭載されている。この場合、半田２８はダミー柱状電極１５の半円形の下面および平面状の側面に接合されている。この場合、半田２８はダミー柱状電極１５の平面状の側面においては、ダミー接続パッド２４に向かって漸次厚くなる傾斜状に形成されている。   In the semiconductor device 1, each solder ball 17 is bonded to each corresponding connection pad 23, and each dummy columnar electrode 15 is bonded to each corresponding dummy connection pad 24 via solder 28. Thus, the circuit board 21 is mounted in a face-down manner. In this case, the solder 28 is bonded to the semicircular lower surface and the planar side surface of the dummy columnar electrode 15. In this case, the solder 28 is formed on the planar side surface of the dummy columnar electrode 15 so as to be gradually inclined toward the dummy connection pad 24.

以上のように、半導体装置１において、シリコン基板２下の周辺部にダミー柱状電極１５を設け、シリコン基板２下の周辺部以外の領域に柱状電極１４を設けているので、本来の柱状電極１４の配置領域に制限を受けにくいようにすることができる。また、半導体装置１の実装構造では、半導体装置１のダミー柱状電極１５を回路基板２１のダミー接続パッド２４に半田２８を介して接合しているので、実装時の接合力を高めることができる。   As described above, in the semiconductor device 1, the dummy columnar electrode 15 is provided in the peripheral portion under the silicon substrate 2, and the columnar electrode 14 is provided in a region other than the peripheral portion under the silicon substrate 2. It is possible to make it difficult to be restricted in the arrangement area. In the mounting structure of the semiconductor device 1, since the dummy columnar electrode 15 of the semiconductor device 1 is bonded to the dummy connection pad 24 of the circuit board 21 via the solder 28, the bonding force during mounting can be increased.

また、この半導体装置の実装構造では、半導体構成体１のダミー柱状電極１５の平面状の側面が露出されているので、半導体装置１からの放熱性を良くすることができる。この場合、さらに放熱性を高めたい場合には、ダミー柱状電極１５全体に対応する面積を有するに放熱板を各ダミー柱状電極１５の平面状の側面に接触させて半田付けする構造としてもよい。放熱板は、半導体装置を外部の電磁波からシールドするためのシールドケースで兼用させてもよい。   Further, in this semiconductor device mounting structure, since the planar side surface of the dummy columnar electrode 15 of the semiconductor structure 1 is exposed, the heat dissipation from the semiconductor device 1 can be improved. In this case, if it is desired to further improve heat dissipation, a structure may be adopted in which the heat radiation plate is brought into contact with the planar side surface of each dummy columnar electrode 15 and soldered so as to have an area corresponding to the entire dummy columnar electrode 15. The heat sink may also be used as a shield case for shielding the semiconductor device from external electromagnetic waves.

次に、半導体装置１を回路基板２１上に実装する場合の一例について説明する。まず、回路基板２１のダミー接続パッド２４の上面に、スクリーン印刷法等により半田ペーストを塗布することにより、半田層を形成する。この場合、半田層の厚さは、半導体装置１の柱状電極下に形成された半田ボール１４の高さよりもある程度厚くなるようにする。   Next, an example of mounting the semiconductor device 1 on the circuit board 21 will be described. First, a solder layer is formed on the upper surface of the dummy connection pad 24 of the circuit board 21 by applying a solder paste by a screen printing method or the like. In this case, the thickness of the solder layer is set to be somewhat thicker than the height of the solder ball 14 formed under the columnar electrode of the semiconductor device 1.

次に、半田層の上面に半導体装置１のダミー柱状電極２７の部分を載置する。この状態では、半田層の厚さが半導体装置１の柱状電極下に形成された半田ボール１４の高さよりもある程度厚くなっているので、半導体装置１の柱状電極下に形成された半田ボール１４は回路基板２１のオーバーコート膜２５のやや上方に位置して浮いた状態となっている。   Next, the dummy columnar electrode 27 portion of the semiconductor device 1 is placed on the upper surface of the solder layer. In this state, since the thickness of the solder layer is somewhat thicker than the height of the solder ball 14 formed under the columnar electrode of the semiconductor device 1, the solder ball 14 formed under the columnar electrode of the semiconductor device 1 is The circuit board 21 floats in a position slightly above the overcoat film 25.

次に、リフロー処理を行なうと、半田層が溶融することにより、半導体装置１が下降し、半導体装置１の各半田ボール１７がそれぞれ対応する各接続パッド２３に接合され、且つ、半導体装置１の各ダミー柱状電極１５がそれぞれ対応する各ダミー接続パッド２４に半田２８を介して接合されることにより、半導体装置１が回路基板２１上にフェースダウン方式で搭載される。   Next, when a reflow process is performed, the solder layer melts, the semiconductor device 1 is lowered, each solder ball 17 of the semiconductor device 1 is bonded to the corresponding connection pad 23, and the semiconductor device 1 Each dummy columnar electrode 15 is bonded to each corresponding dummy connection pad 24 via solder 28, whereby the semiconductor device 1 is mounted on the circuit board 21 in a face-down manner.

（第２実施形態）
図３はこの発明の第２実施形態としての半導体装置の実装構造の要部の平面図を示す。この場合の半導体装置１において、図１に示す半導体装置１と異なる点は、シリコン基板２下において四辺部を除く領域に配線８の接続パッド部８ａおよび柱状電極１４をジグザグ状に配置し、且つ、シリコン基板２下の四辺部にそれぞれダミー接続パッド部１１およびダミー柱状電極１５を配置した点である。 (Second Embodiment)
FIG. 3 is a plan view of a main part of a semiconductor device mounting structure according to a second embodiment of the present invention. The semiconductor device 1 in this case is different from the semiconductor device 1 shown in FIG. 1 in that the connection pad portions 8a and the columnar electrodes 14 of the wiring 8 are arranged in a zigzag shape in the region excluding the four sides under the silicon substrate 2. The dummy connection pad portion 11 and the dummy columnar electrode 15 are arranged on the four sides below the silicon substrate 2, respectively.

そして、半導体装置１は、図２に示す場合と同様に、各半田ボール１７がそれぞれ対応する各接続パッド２３に接合され、且つ、各ダミー柱状電極１５がそれぞれ対応する各ダミー接続パッド２４に半田２８を介して接合されていることにより、回路基板２１上にフェースダウン方式で搭載されている。   In the semiconductor device 1, as in the case shown in FIG. 2, each solder ball 17 is bonded to each corresponding connection pad 23, and each dummy columnar electrode 15 is soldered to each corresponding dummy connection pad 24. By being joined via 28, it is mounted on the circuit board 21 in a face-down manner.

なお、上記実施形態においては、ダミー柱状電極１５は、平面状の側面を外部に露出する場合で説明したが、ダミー状柱状電極１５を平面形状が方形のシリコン基板２の角部に設けてもよく、この場合は、ダミー柱状電極１５は、９０度の円弧状の側面と、相互に直交する方向に配置された二つの平面状の側面とからなる外周を有する円弧状柱状電極として形成され、その円弧状柱状電極の二つの平面状の側面は、それぞれ、シリコン基板２の当該角部に隣接する二辺と面一となるように形成される。   In the above embodiment, the dummy columnar electrode 15 has been described in the case where the planar side surface is exposed to the outside, but the dummy columnar electrode 15 may be provided at the corner of the silicon substrate 2 having a square planar shape. Well, in this case, the dummy columnar electrode 15 is formed as an arcuate columnar electrode having an outer periphery composed of a 90-degree arcuate side surface and two planar side surfaces arranged in directions orthogonal to each other, The two planar side surfaces of the arc-shaped columnar electrode are formed so as to be flush with the two sides adjacent to the corner of the silicon substrate 2.

この発明の第１実施形態としての半導体装置の実装構造の要部の平面図。The top view of the principal part of the mounting structure of the semiconductor device as 1st Embodiment of this invention. 図１のII−II線に沿う断面図。Sectional drawing which follows the II-II line | wire of FIG. この発明の第２実施形態としての半導体装置の実装構造の要部の平面図。The top view of the principal part of the mounting structure of the semiconductor device as 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１ 半導体装置
２ シリコン基板
３ 接続パッド
４ 絶縁膜
６ 保護膜
８ 配線
８ａ 接続パッド部
１１ ダミー接続パッド部
１４ 柱状電極
１５ ダミー柱状電極
１６ 封止膜
１７ 半田ボール
２１ 回路基板
２２ 絶縁基板
２３ 接続パッド
２４ ダミー接続パッド
２５ オーバーコート膜
２８ 半田 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Silicon substrate 3 Connection pad 4 Insulating film 6 Protective film 8 Wiring 8a Connection pad part 11 Dummy connection pad part 14 Columnar electrode 15 Dummy columnar electrode 16 Sealing film 17 Solder ball 21 Circuit board 22 Insulating substrate 23 Connection pad 24 Dummy connection pad 25 Overcoat film 28 Solder

Claims (10)

下面に集積回路を有する半導体基板と、前記半導体基板下の周辺部以外の領域に設けられ、それぞれ、前記集積回路に接続された複数の柱状電極と、前記半導体基板下の周辺部に設けられた複数のダミー柱状電極と、前記柱状電極および前記ダミー柱状電極の周囲に設けられた封止膜とを備え、前記ダミー柱状電極の側面は前記半導体基板および前記封止膜の側面と面一とされて外部に露出されていることを特徴とする半導体装置。   Provided in a region other than the semiconductor substrate having an integrated circuit on the lower surface and the peripheral portion under the semiconductor substrate, respectively, provided with a plurality of columnar electrodes connected to the integrated circuit, and in the peripheral portion under the semiconductor substrate A plurality of dummy columnar electrodes; and the columnar electrodes and a sealing film provided around the dummy columnar electrodes, and the side surfaces of the dummy columnar electrodes are flush with the side surfaces of the semiconductor substrate and the sealing film. The semiconductor device is exposed to the outside. 請求項１に記載の発明において、前記柱状電極は円柱形状であり、前記ダミー柱状電極は半円形の側面と平面状の側面とからなる外周を有する半円柱形状であり、前記ダミー柱状電極の平面状の側面が外部に露出されていることを特徴とする半導体装置。   The invention according to claim 1, wherein the columnar electrode has a cylindrical shape, the dummy columnar electrode has a semicircular column shape having an outer periphery composed of a semicircular side surface and a planar side surface, and is a plane of the dummy columnar electrode. A semiconductor device characterized in that a side surface of the shape is exposed to the outside. 請求項１に記載の発明において、前記柱状電極は前記半導体基板下の周辺部以外の領域に設けられた配線の接続パッド部下に設けられ、前記ダミー柱状電極は、前記半導体基板下の周辺部に設けられ、側面が前記半導体基板の側面と面一とされて外部に露出されたダミー接続パッド部下に設けられていることを特徴とする半導体装置。   The columnar electrode is provided under a connection pad portion of a wiring provided in a region other than the peripheral portion under the semiconductor substrate, and the dummy columnar electrode is provided in a peripheral portion under the semiconductor substrate. A semiconductor device, wherein the semiconductor device is provided under a dummy connection pad portion, the side surface of which is flush with the side surface of the semiconductor substrate and exposed to the outside. 請求項１に記載の発明において、前記柱状電極下に半田ボールが設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a solder ball is provided under the columnar electrode. 請求項４に記載の発明において、前記ダミー柱状電極下には半田ボールが設けられていないことを特徴とする半導体装置。   5. The semiconductor device according to claim 4, wherein no solder ball is provided under the dummy columnar electrode. 半導体装置が回路基板上にフェースダウン方式で搭載された半導体装置の実装構造において、
前記半導体装置は、下面に終戦回路を有する半導体基板と、前記半導体基板下の周辺部以外の領域に設けられ、それぞれ、前記集積回路に接続された複数の柱状電極と、前記半導体基板下の周辺部に設けられた複数のダミー柱状電極と、前記柱状電極および前記ダミー柱状電極の周囲に設けられた封止膜と、前記柱状電極下に設けられた半田ボールとを備え、前記ダミー柱状電極の側面が前記半導体基板および前記封止膜の側面と面一とされて外部に露出されたものからなり、
前記回路基板は、絶縁基板と、前記絶縁基板上に設けられた複数の接続パッドと、前記接続パッドの配置領域の外側における前記絶縁基板上に設けられた複数のダミー接続パッドとを備えたものからなり、
前記半導体装置は、その半田ボールが前記回路基板の接続パッドに接合され、且つ、そのダミー柱状電極が前記回路基板のダミー接続パッドに半田を介して接合されていることにより、前記回路基板上にフェースダウン方式で搭載されていることを特徴とする半導体装置の実装構造。 In a semiconductor device mounting structure in which a semiconductor device is mounted on a circuit board in a face-down manner,
The semiconductor device includes a semiconductor substrate having a warfare circuit on a lower surface, a plurality of columnar electrodes provided in a region other than a peripheral portion under the semiconductor substrate, each connected to the integrated circuit, and a peripheral under the semiconductor substrate. A plurality of dummy columnar electrodes provided in a portion, a sealing film provided around the columnar electrode and the dummy columnar electrode, and a solder ball provided under the columnar electrode, The side surface is the same as the side surface of the semiconductor substrate and the sealing film and is exposed to the outside,
The circuit board includes an insulating substrate, a plurality of connection pads provided on the insulating substrate, and a plurality of dummy connection pads provided on the insulating substrate outside the arrangement area of the connection pads. Consists of
In the semiconductor device, the solder balls are bonded to the connection pads of the circuit board, and the dummy columnar electrodes are bonded to the dummy connection pads of the circuit board via solder, so that A mounting structure of a semiconductor device, which is mounted in a face-down manner. 請求項６に記載の発明において、前記半導体装置において、前記柱状電極は円柱形状であり、前記ダミー柱状電極は半円形の側面と平面状の側面とからなる外周を有する半円柱形状であり、前記ダミー柱状電極の平面状の側面が外部に露出されていることを特徴とする半導体装置の実装構造。   7. The semiconductor device according to claim 6, wherein in the semiconductor device, the columnar electrode has a columnar shape, and the dummy columnar electrode has a semicircular column shape having an outer periphery composed of a semicircular side surface and a planar side surface, A mounting structure of a semiconductor device, wherein a planar side surface of a dummy columnar electrode is exposed to the outside. 請求項６または７に記載の発明において、前記半田は前記半導体装置のダミー柱状電極の露出された側面に傾斜状に形成されていることを特徴とする半導体装置の実装構造。   8. The semiconductor device mounting structure according to claim 6, wherein the solder is formed in an inclined shape on the exposed side surface of the dummy columnar electrode of the semiconductor device. 請求項６に記載の発明において、前記半導体装置において、前記柱状電極は前記半導体基板下の周辺部以外の領域に設けられた配線の接続パッド部下に設けられ、前記ダミー柱状電極は、前記半導体基板下の周辺部に設けられ、側面が前記半導体基板の側面と面一とされて外部に露出されたダミー接続パッド部下に設けられていることを特徴とする半導体装置の実装構造。   7. The semiconductor device according to claim 6, wherein in the semiconductor device, the columnar electrode is provided under a connection pad portion of a wiring provided in a region other than a peripheral portion under the semiconductor substrate, and the dummy columnar electrode is provided in the semiconductor substrate. A semiconductor device mounting structure, wherein the semiconductor device mounting structure is provided under a dummy connection pad portion provided in a lower peripheral portion and having a side surface flush with a side surface of the semiconductor substrate and exposed to the outside. 請求項６に記載の発明において、前記回路基板において、前記接続パッドおよび前記ダミー接続パッドの中央部を除く前記絶縁基板上にオーバーコート膜が設けられていることを特徴とする半導体装置の実装構造。   7. The semiconductor device mounting structure according to claim 6, wherein an overcoat film is provided on the insulating substrate except for a central portion of the connection pad and the dummy connection pad in the circuit board. .
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US20140185248A1 (en) * 2011-09-09 2014-07-03 Murata Manufacturing Co., Ltd. Module board

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JP2001053399A (en) * 1999-08-11 2001-02-23 Toyo Commun Equip Co Ltd Surface mounted unit
JP2005347361A (en) * 2004-06-01 2005-12-15 Casio Comput Co Ltd Mounting structure of semiconductor device
JP2008172060A (en) * 2007-01-12 2008-07-24 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method

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JP2001053399A (en) * 1999-08-11 2001-02-23 Toyo Commun Equip Co Ltd Surface mounted unit
JP2005347361A (en) * 2004-06-01 2005-12-15 Casio Comput Co Ltd Mounting structure of semiconductor device
JP2008172060A (en) * 2007-01-12 2008-07-24 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140185248A1 (en) * 2011-09-09 2014-07-03 Murata Manufacturing Co., Ltd. Module board
US9591747B2 (en) * 2011-09-09 2017-03-07 Murata Manufacturing Co., Ltd. Module board

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