JP2009266050A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cope with the problem of sharing a device driver which is software for controlling devices without changing nor deteriorating execution performance, in a multi-core environment in which generally, a plurality of concurrently-operating CPUs each of which is under a different OS from one another, while the number of devices such as I/O devices and accelerator IPs is restricted, and the devices are required to be shared among the plurality of CPUs or OSs. <P>SOLUTION: In order to solve the problem, a virtual machine control mechanism (VMM) assigns access to the devices from the plurality of OSs and gives an image occupying the devices to the OSs. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a system configured by software that operates on the apparatus.

  With the progress of integration in microprocessors, microprocessors equipped with a plurality of central processing units (CPUs) have been developed as multi-core systems. When an application program is operated on a microprocessor equipped with a plurality of CPUs, there are a plurality of operating systems (OS) as a basic system, data exchange between these OSs, and functions on different OSs. It is necessary to have a method for executing the process without being aware of the existence of a plurality of CPUs and OSs. In such a situation, as a system for controlling the execution of the OS and application on the multiprocessor system as described above, for example, as disclosed in Patent Document 1, an OS for a single processor and an existing one are used on the multiprocessor. There is a conventional technique that allows an application to operate and realize parallel processing. Such a mechanism for freely linking system configuration resources such as a physical CPU and an OS or application is called virtualization, and has been widely used in the field of servers and the like. A mechanism for realizing and managing virtualization in cooperation with the OS is called a virtual machine control mechanism (VMM). As a method for virtualizing input / output (hereinafter referred to as “I / O”) and sharing a plurality of OSs with input / output devices, there is, for example, a conventional technique disclosed in Patent Document 2.

  Further, as shown in Non-Patent Document 1 and Non-Patent Document 2, there are three types of methods for virtualizing I / O: a device emulation method, a virtual device driver method, and a direct I / O method. To do. The device emulation method is a method of simulating the hardware of an I / O device by software, and emulates the operation by transferring control to the VMM whenever the guest OS CPU accesses the device control register. is there. In this method, it is necessary to transfer control to the VMM every time the control register is accessed, and the execution overhead is large in principle.

  The virtual device method is a method in which an abstract virtual device is defined and a dedicated device driver (virtual driver) is installed and used in the guest OS. Here, the actual I / O device is occupied by the management OS, and the virtual driver accesses from the management OS via the VMM.

  The direct I / O method is a method in which an I / O device is directly accessed from a guest OS, and the guest OS controls a physical device using almost the same device driver as a normal device driver. This method can provide the same performance as when a single OS occupies the I / O device, but in general, a device cannot be shared among a plurality of guest OSes. As shown in Non-Patent Document 3, there is a method in which a physical device is provided with a shared function by having a plurality of register sets on the physical device side.

JP 2003-345614 A JP 2003-202999 A The whole picture of Intel Virtualization Technology 2nd Nikkei IT Pro November 2006 PRIMEQUEST Virtual Machine Function White Paper Fujitsu Limited April 2007 Nikkei Bytes November 2005, pages 28-33

  In a multi-core system in which a large number of CPUs and IPs are integrated on a single chip, complicated functions are related to each other and operate at the same time. Therefore, one physical device is operated by a plurality of cores and an OS that operates on these cores. Share situations occur. In this sharing, the OS that is the main subject of sharing does not mean that only one OS is active at a time, and that each is always active and operates in parallel. Is the situation of using. In such a case, since there is one control register group for controlling the real device, access to them is arbitrated in some form, and one set of control register group is virtually shown as a plurality of OSs. Need to handle access from.

  As described above, in a multi-core environment, it is common that a plurality of CPUs operate simultaneously, and each of them is under a different OS. On the other hand, the number of devices such as I / O devices and accelerator IPs is limited, and there is a demand to share these multiple CPUs and OSs. For example, in a car navigation system equipped with a hard disk, one hard disk device is used for storing map data and music data, and they are used for path search and music playback that operate on separate processors. Sometimes you want to access them at the same time.

  In order to realize this request, in the above-described device emulation method and virtual device method, an OS that manages one physical device is placed as a management OS and is left to that. In this method, device allocation and the like can be performed simply, but it is necessary to increase the processing in the virtual machine control mechanism (VMM) layer, or to change the device driver in the guest OS other than the management OS. . In addition, the processing performance may be deteriorated because it passes through the management OS.

  If the direct I / O method is used, such an overhead does not occur, but at present, it is required to implement a shared hardware mechanism such as having a plurality of control register sets on the I / O device side.

  In order to solve the above problems, in the present invention, a first central processing unit that executes a first operating system, a second central processing unit that executes a second operating system, and the first and second A memory that is designated and accessed by a central processing unit; and an input / output device that is designated and accessed by the first and second central processing units. If the first central processing unit outputs an address designating the input / output device when assigned to one operating system, the input / output is performed without converting the address designating the input / output device. When accessing the device and the second central processing unit outputs an address designating the input / output device, an address designating the input / output device is designated. Converts the scan into the address corresponding to the virtual device area provided in the memory, it stores the data in which the second central processing unit is output to the virtual device region.

  Alternatively, a plurality of central processing units that execute a plurality of operating systems, a memory that is designated and accessed by the plurality of central processing units, and a control register that is designated and accessed by the plurality of central processing units And an input / output device having an address conversion mechanism for converting addresses output from the plurality of central processing units according to a predetermined condition, wherein the control register and the memory are included in one address space, A plurality of virtual device areas corresponding to each of the plurality of operating systems, and the address conversion mechanism is a central processing unit that executes an operating system to which the input / output device is allocated among the plurality of operating systems. Outputs an address specifying the control register When the address specifying the control register is output from a central processing unit that executes an operating system to which the input / output device is not assigned among the plurality of operating systems without performing address conversion, the plurality of virtual Convert the corresponding one of the device areas to the specified address.

  According to the invention disclosed in the present application, the time required for software development can be shortened in a multi-core environment, and the efficiency of input / output processing can be improved.

  In the main invention disclosed in this specification, a plurality of central processing units (CPUs) share a single memory in a single chip, and a plurality of operating systems (OS) are installed on each of the plurality of CPUs. This is a technique related to an I / O sharing method in the execution of an application program in an environment that operates while sharing an output device (I / O). The outline of the main invention disclosed in this specification will be described first. When a plurality of OSs are operating in the active state at the same time and share one device and access them simultaneously, By assigning the access from the OS and giving each OS an image that occupies the I / O device, the input / output operations can be performed in parallel. In this case, a virtual machine control mechanism (VMM) may distribute access to the device from the plurality of OSs. As a result, the I / O device driver provided by each OS can be used without change, and the shared I / O device does not require a special mechanism, and the conventional one can be used as it is. . Furthermore, the virtual machine control mechanism (VMM) does not need to intervene every time the control register is accessed, and the processing overhead can be reduced.

In other words, access to the device from the plurality of OSs is distributed, and an image occupying the device is given to each OS by the following method.
(1) When a single device is shared by a plurality of OSs, the physical address translation mechanism (PAM) is used to switch the MMIO (memory-mapped IO) register area address required for each OS. Switch instances to distribute. Here, the actual control register area is called a real device area, and the area allocated for switching is called a virtual device area. From the device driver on the OS side, the real device area can be accessed if the device has the control right and the device is assigned, and the virtual device area is accessed if the device is not assigned. Also, device allocation exclusivity is guaranteed using a physical address translation mechanism.
(2) A virtual device area is provided for each OS sharing a device.
(3) Information on whether or not the data is for writing in the virtual device area, the order of writing, time restrictions on accessing related elements, and whether or not the data has been written to the data for writing Information.
(4) The VMM has a device scheduler, and this scheduler schedules shared devices based on device operation end notifications and time intervals, and sequentially assigns them to a plurality of shared OSs.
(5) The real device area and the virtual device area are copied by the VMM by switching the device assignment by the device scheduler. At this time, the write data is copied from the virtual device area to the real device area only when it is written again from the previous write, and written to the real device area in accordance with the write order.

  The details of the method for sharing an I / O device in a plurality of OSs according to the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a software and hardware configuration in the present invention. The target multi-core system includes a single memory MEM (100), a plurality of CPUs (101 to 103) of CPU1 to CPU3, and input / output devices (104, 105) of IO1 to IO2. Further, the OS is operated as OS1, OS2, OS3 (151 to 153) on each CPU, and the applications (APPL) 1, 2, 3 (161 to 163) are operated thereon. 110 is a control program at a lower level than the OS called a virtual machine control mechanism (VMM) 110, and links resources such as CPU and memory I / O with the OS. This has a resource division / distribution function (RDD) 120. Further, a memory is accessed from the CPU via a memory transfer path (MEMTS) 130, and a physical address management mechanism (PAM) 140 that converts an access address in this memory access is provided. Here, the applications 161 to 163, the OS1 to OS3 (151 to 153), and the VMM (including the resource division / distribution function 120) 110 are configured by software, and the others are configured by hardware. These software are stored in the memory MEM (100).

  The resource division / distribution function 120 cooperates with the physical address management mechanism PAM (140) by hardware to set the memory address used by the application or OS to refer to the memory, and sets and operates an entry in the PAM. By adding an appropriate offset to the address value, the physical arrangement of the reference location on the actual memory 100 can be shifted without being conscious of the application or OS, and the memory is divided into an area for the CPU 1, It is distributed as an area for the CPU2.

  On the other hand, regarding the use of I / O devices, the input / output device has a control register (not shown) for operating its function, and these control registers are used as memory addresses as memory mapped IO (MMIO). The address is mapped. Therefore, the CPU accesses the I / O device by outputting the memory address as if it were a memory. Specifically, the I / O device is access-controlled by an input / output management program called a device driver installed in the OS. Generally, direct operations on I / O devices are performed only by device drivers for the I / O devices. Examples of such MMIO devices include a hard disk device.

  Here, for example, when the I / O device (IO1) is shared by OS1 and OS2, the real device area mapped as the control register of IO1 is shared by both OS1 and OS2. For this reason, the VMM is required to realize the input / output function while handing over the control of the real device area to the OS1 and OS2 in a time division manner.

  Details of the components shown in FIG. 1 in an example in which the OS 1 and OS 2 share and execute the input / output device IO 1 will be described with reference to FIG. The device drivers DRV1 and DRV2 included in the OS1 and OS2 are programs that perform physical control on the respective devices. Further, the VMM has a shared device scheduler (CDC) 250 in addition to the resource dividing / distributing mechanism 120 shown in FIG. 1, and also has region control information (RCI) 260 in the shared device scheduler. The shared device scheduler 250 arbitrates usage rights for devices shared by a plurality of OSs, and the area control information 260 is an attribute of how information stored in the area control register is used. Is shown. Furthermore, in this figure, an address space for CPU 1 and CPU 2 to access is shown. The address space includes a memory area to which the memory 100 is mapped and a real device area to which a memory mapped IO (MMIO) control register is mapped. In the memory area to which the memory 100 is mapped, a virtual device area 1 (221) for OS1 (CPU1) and a virtual device area 2 (222) for OS2 (CPU2) are provided. Also, areas 271 and 272 indicating flags indicating whether or not the accessed IO is in use are provided in each virtual device area. A write monitoring mechanism WOS (281, 282) is provided corresponding to each virtual device region 221, 222. The write monitoring mechanism monitors whether a write operation has been performed on each virtual device area.

  Assume that OS1 has control over IO1 and is accessing it. At this time, an entry of PAM (140) is set by the VMM (110), and device access from the OS1 to the IO1 is made to the real device area 1 (220) to which the control register of the IO1 is mapped. It has become. That is, an address (231) for accessing the control register of IO1 is output from the device driver DRV1 (230) in the OS1, and the address (231) is real by the PAM (140) as indicated by a solid arrow 232. The device is mapped to the device area 1 (220), and the device functions according to the address. On the other hand, if there is an access from the OS 2 that does not have control over the device to the IO 1, the device driver DRV 2 (240) in the OS 2 refers to the control register of the IO 1. This access is performed by the PAM (140). Thus, the address (241) is converted to have a predetermined offset (offset 2), and is converted into an access to the memory 100 which is the virtual device area 2 (222) for the OS2 of the IO1 as a dotted arrow 242. The contents of access to the virtual device area made during a period when there is no control right are reflected in the real device the next time control right is obtained.

  FIG. 3 explains the process of address conversion by the PAM (140). The PAM has a plurality of entries 370 corresponding to each OS (CPU). Each entry 370 stores a lower limit address 310 and an upper limit address 320 for specifying the address range of the memory to which the control register of the I / O device is mapped, and I / O belonging to the address range. When accessing the device, the offset value 330 to be added to the addressing signal 350 output by the device driver is stored. In the PAM, with respect to the value of the input address designation signal (350), the OS designation signal (340) is used to obtain which OS or CPU has output it, and the PAM entry (to be used for address translation) ( 370). The address designation signal (350) output from the OS by the device driver is input to the comparator COMP (360), and the entry 370 is selected by comparing with the upper and lower limit values (310, 320) of the address range. Is given an offset value (330) to be applied, and these are added to output a true access address (380). With this hardware mechanism, it is possible to distribute and arbitrate access to the control register of the MMIO device output from a plurality of CPUs / OSs.

  When the OS1 has control over the target I / O device (IO1), as described with reference to FIG. 2, the access to the I / O device (IO1) from the OS1 by the setting of the PAM, that is, control of this device The access to the register is mapped as to the corresponding real device area (220), and the control register access from the device driver is treated as the same as the normal device operation. On the other hand, an access to the device from OS2 that does not have control over this device (IO1) is mapped as to the virtual device region 2 (222) by adding an offset value according to the setting of the PAM. Memory access.

  Hereinafter, FIG. 4, FIG. 3 and FIG. 2 show a processing procedure for arbitrating access to an I / O from a plurality of OSs by setting a PAM entry, that is, access to an actual device area for the device. As an example, a case where the control right of a device is changed from OS1 to OS2 will be described.

  Before the control right of the I / O device IO1 is changed from OS1 to OS2, since the OS1 has the control right of the IO1, the content of the offset value (330) with respect to the address of the control register of the IO1 is 0. The device control access address 231 output from the device driver is output as is as the access address (380). Next, the start of the device switch, that is, the change of the control right is performed by changing the setting of the entry contents of the PAM. Specifically, first, in order to cancel the allocation of the OS1 control right, the PAM entry corresponding to OS1 in the real device area (220) is changed to point to the virtual device area 1 (221) for IO1. (410). When changing the control right, the VMM (110) sets this offset value as the offset 1 (261) in FIG. 2, and is mapped to the virtual device area 1 (221) for OS1 as indicated by the dotted arrow 233. So that The virtual device area 1 and the virtual device area 2 in the figure are secured in the memory as 221 and 222 in FIG. Such area reservation and offset value specification are performed at the time of system initialization.

  Next, in order to copy the contents of the real device area (220) to the virtual device area to 1 (221), the device in-use flag (271) of the virtual device area 1 (221) is set to ON, and this is set from OS1. Wait for access to the device (420). Next, the contents of the control register are copied from the real device area (220) to the virtual device area 1 for the OS1 whose device allocation is to be released, and the same contents as the contents of the real device area (220) are copied to the virtual device area 1. (221) is held (430). The device busy flag (271) in the virtual device area 1 is turned OFF (440). Thus, the OS 1 can read the control register information from the virtual device area 1 even when there is no I / O device control right. Here, the device busy flag is a flag indicating whether or not the device is currently operating and is provided in the actual device, and is present in the actual device area as a part (270) of the control register. To do. In the present invention, copies of the areas are held as 271 and 272 in the virtual device area 1 and the virtual device area 2, respectively. As will be described later, control is performed with reference to this copy area from the OS having no control right.

  Next, the OS 2 that obtains the control right from now on can access the real device area. For this purpose, as shown in FIGS. 4 and 470, the entry whose offset value is offset 2 (262) in the current PAM is set to 0, and the control register area of the I / O device from OS2 is set to 0. The address for access is set to the real device area (220). By this operation, the direct access right to the device is transferred from the OS 1 to the OS 2, the OS 1 becomes the virtual device area 1, and the OS 2 becomes the real device area and can access the actual device. Here, the area that can be accessed from the OS 1 is first mapped from the real device area to the virtual device area, and then the area that can be accessed from the OS 2 is mapped to the real device area in this order by a single VMM. Therefore, a situation in which the same real device area is accessed from a plurality of OSs to the I / O device does not occur, and exclusive control of the device is performed here.

  Furthermore, the result of virtual access to the I / O device that has been performed by the OS 2 so far is reflected on the actual device. It is necessary to reflect the operation for the device written in the virtual device area 2 when there is no control right to the real device. For this reason, the contents of the virtual device area are written to the real device at the timing when the control right moves. 4 and 460, this corresponds to copying from the virtual device area 2 of the OS 2 having control over the current device to the real device area. Prior to this copy operation, in 450, the device busy flag (272) in the virtual device area 2 (222) is set to ON so that the OS 2 can wait for access to the device.

  In the above, (1) address, (2) size, (3) whether or not writing is performed for each piece of data in the virtual device area as management information in the VMM, (4) writing order, (5) It has area control information (260) such as a time restriction of writing related data. Further, for the write data, a write monitoring mechanism (281, 282) is provided for monitoring whether or not the data has changed from the previous write for each virtual device area.

  In the 460 copy operation, first, data that becomes a command for an operation that does not change the state, that is, only the read operation such as the device state, is written in the actual device area. Next, with respect to data to be changed, that is, data serving as a command for an operation for changing the state of the device, data that has changed from the previous writing is written. The order of writing is performed based on the writing order information in the area control information (250). If there is a time restriction between the writing data, the writing is performed in compliance with the time restriction. Further, the data to be written is limited to the case where the data is written in the virtual device area when there is no control right, and whether or not the data has been written is determined by the write monitoring mechanism (FIGS. 2, 281 and 282). In an actual operation, as an example, a method of initializing data to be written to a special value that is not set as an IO operation, and monitoring whether or not the writing has been performed depending on whether the value has changed Etc. are taken.

  A copy operation from the virtual device area 610 to the real device area 620 will be described with reference to FIG. State change no data 1 (611), state change no data 2 (612), and no state change data 3 (613), which are data serving as commands for operations that do not cause a state change, are stored in the actual device area 620 by 630, respectively. It is written so as to be copied to the corresponding areas of no-change data 1 (621), no-change data 2 (622), and no-change data 3 (623). Since the data to be a command for the operation to change the state is the state change data 1 (614) is written in the write monitoring mechanism (616), the state change data 1 (624) in the actual device area 620 Is copied by 630. Since the data 2 with status change (615) is not written (617) in the write monitoring mechanism, it is not copied to the actual device area 620. If 617 is written, the data with status change 2 (615) is copied after copying the data with status change 1 (614) according to the order indicated by the write order (618, 619).

  Here, the data used as the command for the operation to change the state causes the actual physical device to generate an operation, and causes the change of the state. It can only be issued once, and the order in which they are generated must be maintained. For this reason, write monitoring is performed and the order of writing is maintained. When the same kind of write operation is performed, the end report for this operation is not made, and the subsequent write operation is put on hold.

  As a result of the above operations, the operations that have been performed on devices that have not been controlled so far are reflected in the actual device when control is obtained. The device driver functions by operating the registers. Finally, the device busy flag in the virtual device area is turned OFF (480).

  The scheduling process for the shared device allocation is as shown in FIG. This is a shared device scheduler (FIG. 2, 250) that schedules the right to use only one physical I / O device and schedules it to be assigned to multiple active OSs in order. It is an example of a processing algorithm.

  The shared device scheduler is normally in an idle state (500) in which no allocation process is performed, and checks the state of the input / output device (IO1 in this example) to be shared at regular intervals by a timer interrupt or the like. This check is performed, for example, by referring to the “in-use flag” (FIG. 2, 270) installed in the device itself. During this process, the VMM (FIG. 2, 200) performs this control, so that the shared device scheduler itself can access the real device area.

  When the processing of the IO progresses and an end interrupt is generated from the device (510), such an interrupt is once captured by the VMM, and interrupt processing is started. In 520, the cause of the interrupt is determined, and in the case of a device end interrupt (521), since the processing in the device has ended, control is transferred to another OS (next in the order assumed by the scheduler). (530) The end interrupt itself is sent as it is to the OS (OS1) that has been in control of the device so far (540).

  On the other hand, if it is a timer interrupt (522), it is checked whether the device is in use with reference to the busy flag (FIG. 2, 270) (550). When the in-use flag is ON and the device is in use, the scheduler does nothing and the access right to the device remains set in the OS (551). When the in-use flag is OFF and the device is not in use (552), the control right is handed over to another OS in the same manner as in 530 (560). Here, the selection of another OS to which control is given is not limited to the method of sequentially assigning to the next one as shown in this example. There is a method of setting a priority for the OS and giving it to the OS having the highest priority at that time based on the priority. If the interrupt factor is other (523), the interrupt is sent to the OS to receive and process.

  As described above, in the present invention, in order to share and access one device from a plurality of OSs operating simultaneously in a multi-core system, the device driver provided in the OS is not changed, and the device driver is not changed. It can be realized by operating. Moreover, flexible access can be made possible without worrying about the influence of access to the device from other OSs operating simultaneously, and control arbitration is performed using PAM, which is hardware. Therefore, it is possible to prevent the execution performance from deteriorating because the VMM intervenes.

The figure which showed the whole system structure outline | summary. The figure which showed the detailed system configuration. The figure which showed the physical address management mechanism (PAM). The figure which showed the flow of the device allocation switching process. The figure which showed copy operation from a virtual device area to a real device area. The figure which showed the flow of the device scheduling process.

Explanation of symbols

  100: Memory, 101, 102, 103: CPU, 104, 105: Input / output device, 110: Virtual machine control mechanism (VMM), 120: Resource division / distribution mechanism, 130: Memory transfer path, 140: Physical address management mechanism (PAM), 151, 152, 153: operating system, 161, 162, 163: application, 220: real device area, 221, 222: virtual device area, 230, 240: device driver, 231, 232, 233, 241, 242: Control register access address, 250: Shared device scheduler, 260: Area control information, 261, 262: Offset value, 270, 271, 272: In-use flag, 281, 282: Write monitoring mechanism, 310: Lower limit address entry, 320: Upper limit address , 330: Offset value, 340: OS designation signal, 350: Address designation signal, 360: Comparator, 370: PAM entry, 380: True access address, 410: Release side PAM setting process, 420/440: Release -Side device busy flag setting processing, 430: release-side copy processing, 450 and 480: assignment-side device busy flag setting processing, 460: assignment-side copy processing, 470: assignment-side PAM setting processing, 500: idle state, 510: Interrupt generation, 520: Analysis processing for interrupt factor, 521, 522, 523: Distinguish between interrupt factors, 530, 560: Transfer processing of control to next OS, 540, 570: Transfer processing of interrupt, 550: Device In-use inspection, 551 and 552: In-use inspection result, 610: Virtual device area 611, 612, 613, 614, 615: control data to be commands, 616, 617: write monitoring mechanism, 618, 619: write order, 620: actual device area, 621, 622, 623, 624, 625: command Control data.

Claims (13)

A first central processing unit executing a first operating system;
A second central processing unit executing a second operating system;
A memory whose address is designated and accessed from the first and second central processing units;
An input / output device that is designated and accessed by the first and second central processing units;
When access to the input / output device is assigned to the first operating system,
When the first central processing unit outputs an address designating the input / output device, it accesses the input / output device without converting the address designating the input / output device,
When the second central processing unit outputs an address designating the input / output device, the address designating the input / output device is converted into an address corresponding to a virtual device area provided in the memory, An information processing apparatus, wherein data output from a second central processing unit is stored in the virtual device area. In claim 1,
The information processing apparatus further includes an allocation scheduler for changing an operating system to which access is allocated to the input / output device when a predetermined time elapses or a notification of termination of the input / output device has elapsed. Processing equipment. In claim 2,
The input / output device is designated by an address that designates the input / output device, and has a control register in which data as a command is written,
The information processing apparatus further comprises an address conversion mechanism for converting an address designating the control register output from the central processing unit. In claim 3,
The information processing apparatus, wherein the memory has virtual device areas corresponding to the first operating system and the second operating system, respectively. In claim 2,
The allocation scheduler has information on whether or not the data in the virtual device area is information for writing, information on the order of writing, and information on a time interval for writing between related elements. Processing equipment.   6. The allocation switching by the allocation scheduler according to claim 5, wherein a virtual device area corresponding to an operating system whose allocation has been canceled is transferred from the input / output device to a virtual device area corresponding to a newly allocated operating system and a virtual device area corresponding to a newly allocated operating system. An information processing apparatus for copying data to an entry / output apparatus. In claim 6,
The information processing apparatus further includes a write monitoring mechanism that monitors whether data has changed from a previous write for the virtual device area,
In the allocation switching by the allocation scheduler, when copying data from the virtual device area to the input / output device, the information processing device refers to the information of the write monitoring mechanism and is rewritten from the previous writing. An information processing apparatus that writes data to the input / output device according to a writing order only when the data is written. In claim 7,
The write monitoring mechanism uses a value that is not used as data to be written in the virtual device area, and determines whether the data has changed from a previous write depending on whether the data has been changed. Processing equipment. Multiple central processing units running multiple operating systems;
A memory that is addressed and accessed from the plurality of central processing units;
An input / output device having a control register whose address is designated and accessed from the plurality of central processing units;
An address conversion mechanism for converting addresses output by the plurality of central processing units according to a predetermined condition;
The control register and the memory are included in one address space,
The memory has a plurality of virtual device areas corresponding to the plurality of operating systems,
The address conversion mechanism does not perform address conversion when a central processing unit that executes the operating system to which the input / output device is assigned among the plurality of operating systems outputs an address that specifies the control register, and When an address for designating the control register is output from a central processing unit that executes an operating system to which the input / output device is not assigned among the operating systems, the corresponding one of the virtual device areas is designated. An information processing apparatus that converts the information into an address to be processed. In claim 9,
The address translation mechanism has a plurality of entries corresponding to each of the plurality of operating systems;
Each of the plurality of entries has an address range including the control register and an offset value to be added. In claim 9,
Each of the plurality of virtual device areas is copied with the contents of the control register when the corresponding operating system is deallocated with the input / output device,
The information processing apparatus according to claim 1, wherein when the operating system assigned to the input / output device is changed, the contents of a virtual device area corresponding to the newly assigned operating system are copied to the control register. In claim 11,
Each of the plurality of virtual device areas has a busy flag,
The information processing apparatus is accessible when the busy flag is off. In claim 12,
While the contents of one of the plurality of virtual device areas are copied to the control register and while the contents of the control register are copied to one of the plurality of virtual device areas, the busy flag Is turned on and inaccessible.

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