JP2009260361A - Semiconductor device and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain high function in a semiconductor element 1 composed of MOSFETs, a plurality of which are formed in an integrated circuit and which constitute a logical circuit and the like. <P>SOLUTION: In a MOSFET where a source region 3 and a drain region 4 are formed in a well 2, and a gate electrode 7 is formed on a channel region 5 between those regions via a gate insulating film 6, for example an SOI substrate is used, and respective elements are electrically insulated therebetween with the use of a field oxide film. Further, for each element a contact hole is formed in an interlayer dielectric in a region other than the source region 3 and the drain region 4, and a substrate terminal TW is taken out from the channel region 5. Hereby, a two-input-one-output element can be achieved, which adopts both of a gate terminal TG and the substrate terminal TW as inputs. Upon constructing a logical circuit the degree of integration is enhanced to achieve high speed and reduction in cost. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device realized by a MOSFET and a driving method for causing the semiconductor device to perform a predetermined operation.

  The MOSFET can control the electrical continuity between the source and the drain by changing the voltage applied to the gate electrode. For example, in an N-type MOSFET, when a high level is input to the gate electrode, the source and drain are controlled. The connection is established, and shuts off when a low level is input. At this time, the potential of the well is normally fixed. For example, the potential of the well is fixed to a low level in the N-type MOSFET and to a high level in the P-type MOSFET. In this way, the conventional MOSFET is used as a three-terminal element that performs switching between the source and the drain with the gate electrode as an input.

  FIG. 22 is an electric circuit diagram of a logic circuit log1 which is an example of a typical prior art semiconductor device using such a MOSFET. In the logic circuit log1, a parallel circuit of PMOSFETs (qp1) and (qp2) to which inputs in1 and in2 to input terminals p1 and p2 are respectively applied is connected between a high-level VDD power line and an output terminal p3. A series circuit of NMOSFETs (qn1) and (qn2) to which the inputs in1 and in2 are respectively provided is configured to be interposed between the output terminal p3 and the power line of the low level GND, and the inputs in1 and in2 are few. Both are NAND circuits that set the output out to a high level when either one is at a low level.

  FIG. 23 is an electric circuit diagram of another conventional logic circuit log2. In the logic circuit log2, a series circuit of PMOSFETs (qp1) and (qp2) to which the inputs in1 and in2 are respectively applied is interposed between a power line of a high level VDD and an output terminal p3, and the inputs in1 and in2 NMOSFETs (qn1) and (qn2) are respectively provided between the output terminal p3 and the low level GND power supply line, and at least one of the inputs in1 and in2 is high. This is a NOR circuit that sets the output out to the low level when it is at the level.

  In the logic circuits log1 and log2, which are the conventional semiconductor devices as described above, each MOSFET corresponds to one input, so that four MOSFETs are required for the NAND circuit and the NOR circuit as described above. And The AND circuit can be realized by connecting a NOT circuit in series to the NAND circuit, and the OR circuit can be realized by connecting a NOT circuit in series to the NOR circuit, so each requires six MOSFETs. Therefore, it becomes an obstacle to improvement in the degree of integration, which hinders increase in operation speed, improvement in yield, and cost reduction.

  An object of the present invention is to provide a semiconductor device and a driving method thereof that can achieve high functionality.

  In order to solve the above problems, a semiconductor device according to the present invention is formed on a semiconductor substrate, a P-type or N-type deep well region formed in the semiconductor substrate, and the deep well region. The P or N conductivity type shallow well region that becomes the first electrode, and the source region that is formed in the shallow well region and becomes the second electrode with either P or N conductivity type And a drain region to be a third electrode, a channel region formed between the source region and the drain region, a gate insulating film formed on the channel region, and formed on the gate insulating film, And a gate electrode serving as a fourth electrode, and at least the shallow well region is electrically isolated between adjacent elements by the groove type isolation region, and adjacent to the groove type isolation region. Each shallow well each region between the elements is divided, is characterized by providing a contact hole in a region other than the source and drain regions.

  The semiconductor device according to the present invention has a pair of elements whose conductivity types are opposite to each other, the source of the P-type element is fixed at a high potential, the source of the N-type element is fixed at a low potential, and the gates of both are shared. Preferably, the first input terminal, the contact holes of both are commonly used as the second input terminal, and the drains of both are preferably used as the output terminal.

  The semiconductor device according to the present invention includes a pair of elements having opposite conductivity types, a P-type element source fixed at a high potential, an N-type element source fixed at a low potential, and a P-type element gate. And the contact hole of the N-type element are commonly used as the first input terminal, the contact hole of the N-type element and the contact hole of the P-type element are commonly used as the second input terminal, and the drains of both are commonly used as the output terminal. Is preferred.

  The semiconductor device according to the present invention has a pair of elements whose conductivity types are opposite to each other, the drain of the N-type element is fixed at a high potential, the drain of the P-type element is fixed at a low potential, and both gates are shared. Preferably, the first input terminal, the contact hole of both are used as the second input terminal, and the source of both are used as the output terminal.

  In addition, the semiconductor device according to the present invention includes a pair of elements whose conductivity types are opposite to each other, the drain of the N-type element is fixed at a high potential, the drain of the P-type element is fixed at a low potential, and the gate of the N-type element The P-type element contact hole is commonly used as the first input terminal, the P-type element gate and N-type element contact hole are commonly used as the second input terminal, and both drains are commonly used as the output terminal. Is preferred.

  In the semiconductor device driving method according to the present invention, it is preferable that the gate and the contact hole are input terminals in the semiconductor device, and individual input signals synchronized with each other are input.

  As described above, the semiconductor device according to the present invention is formed on a semiconductor substrate, a P-type or N-type deep well region formed in the semiconductor substrate, and the deep well region. A shallow well region of the other conductivity type of P or N which becomes one electrode, a source region which is formed in the shallow well region and becomes a second electrode by the conductivity type of P or N, and a third region A drain region to be an electrode of the first electrode, a channel region formed between the source region and the drain region, a gate insulating film formed on the channel region, and a gate insulating film formed on the gate insulating film, And at least the shallow well region is electrically isolated by the groove type isolation region between the adjacent elements, and the adjacent element is separated by the groove type isolation region. Each shallow well region which is provided with a contact hole in a region other than the source and drain regions.

  Therefore, it is possible to provide a semiconductor device that can have high functionality.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the present invention, showing a basic configuration of the present invention. 2 is a graph showing an example of operating characteristics of the semiconductor element shown in FIG. 1. 6 is a graph showing another example of the operating characteristics of the semiconductor element shown in FIG. 1. It is a front view of the semiconductor element of the 2nd Embodiment of this invention which implement | achieves the structure of FIG. 1 concretely. It is sectional drawing seen from the cut surface line VV of FIG. It is sectional drawing seen from the cut surface line VI-VI of FIG. It is a front view of the semiconductor element of the 3rd Embodiment of this invention which implement | achieves the structure of FIG. 1 concretely. It is sectional drawing seen from the cut surface line VIII-VIII of FIG. It is sectional drawing seen from the cut surface line IX-IX of FIG. FIG. 10 is an electric circuit diagram of a logic circuit according to a fourth embodiment of the present invention using the semiconductor element shown in FIGS. 11 is a graph showing operating characteristics of the logic circuit shown in FIG. 10. FIG. 10 is an electric circuit diagram of a logic circuit according to a fifth embodiment of the present invention using the semiconductor element shown in FIGS. 13 is a graph showing operating characteristics of the logic circuit shown in FIG. 12. It is a graph which shows the operating characteristic of the logic circuit of the 6th Embodiment of this invention. It is a graph which shows the operating characteristic of the logic circuit of the 7th Embodiment of this invention. FIG. 10 is an electric circuit diagram of a logic circuit according to an eighth embodiment of the present invention using the semiconductor element shown in FIGS. It is a graph which shows the operation characteristic of the logic circuit shown in FIG. FIG. 10 is an electric circuit diagram of a logic circuit according to a ninth embodiment of the present invention using the semiconductor element shown in FIGS. It is a graph which shows the operating characteristic of the logic circuit shown in FIG. It is a graph which shows the operating characteristic of the logic circuit of the 10th Embodiment of this invention. It is a graph which shows the operating characteristic of the logic circuit of the 11th Embodiment of this invention. It is an electrical circuit diagram which shows an example of the logic circuit comprised using a typical prior art MOSFET element. It is an electric circuit diagram which shows the other example of the logic circuit comprised using a typical prior art MOSFET element.

  The first embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a cross-sectional view schematically showing a semiconductor element 1 according to a first embodiment of the present invention for explaining the basic configuration of the present invention. In a normal MOSFET structure in which a source region 3 and a drain region 4 are formed in a well 2 and a gate electrode 7 is formed on a channel region 5 between them through a gate insulating film 6. The substrate terminal TW is extracted from the well 2 through the contact hole, and this is used as the first electrode. The source terminal TS is extracted from the source region 3 and becomes the second electrode, and is extracted from the drain region 4 and the third electrode. The drain terminal TD serving as the first electrode and the gate terminal TG led out from the gate electrode 7 to serve as the fourth electrode are employed. The gate terminal TG, which is the first input terminal, and the substrate terminal TW, which is the second input terminal, are given separate inputs IN1 and IN2 that are synchronized with each other based on a clock signal or the like. It is assumed that an appropriate drain voltage is applied between the drain and the source.

In the semiconductor device 1, when the well 2 is a P-type MOSFET, the relationship of the drain current with respect to the potentials of the inputs IN1 and IN2 is as shown in FIG. When the input IN2, that is, the well potential is low potential (L) and the input IN1, that is, the gate potential is low potential (L), the drain current becomes ILL, and the input IN2 is low potential (L), The drain current when the input IN1 is at a high potential (H) is I _HL .

In contrast, when the input IN2 is at a high potential (H) and the input IN1 is at a low potential (L), a drain current of I _LH flows, the input IN2 is at a high potential (H), and the input IN1 When I is at a high potential (H), a drain current of I _HH flows.

  As described above, the drain current is larger for the same input IN1 when the potential of the input IN2 is higher. This is because, when a positive voltage is applied to the well 2 in the MOSFET, the potential barrier in the channel region is lowered and the threshold voltage is lowered. That is, a positive voltage is applied to the gate electrode 7. This is because the voltage at which the drain current begins to flow sometimes decreases.

  From FIG. 2, when the input IN2 is at a low potential (L), there is little difference in drain current regardless of whether the input IN1 is at a high potential (H) or a low potential (L). When the input IN2 is at a high potential (H), there is a large difference in drain current between the high potential (H) and the low potential (L) with respect to the input IN1. Therefore, in the example of FIG. 2, the drain-source conduction is realized only when both of the inputs IN1 and IN2 are at a high potential (H), and the cutoff operation is realized in the other cases.

  On the other hand, by setting the operating characteristics as shown in FIG. 3, when at least one of the inputs IN1 and IN2 is at a high potential (H), the drain-source is conductive and both the inputs IN1 and IN2 are low. An operation of cutting off only when the potential is (L) can be realized.

  The characteristics shown in FIG. 2 and the characteristics shown in FIG. 3 are, for example, the impurity concentration of the channel region 5 and the high potential (H) level of the inputs IN1 and IN2 in the semiconductor element 1 having the structure shown in FIG. It can be selected by appropriately adjusting the level of the low potential (L). In the case of a PMOSFET in which the well 2 is formed in an N-type, the operating characteristics are opposite to those shown in FIGS.

  In this way, an element capable of obtaining one output with respect to two inputs IN1 and IN2 synchronized with each other is realized by one element, so that the function of the element is enhanced and an integrated circuit is realized. The degree of integration can be improved.

  The second embodiment of the present invention will be described below with reference to FIGS.

  4 to 6 are views showing the structure of the semiconductor element 11 that specifically realizes the semiconductor element 1 described above. 4 is a front view, FIG. 5 is a cross-sectional view taken along the cutting plane line V-V in FIG. 4, and FIG. 6 is a cross-sectional view taken along the cutting plane line VI-VI in FIG. FIG. 4 shows a substantial element portion from which an upper metal wiring and an interlayer insulating film described later are removed.

  The semiconductor element 11 uses an SOI substrate in which a base insulating film 13 is formed on a semiconductor substrate 12 and a semiconductor layer 14 is further formed on the base insulating film 13. Further, the semiconductor layer 14 is electrically isolated from each other by the field oxide film 15 between adjacent elements, and is configured not to be affected by a change in well potential between adjacent elements. In the semiconductor layer 14, the conductivity type opposite to the conductivity type of the semiconductor layer 14, that is, for example, when the semiconductor element 11 is an NMOSFET, the conductivity type of the semiconductor layer 14 is P-type, The source region 3 and the drain region 4 are formed, and a gate electrode 7 is formed on the channel region between the source region 3 and the drain region 4 with the gate insulating film 6 interposed therebetween.

  The element thus formed is covered with an interlayer insulating film 16. Contact holes 17, 18 and 19 are formed in the interlayer insulating film 16, and upper metal wirings 21, 22 and 23 are electrically connected to the source region 3, the drain region 4 and the gate electrode 7, respectively. Thus, the upper metal wirings 21, 22, and 23 become the source terminal TS, the drain terminal TD, and the gate terminal TG that is the first input terminal, respectively. In the interlayer insulating film 16, a contact hole 20 is formed in a region other than the source region 3 and the drain region 4. In the semiconductor layer 14, a region 14 a corresponding to the contact hole 20 is a region having the same conductivity type and a high impurity concentration as the semiconductor layer, and the upper metal wiring 24 formed in the contact hole 20 by the region 14 a. Are ohmic-connected to the semiconductor layer 14 and the upper metal wiring 24 becomes a substrate terminal TW which is a second input terminal.

  With such a structure, by simply forming a field oxide film 15 on the semiconductor layer 14 using an SOI substrate, the four terminals as shown in FIG. An element can be realized.

  A third embodiment of the present invention will be described below with reference to FIGS.

  7 to 9 are views showing the structure of the semiconductor element 31 in which the semiconductor element 1 shown in FIG. 1 is realized with a structure different from that of the semiconductor element 11 shown in FIGS. 7 is a front view, FIG. 8 is a cross-sectional view taken along section line VIII-VIII in FIG. 7, and FIG. 9 is a cross-sectional view taken along section line IX-IX in FIG. In FIG. 7, the interlayer insulating film and the upper metal wiring are omitted.

  The semiconductor element 31 uses a substrate in which a deep well region 33 and a shallow well region 34 having a conductivity type opposite to that of the deep well region 33 are stacked in a semiconductor substrate 32. A high-concentration buried region 35 for reducing the resistance of the shallow well region 34 is formed in the shallow well region 34, and an electrically insulating trench type element isolation is provided between adjacent elements. The regions 36 are electrically separated from each other. In the shallow well region 34, a source region 3 and a drain region 4 having a conductivity type opposite to that of the shallow well region 34 are formed, and a channel region between the source region 3 and the drain region 4 is formed on the shallow well region 34. A gate electrode 7 is formed through the gate insulating film 6.

  The source region 3, drain region 4 and gate electrode 7 are electrically connected to upper metal wirings 45, 46 and 47 through contact holes 41, 42 and 43 formed in the interlayer insulating film 37, respectively. . Further, in the shallow well region 34, a region 34 a having a high impurity concentration is formed in a region other than the source region 3 and the drain region 4, and this region 34 a is a contact hole 44 formed in the interlayer insulating film 37. Is electrically connected to the upper metal wiring 48. As a result, the shallow well region 34 is ohmically connected to the upper metal wiring 48. A field oxide film 38 is formed between the region 34 a and the gate electrode 7.

In the semiconductor element 31, the source region 3 and the drain region 4 are formed with a depth of, for example, about 100 nm and an impurity concentration of 1 × 10 ²⁰ / cm ³ or more, and the shallow well region 34 has a depth of about 100 nm. The high-concentration buried region 35 is formed with a depth of 500 to 700 nm and a peak at which the impurity concentration distribution is at a peak, and is formed at a thickness of 1,000 nm and an impurity concentration of 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ^3. The concentration is about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ , and the deep well region 33 is formed with a depth of about 3 μm and an impurity concentration of about 5 × 10 ¹⁶ / cm ³ . Note that the depth and impurity concentration of each region are not limited to this.

  The depth of the trench type element isolation region 36 is the same as the depth of the shallow well region 34, the width of the depletion layer formed by the junction of the shallow well region 34 and the deep well region (more precisely, the depletion layer width). Among them, the shallow well region 34 can be electrically insulated from each other by setting the length (extended to the deep well region 33 side) to a value equal to or greater than the added value.

  On the other hand, the depth of the trench type element isolation region 36 does not reach the total value of the depth of the shallow well region 34 and the width of the depletion layer formed by the junction of the shallow well region 34 and the deep well region 33. In this case, the depletion layer on the deep well region 33 side electrically connects the shallow well regions 33 of adjacent elements, and punch-through occurs.

  For this reason, with the configuration as described above, adjacent grooves are electrically insulated from each other only by increasing a slight space of the groove-type isolation region 36 that is substantially equal to the minimum processing dimension in element formation. be able to. As a result, the four-terminal semiconductor element 1 as shown in FIG. 1 can be formed without using an expensive SOI substrate having a high body resistance as in the semiconductor element 11 shown in FIGS. Can do.

  The following describes the fourth embodiment of the present invention with reference to FIG. 10 and FIG.

FIG. 10 shows a specific example using the above-described semiconductor elements 1, 11, and 31 which are unit elements, and is an electric circuit diagram of a logic circuit LOG1 having a CMOS structure. The logic circuit LOG1 includes a pair of PMOSFET (QP) and NMOSFET (QN), and the source TSP of the PMOSFET (QP) is connected to a high level (V _DD ) power supply line, and the NMOSFET (QN) Source TSN is connected to a low level (GND) power supply line, drains TDP and TDN of both MOSFETs (QP) and (QN) are connected in common to the output terminal P3, and gates TGP and TGN are connected in common to the first In the configuration of a normal CMOS inverter connected to the input terminal P1, the substrate terminals TWP and TWN are commonly connected to the second input terminal P2.

Further, by appropriately selecting the power supply voltage V _DD and the impurity concentration of the channel region, the operation characteristics of the drain current with respect to the inputs IN1 and IN2 of the PMOSFET (QP) are set as shown in FIG. Similarly, the operation characteristics of the drain current for the inputs IN1 and IN2 of the NMOSFET (QN) are set as shown in FIG. That is, both MOSFETs (QP) and (QN) have a threshold voltage (a break point in the graph) higher than the high potential (H) when the input IN2 is at a low potential (L), and the input IN2 is at a high potential (H). In some cases, the threshold voltage is set to be lower than the high potential (H) and higher than the low potential (L).

  In the logic circuit LOG1 configured as described above, when the input IN1 is at a low potential (L), regardless of the potential of the input IN2, the PMOSFET (QP) is turned on, the NMOSFET (QN) is cut off, and the output OUT Becomes a high potential (H). In contrast, when the input IN1 is at a high potential (H), when the input IN2 is at a low potential (L), the PMOSFET (QP) is turned on, the NMOSFET (QN) is cut off, and the output OUT is at a high potential. When the input IN2 becomes the high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT becomes the low potential (L). The above operations are summarized as shown in Table 1. The output OUT becomes a low potential (L) only when both the inputs IN1 and IN2 are at a high potential (H), and at least one of the inputs IN1 and IN2 is low. It is understood that a NAND operation in which the output OUT becomes a high potential (H) when the potential is (L) is realized.

  Therefore, a NAND circuit that normally requires four MOSFETs can be realized with two MOSFETs, and the degree of integration can be improved when an integrated circuit is formed.

  The following describes the fifth embodiment of the present invention with reference to FIG. 12 and FIG.

FIG. 12 is an electric circuit diagram of the logic circuit LOG2 according to the fifth embodiment of this invention. The logic circuit LOG2 includes a pair of P and N MOSFETs (QP) and (QN), and the source TSP of the PMOSFET (QP) is connected to the high-level (V _DD ) power supply line. The source TSN of (QN) is connected to the low-level (GND) power supply line, and both drains TDP and TDN are connected to the output terminal P3 in common with the logic circuit LOG1 described above. However, the gate TGP of the PMOSFET (QP) and the substrate terminal TWN of the NMOSFET (QN) are commonly connected to the input terminal P1, and the gate TGN of the NMOSFET (QN) and the substrate terminal TWP of the PMOSFET (QP) are input in common. It is connected to the terminal P2.

  The operating characteristics of the logic circuit LOG2 are set as shown in FIG. That is, as shown in FIG. 13A, the PMOSFET (QP) has an input IN2, that is, a threshold voltage higher than a high potential (H) when the well potential is a low potential (L), and the input IN2 is a high potential. When (H), the threshold voltage is set to be lower than the high potential (H) and higher than the low potential (L). On the other hand, as shown in FIG. 13B, the NMOSFET (QN) has a threshold voltage higher than the high potential (H) when the input IN1 is at a low potential (L), and the input IN1 is at a high potential (H). When it is H), the threshold voltage is set to be lower than the high potential (H) and higher than the low potential (L).

  Therefore, when the input IN1 is at a low potential (L), regardless of the level of the input IN2, the PMOSFET (QP) becomes conductive, the NMOSFET (QN) is cut off, and the output OUT becomes a high potential (H). When the input IN1 is at a high potential (H) and the input IN2 is at a low potential (L), the PMOSFET (QP) is turned on, the NMOSFET (QN) is cut off, and the output OUT is at a high potential (H). . Furthermore, when both the inputs IN1 and IN2 are at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT is at a low potential (L).

  That is, as shown in Table 1, the output OUT becomes a low potential (L) only when both the inputs IN1 and IN2 are at a high potential (H), and in other cases, the output OUT becomes a high potential (H). Become. Even with this configuration, the NAND operation can be realized.

  The following describes the sixth embodiment of the present invention with reference to FIG.

  In the sixth embodiment, in the logic circuit LOG1 shown in FIG. 10, the operating characteristics of the MOSFETs (QP) and (QN) are set as shown in FIG. 11 (a) and FIG. 11 (b), respectively. Instead, the settings are made as shown in FIGS. 14 (a) and 14 (b). That is, in both MOSFETs (QP) and (QN), when the input IN2 is at a low potential (L), the threshold voltage is higher than the low potential (L) and lower than the high potential (H), and the input IN2 is at a high potential. When (H), the threshold voltage is set to be lower than the low potential (L).

  Thus, when the input IN1 is at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT becomes a low potential (L) regardless of the potential of the input IN2. Also, when the input IN1 is at a low potential (L) and the input IN2 is at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is conducted, and the output OUT is at a low potential ( L). Furthermore, when both the inputs IN1 and IN2 are at a low potential (L), the PMOSFET (QP) becomes conductive, the NMOSFET (QN) is cut off, and the output OUT becomes a high potential (H). Therefore, when these operations are summarized, as shown in Table 2, the output OUT becomes the high potential (H) only when the inputs IN1 and IN2 are both at the low potential (L), and in other cases, the output OUT is A NOR operation at a low potential (L) can be realized.

  In this way, a NOR circuit that normally requires four MOSFETs can be realized by two MOSFETs.

  The seventh embodiment of the present invention will be described below with reference to FIG.

  FIG. 15 is a graph showing the operating characteristics of the seventh embodiment of the present invention, and is applied to the logic circuit LOG2 shown in FIG. FIG. 15A shows the operating characteristics of the PMOSFET (QP), and FIG. 15B shows the operating characteristics of the NMOSFET (QN). That is, when the well potential (input IN2) of the PMOSFET (QP) and the well potential (input IN1) of the NMOSFET (QN) are both low potential (L), the respective threshold voltages are higher than the low potential (L). And when the well potential is both high potential (H), the threshold voltage is set to be lower than the low potential (L).

  Therefore, when the input IN1 is at a high potential (H), regardless of the potential of the input IN2, the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT is at a low potential (L). Also, when the input IN1 is at a low potential (L) and the input IN2 is at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is conducted, and the output OUT is at a low potential (L). ) Furthermore, when both the inputs IN1 and IN2 are at a low potential (L), the PMOSFET (QP) becomes conductive, the NMOSFET (QN) is cut off, and the output OUT becomes a high potential (H).

  Therefore, even with this configuration, as shown in Table 2, the output OUT is at a high potential (H) only when the inputs IN1 and IN2 are both at a low potential (L). A NOR operation at a low potential (L) can be realized.

  The eighth embodiment of the present invention will be described below with reference to FIGS.

FIG. 16 is an electric circuit diagram of the logic circuit LOG3 according to the eighth embodiment of the present invention. In this logic circuit LOG3, the drain TDN of the NMOSFET (QN) is connected to the high level (V _DD ) power line, the drain TDP of the PMOSFET (QP) is connected to the low level (GND) power line, and both MOSFETs ( QP) and (QN) sources TSP and TSN are commonly connected to an output terminal P3, gates TGP and TGN are commonly connected to a first input terminal P1, and substrate terminals TWP and TWN are commonly connected to a second input. Connected to terminal P2.

Further, by appropriately selecting the power supply voltage V _DD and the impurity concentration of the channel region, the operation characteristics of the drain current with respect to the inputs IN1 and IN2 of the PMOSFET (QP) are set as shown in FIG. Similarly, the operating characteristics of the drain current for the inputs IN1 and IN2 of the NMOSFET (QN) are set as shown in FIG.

  That is, when both MOSFETs (QP) and (QN) are both input IN2, that is, when the well potential is low potential (L), the threshold voltage is set to be higher than high potential (H), and input IN2 is high potential. When it is (H), the threshold voltage is set to be lower than the high potential (H) and higher than the low potential (L).

  Therefore, when the input IN1 is at a low potential (L), the PMOSFET (QP) is conducted, the NMOSFET (QN) is cut off, and the output OUT is at a low potential (L) regardless of the potential of the input IN2. Further, when the input IN1 is at a high potential (H) and the input IN2 is at a low potential (L), the PMOSFET (QP) is conducted, the NMOSFET (QN) is cut off, and the output OUT is at a low potential (L). ) Furthermore, when the inputs IN1 and IN2 are both at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT is at a high potential (H).

  Therefore, as shown in Table 3, the output OUT becomes a high potential (H) only when both the inputs IN1 and IN2 are at a high potential (H), and in other cases, the output OUT becomes a low potential (L). It is understood that the AND operation is performed.

  In this way, as described in the prior art, an AND circuit normally composed of six MOSFETs can be realized with two MOSFETs.

  The ninth embodiment of the present invention will be described below with reference to FIGS.

FIG. 18 is an electric circuit diagram of the logic circuit LOG4 according to the ninth embodiment of this invention. In this logic circuit LOG4, the drain TDN of the NMOSFET (QN) is connected to the high level (V _DD ) power line, and the drain TDP of the PMOSFET (QP) is connected to the low level (GND) power line. The point that the sources TSP and TSN are commonly connected to the output terminal P3 is similar to the above-described logic circuit LOG3. However, the gate TGN of the NMOSFET (QN) and the substrate terminal TWP of the PMOSFET (QP) are commonly connected to the input terminal P1, and the gate TGP of the PMOSFET (QP) and the substrate terminal TWN of the NMOSFET (QN) are input in common. It is connected to the terminal P2.

  Further, the operating characteristics of the logic circuit LOG4 are set as shown in FIG. That is, as shown in FIG. 19A, the PMOSFET (QP) has a threshold voltage higher than the high potential (H) when the input IN1, ie, the well potential is low potential (L), and the input IN1 is high potential. When (H), the threshold voltage is set to be lower than the high potential (H) and higher than the low potential (L). On the other hand, as shown in FIG. 19B, the NMOSFET (QN) has a threshold voltage higher than the high potential (H) when the input IN2 is at a low potential (L), and the input IN2 is at a high potential (H). When it is H), the threshold voltage is set to be lower than the high potential (H) and higher than the low potential (L).

  Therefore, when the input IN1 is at a low potential (L), regardless of the level of the input IN2, the PMOSFET (QP) is turned on, the NMOSFET (QN) is cut off, and the output OUT is at a low potential (L). When the input IN1 is at a high potential (H) and the input IN2 is at a low potential (L), the PMOSFET (QP) is turned on, the NMOSFET (QN) is cut off, and the output OUT is at a low potential (L). . Furthermore, when the inputs IN1 and IN2 are both at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT is at a high potential (H).

  That is, as shown in Table 3, the output OUT is at a high potential (H) only when both the inputs IN1 and IN2 are at a high potential (H), and in other cases, the output OUT is at a low potential (L). Become. Even with this configuration, the AND operation can be realized.

  The tenth embodiment of the present invention will be described below with reference to FIG.

  FIG. 20 is a graph showing the operating characteristics of the tenth embodiment of the present invention. This operating characteristic is applied to the logic circuit LOG3 shown in FIG. 20A shows the operating characteristics of the PMOSFET (QP), and FIG. 20B shows the operating characteristics of the NMOSFET (QN). Therefore, when the well potentials of the MOSFETs (QP) and (QN), that is, the input IN2 is both low potential (L), the threshold voltage is higher than the low potential (L) and lower than the high potential (H). When IN2 is at a high potential (H), the threshold voltage is set to be lower than the low potential (L).

  Thus, when the input IN1 is at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT becomes a high potential (H) regardless of the potential of the input IN2. Even when the input IN1 is at a low potential (L) and the input IN2 is at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT is at a high potential (H). ) Furthermore, when both the inputs IN1 and IN2 are at a low potential (L), the PMOSFET (QP) is turned on, the NMOSFET (QN) is cut off, and the output OUT is at a low potential (L).

  That is, as shown in Table 4, the output OUT is at a low potential (L) only when both the inputs IN1 and IN2 are at a low potential (L), and in other cases, the output OUT is at a high potential (H). It is understood that an OR operation is realized.

  In this way, as described above, an OR circuit that is normally composed of six MOSFETs can be realized with two MOSFETs.

  The eleventh embodiment of the present invention will be described below with reference to FIG.

  FIG. 21 is a graph showing the operating characteristics of the eleventh embodiment of the present invention, and is applied to the logic circuit LOG4 shown in FIG. FIG. 21A shows the operating characteristics of the PMOSFET (QP), and FIG. 21B shows the operating characteristics of the NMOSFET (QN). That is, when the well potential (input IN1) of the PMOSFET (QP) and the well potential (input IN2) of the NMOSFET (QN) are low potential (L), the threshold voltage is higher than the low potential (L) and high When the potential is lower than the potential (H) and the well potential is the high potential (H), the threshold voltage is set to be lower than the low potential (L).

  Therefore, when the input IN1 is at a high potential (H), regardless of the potential of the input IN2, the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT becomes a high potential (H). Even when the input IN1 is at a low potential (L) and the input IN2 is at a high potential (H), the PMOSFET (QP) is cut off, the NMOSFET (QN) is turned on, and the output OUT is at a high potential (H). ) Furthermore, when both the inputs IN1 and IN2 are at a low potential (L), the PMOSFET (QP) is turned on, the NMOSFET (QN) is cut off, and the output OUT is at a low potential (L).

  That is, as shown in Table 4, the output OUT is low potential (L) only when both the inputs IN1 and IN2 are low potential (L), and in other cases, the output OUT is high potential (H). Even in this configuration, the OR operation can be realized.

  As described above, the semiconductor device according to the present invention electrically isolates the formation region of each element by the element isolation region on the SOI, SOS structure substrate, and forms a MOSFET for each separated element formation region. Then, the semiconductor layer of the MOSFET can be used as an electrode by being electrically connected to the outside through a contact hole.

  Therefore, a 2-input, 1-output circuit can be realized with one element, and the function of a single MOSFET can be improved. Thus, for example, when a logic circuit is configured, the degree of integration can be improved in the integration of an integrated circuit, and the operation speed can be increased, the yield can be improved, and the cost can be reduced.

  In addition, as described above, the semiconductor device according to the present invention forms either the P or N conductive type deep well region and the P or N conductive type shallow well region in the semiconductor substrate. In addition, using a bulk substrate in which at least the shallow well region is electrically isolated by a trench type isolation region between adjacent elements, a MOSFET is formed for each isolated element formation region, and the source of the MOSFET A contact hole is provided in a region other than the region and the drain region, and the shallow well region is electrically connected to the outside so that it can be used as an electrode.

  According to the above configuration, even in a bulk substrate, the shallow well region of each element formation region is electrically insulated by the grooved element isolation region, thereby preventing interference between the elements and for each element. Individual operation of Then, the semiconductor layer of the MOSFET is electrically connected to the outside through a contact hole and can be used as an electrode, and two inputs, that is, an input to the gate and an input to the semiconductor layer are enabled.

  Therefore, a 2-input, 1-output circuit can be realized with one element, and the function of a single MOSFET can be improved. Thus, for example, when a logic circuit is configured, the degree of integration can be improved in the integration of an integrated circuit, and the operation speed can be increased, the yield can be improved, and the cost can be reduced. Further, the cost can be reduced and the resistance value of the first electrode can be reduced as compared with the case where an SOI or SOS substrate is used.

  Furthermore, as described above, in the semiconductor device according to the present invention, in the configuration of the CMOS inverter in which the conductivity types are a pair of elements having opposite polarities, both contact holes are shared by the second semiconductor device. Both input and normal gates are used as input terminals in common.

  Therefore, a NAND or NOR circuit can be realized by appropriately adjusting the potential of two inputs or the impurity concentration of the channel region, and these circuits that conventionally required four MOSFETs are realized by two MOSFETs. can do.

  Furthermore, as described above, the semiconductor device according to the present invention includes a CMOS inverter having a pair of elements whose conductivity types are opposite to each other in the semiconductor device. The second input terminal is used, and the contact holes of the NMOSFET and PMOSFET are also used as the first and second input terminals, respectively.

  Therefore, a NAND or NOR circuit can be realized by appropriately adjusting the two input potentials or the impurity concentration of the channel region. Thus, these circuits that conventionally required four MOSFETs can be realized by two MOSFETs.

  Furthermore, as described above, the semiconductor device according to the present invention includes a pair of elements whose conductivity types are opposite to each other in the semiconductor device, the drain of the N-type element is fixed at a high potential, and the drain of the P-type element. Is fixed at a low potential, both gates are commonly used as a first input terminal, and both contact holes are commonly used as a second input terminal.

  Therefore, an AND or OR circuit can be realized by appropriately adjusting the two input potentials or the impurity concentration of the channel region. Thus, these circuits that conventionally required six MOSFETs can be realized by two MOSFETs.

  In addition, as described above, the semiconductor device according to the present invention includes a pair of elements whose conductivity types are opposite to each other in the semiconductor device, the drain of the N-type element is fixed at a high potential, and the drain of the P-type element is The low potential is fixed, the gate of the N-type element and the contact hole of the P-type element are commonly used as the first input terminal, the gate of the P-type element and the contact hole of the N-type element are commonly used as the second input terminal, Are commonly used as output terminals.

  Therefore, an AND or OR circuit can be realized by appropriately adjusting the two input potentials or the impurity concentration of the channel region. Thus, these circuits that conventionally required six MOSFETs can be realized by two MOSFETs.

  Furthermore, as described above, in the semiconductor device driving method according to the present invention, in any of the semiconductor devices described above, the gate and the contact hole are used as input terminals, respectively, and are synchronized with each other by a clock or the like. Input an input signal.

  Therefore, not a simple 1-input 1-output ON / OFF operation, but a 2-input 1-output logic circuit operation can be realized, and a logic circuit can be configured with a small number of elements.

  A semiconductor device according to the present invention includes a semiconductor substrate, a base insulating film formed on the semiconductor substrate, and formed between the base insulating film and surrounded by an electrically insulating element isolation region. Are divided into semiconductor layers of one of P and N conductivity types serving as the first electrode, and source regions formed in the semiconductor layer and serving as the second electrode of either P or N conductivity type And a drain region to be a third electrode, a channel region formed between the source region and the drain region, a gate insulating film formed on the channel region, and formed on the gate insulating film, A gate electrode serving as a fourth electrode may be provided, and a contact hole may be provided in a region other than the source region and the drain region for each semiconductor layer partitioned by the element isolation region.

  According to the above configuration, by using a substrate having an SOI (Silicon On Insulator) or SOS (Silicon On Sapphire) structure in which an element is formed on a base insulating film formed on a semiconductor substrate, the formation region of each element is defined as an element. Each isolation region can be electrically isolated relatively easily by the isolation region, thus preventing interference between the respective elements and enabling individual operations for each element. A MOSFET is formed every time. Then, the semiconductor layer of each MOSFET is electrically connected to the outside through a contact hole so that it can be used as an electrode, and two inputs, that is, an input to the gate and an input to the semiconductor layer are enabled 4 A terminal element is realized.

  Therefore, a 2-input, 1-output circuit can be realized with one element, and the function of a single MOSFET can be improved. Thus, for example, when a logic circuit is configured, the degree of integration can be improved in the integration of an integrated circuit, and the operation speed can be increased, the yield can be improved, and the cost can be reduced.

  The semiconductor device according to the present invention includes a semiconductor substrate, a P-type or N-type deep well region formed in the semiconductor substrate, a first electrode formed on the deep well region. A shallow well region of the other conductivity type of P or N, and a source region and a third electrode formed in the shallow well region and serving as the second electrode of either P or N conductivity type, A drain region, a channel region formed between the source region and the drain region, a gate insulating film formed on the channel region, and a fourth electrode formed on the gate insulating film And at least the shallow well region is electrically isolated by the groove type isolation region between adjacent elements, and the adjacent elements are separated by the groove type isolation region. Each shallow well region may be characterized by providing a contact hole in a region other than the source and drain regions.

  According to the above configuration, even in the bulk substrate, the shallow well region of each element formation region is electrically insulated by the groove-type isolation region, thereby preventing interference between the respective elements. A MOSFET is formed for each separated element formation region in a state where individual operations are possible. Then, the shallow well region of the MOSFET is electrically connected to the outside through a contact hole and can be used as an electrode, and two inputs, that is, an input to the gate and an input to the shallow well region are enabled. A four-terminal element is realized.

  Therefore, a 2-input, 1-output circuit can be realized with one element, and the function of a single MOSFET can be improved. Thus, for example, when a logic circuit is configured, the degree of integration can be improved in the integration of an integrated circuit, and the operation speed can be increased, the yield can be improved, and the cost can be reduced. Further, the cost can be reduced and the resistance value of the first electrode can be reduced as compared with the case where an SOI or SOS substrate is used.

  Furthermore, in the semiconductor device according to the present invention, in the semiconductor device, a pair of elements whose conductivity types are opposite to each other is paired, the source of the P-type element is fixed at a high potential, and the source of the N-type element is fixed at a low potential. Both gates may be commonly used as first input terminals, both contact holes may be commonly used as second input terminals, and both drains may be commonly used as output terminals.

  According to the above configuration, in the configuration of the CMOS inverter in which the source of the PMOSFET is fixed at a high potential, the source of the NMOSFET is fixed at a low potential, and the drains of both are output, of the pair of P and N MOSFETs, The hole is commonly used as the second input terminal, and the two gates that are normal inputs are commonly used as the first input terminal.

  Accordingly, a NAND or NOR circuit can be realized by appropriately adjusting the potentials of the two inputs or the impurity concentration of the channel region. Thus, these circuits that conventionally required four MOSFETs can be realized by two MOSFETs.

  Furthermore, in the semiconductor device according to the present invention, in the semiconductor device, a pair of elements whose conductivity types are opposite to each other is paired, the source of the P-type element is fixed at a high potential, and the source of the N-type element is fixed at a low potential. The gate of the P-type element and the contact hole of the N-type element are commonly used as the first input terminal, the gate of the N-type element and the contact hole of the P-type element are commonly used as the second input terminal, and the drains of both are common. The output terminal may be a feature.

  In the configuration of the CMOS inverter in which the source of the PMOSFET is fixed at a high potential, the source of the NMOSFET is fixed at a low potential, and the drains of both are output, of the pair of P and N MOSFETs, the PMOSFET and the NMOSFET The gates are the first and second input terminals, respectively, and the contact holes of the NMOSFET and PMOSFET are also the first and second input terminals, respectively.

  Accordingly, a NAND or NOR circuit can be realized by appropriately adjusting the potentials of the two inputs or the impurity concentration of the channel region. Thus, these circuits that conventionally required four MOSFETs can be realized by two MOSFETs.

  Furthermore, in the semiconductor device according to the present invention, in the semiconductor device, a pair of elements whose conductivity types are opposite to each other is paired, the drain of the N-type element is fixed at a high potential, and the drain of the P-type element is fixed at a low potential. Both gates may be commonly used as first input terminals, both contact holes may be commonly used as second input terminals, and both sources may be commonly used as output terminals.

  According to the above configuration, an AND or OR circuit can be realized by appropriately adjusting the potentials of the two inputs or the impurity concentration of the channel region. Thus, these circuits that conventionally required six MOSFETs can be realized by two MOSFETs.

  In the semiconductor device according to the present invention, in the semiconductor device, a pair of elements whose conductivity types are opposite to each other is paired, the drain of the N-type element is fixed to a high potential, and the drain of the P-type element is fixed to a low potential. The gate of the N-type element and the contact hole of the P-type element are commonly used as the first input terminal, the gate of the P-type element and the contact hole of the N-type element are commonly used as the second input terminal, and the drains of both are shared. It is characterized by being an output terminal.

  Also with the above configuration, an AND or OR circuit can be realized by appropriately adjusting the potential of two inputs or the impurity concentration of the channel region. Thus, these circuits that conventionally required six MOSFETs can be realized by two MOSFETs.

  Furthermore, the method for driving a semiconductor device according to the present invention may be characterized in that, in any of the semiconductor devices described above, the gate and the contact hole are input terminals, and individual input signals synchronized with each other are input. .

  According to the above configuration, each element outputs one output signal for two input signals synchronized with each other by a clock or the like.

  Therefore, not a simple 1-input 1-output ON / OFF operation, but a 2-input 1-output logic circuit operation can be realized, and a logic circuit can be configured with a small number of elements.

DESCRIPTION OF SYMBOLS 1,11,31 Semiconductor element 2 Well 3 Source region 4 Drain region 5 Channel region 6 Gate insulating film 7 Gate electrode 12, 32 Semiconductor substrate 13 Underlying insulating film 14 Semiconductor layer 15, 38 Field oxide film 16, 37 Interlayer insulating film 17 , 18, 19, 20; 41, 42, 43, 44 Contact holes 21, 22, 23, 34; 45, 46, 47, 48 Upper metal wiring 33 Deep well region 34 Shallow well region 35 High concentration buried region 36 Groove Type element isolation region LOG1, LOG2, LOG3, LOG4 logic circuit QP PMOSFET
QN NMOSFET
TD; TDP, TDN Drain terminal TG; TGP, TGN Gate terminal TS; TSP, TSN Source terminal TW; TWP, TWN Substrate terminal

Claims (6)

A semiconductor substrate;
A deep well region of either P or N conductivity type formed in the semiconductor substrate;
A shallow well region of the other conductivity type formed on the deep well region and serving as the first electrode, either P or N;
A source region formed as a second electrode and a drain region formed as a third electrode in one of the conductivity types of P and N, formed in the shallow well region;
A channel region formed between the source region and the drain region;
A gate insulating film formed on the channel region;
A gate electrode formed on the gate insulating film and serving as a fourth electrode;
At least a shallow well region is electrically isolated between adjacent elements by a groove type isolation region, and a source region and a drain are provided for each shallow well region in which adjacent elements are separated by the groove type isolation region. A semiconductor device, wherein a contact hole is provided in a region other than the region.   2. The semiconductor device according to claim 1, wherein a pair of elements having opposite conductivity types is paired, a source of a P-type element is fixed at a high potential, a source of an N-type element is fixed at a low potential, and both gates are shared. The semiconductor device is characterized in that the first input terminal, the contact hole of both are used as the second input terminal, and the drain of both are used as the output terminal in common.   2. The semiconductor device according to claim 1, wherein a pair of elements having conductivity types opposite to each other is paired, a source of the P-type element is fixed at a high potential, a source of the N-type element is fixed at a low potential, and a gate of the P-type element is fixed. And the contact hole of the N-type element are commonly used as the first input terminal, the contact hole of the N-type element and the contact hole of the P-type element are commonly used as the second input terminal, and the drains of both are commonly used as the output terminal. A semiconductor device characterized by the above.   2. The semiconductor device according to claim 1, wherein a pair of elements whose conductivity types are opposite to each other is paired, a drain of the N-type element is fixed at a high potential, a drain of the P-type element is fixed at a low potential, and both gates are shared. A semiconductor device comprising: a first input terminal; a contact hole of both the terminals as a second input terminal; and a source of both terminals as an output terminal.   2. The semiconductor device according to claim 1, wherein a pair of elements whose conductivity types are opposite to each other is paired, the drain of the N-type element is fixed at a high potential, the drain of the P-type element is fixed at a low potential, and the gate of the N-type element The P-type element contact hole is commonly used as the first input terminal, the P-type element gate and N-type element contact hole are commonly used as the second input terminal, and both drains are commonly used as the output terminal. A semiconductor device characterized by the above.   6. The semiconductor device driving method according to claim 1, wherein the gate and the contact hole are input terminals, and individual input signals synchronized with each other are input.

Images