JP2009260124A - Printed circuit board - Google Patents

Printed circuit board Download PDF

Info

Publication number
JP2009260124A
JP2009260124A JP2008108905A JP2008108905A JP2009260124A JP 2009260124 A JP2009260124 A JP 2009260124A JP 2008108905 A JP2008108905 A JP 2008108905A JP 2008108905 A JP2008108905 A JP 2008108905A JP 2009260124 A JP2009260124 A JP 2009260124A
Authority
JP
Japan
Prior art keywords
printed circuit
circuit board
inner layer
layer plane
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008108905A
Other languages
Japanese (ja)
Inventor
Hiroyuki Motoki
浩之 本木
Hideyuki Nakanishi
秀行 中西
Akihiro Tanaka
顕裕 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aica Kogyo Co Ltd
Original Assignee
Aica Kogyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aica Kogyo Co Ltd filed Critical Aica Kogyo Co Ltd
Priority to JP2008108905A priority Critical patent/JP2009260124A/en
Publication of JP2009260124A publication Critical patent/JP2009260124A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a printed circuit board which solves the problem that the path of return current for a transmission signal flowing on a microstrip line around a hollow becomes long to be a cause of unnecessary radiation noise, and suppresses occurrence of the unnecessary radiation noise owing to the presence of the hollow, in a printed circuit board having inner layer planes, wherein each inner layer plane is provided with the hollow. <P>SOLUTION: The printed circuit board having two or more inner layer plane layers is characterized in that an RC snubber is arranged at a part where voltage fluctuation is caused in the inner layer plane. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は、内層プレーンを有し、かつ、この内層プレーンにくり抜きが設けられているプリント基板に関し、詳しくは、このくり抜きが存在することによる不要放射ノイズの発生が抑制されたプリント基板に関する。   The present invention relates to a printed circuit board having an inner layer plane and having a cutout in the inner layer plane, and more particularly to a printed circuit board in which generation of unnecessary radiation noise due to the presence of the cutout is suppressed.

一般に、プリント基板の部品実装用パッド(以下、単にパッドという)の幅は、これに接続されたマイクロストリップ線路の幅よりも大きいため、パッドの単位長さ当たりの静電容量がマイクロストリップ線路の単位長さ当たりの静電容量よりも大きくなる。そのため、パッドの特性インピーダンスは、マイクロストリップ線路の特性インピーダンスよりも小さくなる。   In general, the width of a component mounting pad (hereinafter simply referred to as a pad) on a printed circuit board is larger than the width of a microstrip line connected to the pad, so that the capacitance per unit length of the pad is less than that of the microstrip line. It becomes larger than the electrostatic capacity per unit length. Therefore, the characteristic impedance of the pad is smaller than the characteristic impedance of the microstrip line.

そこで、これらパッドの特性インピーダンス及びマイクロストリップ線路の特性インピーダンスの整合技術として、パッドの直下の内層プレーンの導体をくり抜くという技術がある。この技術によれば、パッドと内層プレーンとの距離が大きくなり、パッドの静電容量が小さくなるので、パッドの特性インピーダンスの低下が抑制され、もって、パッドの特性インピーダンスをマイクロストリップ線路の特性インピーダンスとを合させることができる。   Therefore, as a technique for matching the characteristic impedance of these pads and the characteristic impedance of the microstrip line, there is a technique of hollowing out the conductor of the inner layer plane immediately below the pads. According to this technology, the distance between the pad and the inner layer plane is increased, and the capacitance of the pad is reduced, so that a decrease in the characteristic impedance of the pad is suppressed, so that the characteristic impedance of the pad is changed to that of the microstrip line. Can be combined.

特許第2654414号公報Japanese Patent No. 2654414

内層プレーンに前述のくり抜きを設けることにより、このくり抜きの周辺でマイクロストリップ線路を流れる伝送信号に対するリターン電流の経路が長くなる。これにより近傍磁界ノイズが発生するという現象がある。特にグランド電位がコモンモードノイズにより揺らいでいる場合、不要放射ノイズの原因となる。   By providing the above-described cutout in the inner plane, the return current path for the transmission signal flowing through the microstrip line around the cutout becomes long. This causes a phenomenon that near magnetic field noise is generated. In particular, when the ground potential fluctuates due to common mode noise, it causes unnecessary radiation noise.

そこで、本発明が解決しようとする課題は、内層プレーンを有し、かつ、この内層プレーンにくり抜きが設けられているプリント基板において、このくり抜きが存在することによる不要放射ノイズの発生が抑制されたプリント基板を得ることを課題とする。   Therefore, the problem to be solved by the present invention is that the generation of unnecessary radiation noise due to the presence of the cutout is suppressed in the printed circuit board having the inner layer plane and the cutout provided in the inner layer plane. An object is to obtain a printed circuit board.

上記課題解決のための請求項1に記載の発明は、2つ以上の内層プレーン層を有するプリント基板において、前記内層プレーンにおける電圧変動が生ずる箇所にRCスナバが配置されていることを特徴とするプリント基板である。ここでいうRCスナバとは、抵抗とコンデンサとからなる直列回路をいう。   The invention described in claim 1 for solving the above-mentioned problem is characterized in that, in a printed circuit board having two or more inner plane layers, an RC snubber is arranged at a location where voltage fluctuation occurs in the inner layer plane. It is a printed circuit board. The RC snubber here refers to a series circuit composed of a resistor and a capacitor.

請求項1に記載の発明によれば、ノイズの発生する信号周波数がより高い周波数にシフトするとともに、抵抗がノイズ分を消費するので、不要放射ノイズを抑制することができる。   According to the first aspect of the present invention, the signal frequency at which noise is generated is shifted to a higher frequency, and the resistor consumes noise, so that unnecessary radiation noise can be suppressed.

図1は、測定のためのサンプル基板100の平面図である。また、図2は、サンプル基板100の背面図である。このサンプル基板100は、長手方向の長さが100mm、短手方向の長さが12mm、層数は4層で、信号層と直下のグランド層間との距離は0.12mm、内層の第1グランド層及び第2グランド層間の距離は1.2mmである。   FIG. 1 is a plan view of a sample substrate 100 for measurement. FIG. 2 is a rear view of the sample substrate 100. This sample substrate 100 has a length in the longitudinal direction of 100 mm, a length in the short direction of 12 mm, the number of layers is 4, the distance between the signal layer and the ground layer immediately below is 0.12 mm, and the first ground of the inner layer The distance between the layer and the second ground layer is 1.2 mm.

このサンプル基板100のパターン長は82mmで中央にパッド101が設けられている。このパッド101は、長手方向が2.0mm、短手方向が1.5mmである。また、第1グランド層においては、このパッド101の直下にくり抜き(図示せず)が設けてある。このくり抜きの寸法は長手方向が2.2mm、短手方向が1.7mmである。   The pattern length of the sample substrate 100 is 82 mm, and a pad 101 is provided at the center. The pad 101 has a longitudinal direction of 2.0 mm and a lateral direction of 1.5 mm. In the first ground layer, a hollow (not shown) is provided immediately below the pad 101. The dimension of the cutout is 2.2 mm in the longitudinal direction and 1.7 mm in the lateral direction.

またさらに、図3は、サンプル基板100におけるSMAコネクタ102との接続構造を示す模式断面図である。このサンプル基板100は、SAMコネクタ102がスルーホールに挿入されることにより、第1グランド層及び第2グランド層がショートする。   FIG. 3 is a schematic cross-sectional view showing a connection structure with the SMA connector 102 in the sample substrate 100. In the sample substrate 100, the first ground layer and the second ground layer are short-circuited when the SAM connector 102 is inserted into the through hole.

図4は、サンプル基板100の電磁波放射の測定の様子を示す模式図である。図4を参照すると、ネットワークアナライザ103のポート1(符号をP1で示す)にケーブル105及びSMAコネクタ102を介してサンプル基板100を接続し、同様にポート2(符号をP2で示す)にダイポールアンテナ104を接続し、これらを10cm間隔で設置し、S21を測定した。   FIG. 4 is a schematic diagram showing a state of measurement of electromagnetic wave radiation of the sample substrate 100. Referring to FIG. 4, the sample board 100 is connected to the port 1 (indicated by P1) of the network analyzer 103 via the cable 105 and the SMA connector 102, and the dipole antenna is similarly connected to port 2 (indicated by P2). 104 were connected, these were installed at intervals of 10 cm, and S21 was measured.

また、サンプル基板100と同様の構造で、第1グランド層のくり抜きを設けていない第2サンプル基板(図示せず)を用意し、これを上記と同様の方法で測定した。   Further, a second sample substrate (not shown) having a structure similar to that of the sample substrate 100 and not provided with the first ground layer was prepared, and this was measured by the same method as described above.

上記の測定の結果、測定信号の周波数が2GHzにおいて、第2サンプル基板では、S21が−55dBであった。一方、サンプル基板100では、S21が−45dBであった。すなわち、サンプル基板100では、第2サンプル基板に比べてS21が増加し、放射があることが確認された。   As a result of the above measurement, S21 was −55 dB in the second sample substrate when the frequency of the measurement signal was 2 GHz. On the other hand, in the sample substrate 100, S21 was −45 dB. That is, in the sample substrate 100, S21 increased compared to the second sample substrate, and it was confirmed that there was radiation.

ここで、サンプル基板100において、10Ωの抵抗及び1pFのコンデンサからなるRCスナバを第1グランド層及び第2グランド層との間に接続したものを用意した。RCスナバは、図5の矢印の示す箇所に取り付けた。また、図6にRCスナバの接続構造を示す模式断面図を示す。上記と同様の方法でこれの電磁波放射を測定したところ、測定信号の周波数が2GHzにおいて、S21が−70dBとなった。すなわち、RCスナバを接続することにより、電磁波放射が減少したことが確認された。   Here, a sample substrate 100 in which an RC snubber composed of a 10Ω resistor and a 1 pF capacitor was connected between the first ground layer and the second ground layer was prepared. The RC snubber was attached at the location indicated by the arrow in FIG. Moreover, the schematic cross section which shows the connection structure of RC snubber in FIG. 6 is shown. When the electromagnetic wave radiation was measured by the same method as described above, S21 was -70 dB when the frequency of the measurement signal was 2 GHz. That is, it was confirmed that electromagnetic radiation was reduced by connecting the RC snubber.

符号の説明Explanation of symbols

100 サンプル基板
101 パッド
102 SMAコネクタ
103 ネットワークアナライザ
104 ダイポールアンテナ
105 ケーブル
100 Sample substrate 101 Pad 102 SMA connector 103 Network analyzer 104 Dipole antenna 105 Cable

サンプル基板の平面図。The top view of a sample board | substrate. サンプル基板の背面図。The rear view of a sample board | substrate. サンプル基板におけるSMAコネクタとの接続構造を示す模式断面図。The schematic cross section which shows the connection structure with the SMA connector in a sample board | substrate. サンプル基板の電磁波放射の測定の様子を示す模式図。The schematic diagram which shows the mode of the measurement of the electromagnetic wave radiation of a sample board | substrate. RCスナバを取り付ける箇所を示す図。The figure which shows the location which attaches RC snubber. RCスナバの接続構造を示す模式断面図。The schematic cross section which shows the connection structure of RC snubber.

Claims (1)

2つ以上の内層プレーン層を有するプリント基板において、前記内層プレーンにおける電圧変動が生ずる箇所にRCスナバが配置されていることを特徴とするプリント基板。 A printed circuit board having two or more inner plane layers, wherein an RC snubber is arranged at a location where voltage fluctuation occurs in the inner layer plane.
JP2008108905A 2008-04-18 2008-04-18 Printed circuit board Pending JP2009260124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008108905A JP2009260124A (en) 2008-04-18 2008-04-18 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008108905A JP2009260124A (en) 2008-04-18 2008-04-18 Printed circuit board

Publications (1)

Publication Number Publication Date
JP2009260124A true JP2009260124A (en) 2009-11-05

Family

ID=41387162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008108905A Pending JP2009260124A (en) 2008-04-18 2008-04-18 Printed circuit board

Country Status (1)

Country Link
JP (1) JP2009260124A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11233951A (en) * 1998-02-16 1999-08-27 Canon Inc Printed wiring board
JPH11261181A (en) * 1998-03-16 1999-09-24 Nec Corp Printed circuit board
JP2000183541A (en) * 1998-12-11 2000-06-30 Toshiba Iyo System Engineering Kk Multilayer printed board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11233951A (en) * 1998-02-16 1999-08-27 Canon Inc Printed wiring board
JPH11261181A (en) * 1998-03-16 1999-09-24 Nec Corp Printed circuit board
JP2000183541A (en) * 1998-12-11 2000-06-30 Toshiba Iyo System Engineering Kk Multilayer printed board

Similar Documents

Publication Publication Date Title
US8049118B2 (en) Printed circuit board
US7505285B2 (en) Main board for backplane buses
JP5003359B2 (en) Printed wiring board
JP4371065B2 (en) Transmission line, communication apparatus, and wiring formation method
US8748753B2 (en) Printed circuit board
US8680403B2 (en) Apparatus for broadband matching
TWI415560B (en) Structure and method for reducing em radiation, and electric object and manufacture method thereof
US9160046B2 (en) Reduced EMI with quarter wavelength transmission line stubs
US20070193775A1 (en) Impedance matching via structure for high-speed printed circuit boards and method of determining same
US7224249B2 (en) Stripline structure with multiple ground vias separated by no more than 100 mil
KR20040084780A (en) Method and apparatus for intra-layer transitions and connector launch in multilayer circuit boards
US20050224912A1 (en) Circuit and method for enhanced low frequency switching noise suppression in multilayer printed circuit boards using a chip capacitor lattice
US10045435B2 (en) Concentric vias and printed circuit board containing same
KR101577370B1 (en) Microwave filter
US8040201B2 (en) Substrate having a structure for suppressing noise generated in a power plane and/or a ground plane, and an electronic system including the same
CN101877936B (en) Wired circuit board
WO2021192073A1 (en) Circuit board and electronic device
JP2007234715A (en) Multilayer printed circuit board
JP5082250B2 (en) High frequency circuit board
JP2007189042A (en) Semiconductor device
JP2009260124A (en) Printed circuit board
JP2011096954A (en) Wiring board
JP5655730B2 (en) Electric field probe
JP6733911B2 (en) Printed wiring board, printed wiring board with electronic components
JP4960824B2 (en) Connection structure between multilayer printed wiring board and horizontal coaxial connector

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110330

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120727

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120802

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120926

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130213