JP2009260082A - Electrostatic protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic protection circuit capable of reducing the size of a circuit area, and protecting the gate oxide films of MOS transistors from electrostatic surge. <P>SOLUTION: The electrostatic protection circuit is used for a semiconductor device which includes a plurality of power source systems separated in power source and to be driven by the same voltage in a normal operation and where a signal is exchanged between the first and second circuits to be operated by the different power source systems. The electrostatic protection circuit includes protecting circuits inserted onto signal lines. The protecting circuits are two serially connected native MOS transistors with negative thresholds. The gates of the two native MOS transistors are respectively connected to the high-potential power sources of the first and second circuits. The gate oxide films are formed to be thicker than the gate films of the MOS transistors constituting the first and second circuits. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electrostatic protection circuit for preventing a gate oxide film of a MOS transistor constituting an interface portion from being destroyed by electrostatic surges when signals are exchanged between circuits operating in different power supply systems. Is.

  In Patent Document 1, in a semiconductor device having two or more types of power supply systems, when signals are exchanged between circuits operating in separate power supply systems, a large potential difference is generated between the power supply lines due to the input of electrostatic surges. Protection that prevents the gate oxide film of the MOS transistor that constitutes the input circuit of the interface portion from being destroyed by raising the potential of the signal line (signal wiring) following the high potential side A circuit is shown.

  A protection circuit disclosed in Patent Document 1 is shown in FIG. In the figure, electrostatic protection circuits HK3 and HK4 are disposed that operate when the potential difference between the signal line S11 and the two power supply lines Vss2 and Vdd2 of the right power supply system becomes excessively large. As a result, an excessive increase in the potential of the signal line S11 is suppressed, and the gate potential of the MOS transistor constituting the input circuit 44 is prevented from excessively rising to destroy the gate oxide film.

  Another protection circuit disclosed in Patent Document 1 is shown in FIG. In the figure, a protection circuit HK5 in which PMOS transistors T1 to T4 are inserted between the power supply lines vdd1, vss1, vdd2, and vss2 of the left and right power supply systems is arranged. Accordingly, when an electrostatic surge flows between the high-potential side and low-potential side power supply lines, an excessive potential difference is prevented from occurring between the signal line S11 and the power supply line.

  In addition, as shown in FIG. 7, a protection circuit having two types of power supply systems, which exchange signals with each other, between vdd1 and vss1, between vdd2 and vss2, between vss1 and vss2, and between the signal line and vss2. There are also known electrostatic protection circuits. This electrostatic protection circuit is used as a circuit for preventing electrostatic breakdown by forming a path that serves as a current escape path against the inflow of electrostatic surges between power supply wires.

  Here, in the electrostatic protection circuit of FIG. 7, when an electrostatic surge flows into vdd1 with the gate of the MOS transistor constituting the inverter of the internal circuit 12 connected to vss1 (0V) and vdd2 grounded (0V) Think about the behavior.

  The current Iesd due to the electrostatic surge is released to the ground of vdd2 via a plurality of paths indicated by arrows in FIG. In FIG. 7, the current Iesd1 flows through the protection circuits 16 and 20, the current Iesd2 flows through the PMOS (P-type MOS transistor) of the internal circuit 12 and the protection circuit 21, and these currents Iesd1 and 2 are combined. It flows to the ground of vdd2 through the protection circuit 18.

  At this time, a voltage drop occurs in the potential Vesd1 due to the electrostatic surge due to the resistance component on each path including the protection circuits 16, 18, 20, and 21. When the potential of vdd1 rises to Vesd1, since the PMOS of the internal circuit 12 is in the ON state, the potential of the node 1 that performs signal transmission rises to Vesd2 that has dropped from Vesd1 by the amount of the resistance component. There is a possibility that an excessive voltage is applied to the gate oxide film of the PMOS.

  Therefore, by arranging the protection circuit 21 having a sufficient driving capability between the node 1 and vss2, the potential (Vesd2) of the node 1 is determined by the on-resistance of the PMOS and the driving capability of the protection circuit 21, and the internal The voltage applied to the PMOS gate oxide film of the circuit 14 is suppressed.

JP-A-9-172146

  In the above-described prior art, the gate oxide films of PMOS and NMOS constituting the input inverter of the internal circuit operating in the second power supply system (vdd2-vss2 system) accompanying the rise in the potential of the signal line for transmitting and receiving signals In the case of FIG. 5, an electrostatic protection circuit called HK3 and HK4, HK5 in FIG. 6, and a protection circuit 21 in FIG.

  In recent years, the manufacturing process of a semiconductor device has been miniaturized, and the gate oxide film of a MOS transistor has been formed thin. Therefore, in order to suppress an increase in the potential of a signal line that transmits and receives signals between circuits operating on different power supply systems, a large driving force is expected for the protection circuit as described above in the configuration of the conventional technique. Therefore, the size of each protection circuit is increased, leading to an increase in circuit area.

  Further, as for HK3, HK4 in FIG. 5 and the protection circuit 21 in FIG. 7, a protection circuit using a parasitic bipolar operation of a MOS transistor is often used. Some potential difference is required between the sources. At this time, the rise in the potential of the signal line is not sufficient for the operation of the protection circuit, electrostatic breakdown of the gate oxide film occurs before the protection circuit operation, or a larger voltage is applied for a longer time than in normal operation. As a result, a load may be applied to the MOS transistor.

  An object of the present invention is to provide an electrostatic protection circuit capable of solving the problems of the prior art, reducing the circuit area, and protecting the gate oxide film of a MOS transistor from electrostatic surges. It is in.

In order to achieve the above object, the present invention provides a signal between a first circuit and a second circuit which have a plurality of power supply systems which are driven with the same voltage during normal operation and which are operated with different power supply systems. A static electricity protection circuit used in a semiconductor device for receiving and
A protection circuit inserted on a signal line through which the signal is transmitted and received,
The protection circuit is two native MOS transistors connected in series and having a negative threshold value, and the gates of the two native MOS transistors are respectively connected to the high-potential power supply of the first and second circuits. The present invention provides an electrostatic protection circuit characterized in that the gate oxide film is connected and formed thicker than the gate oxide film of the MOS transistor constituting the first and second circuits.

  According to the present invention, since the protection circuit has a simple configuration of two native NMOSs connected in series, the circuit can be reduced in size. In addition, since the gate oxide film is formed thick in the MOS device constituting the protection circuit, it is difficult to be destroyed by the electrostatic surge. In addition, by connecting the two native NMOSs to the high-potential power supply of different power supply systems, it is possible to cope with electrostatic surge inflows of different reference-application combinations, and does not hinder normal operation.

  Hereinafter, the electrostatic protection circuit of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block conceptual diagram showing the configuration of the electrostatic protection circuit of the present invention. In the figure, the electrostatic protection circuit of the present invention is applied to a semiconductor device 10 having two power supply systems separated from each other and transferring signals between circuits operating in the respective power supply systems.

  In FIG. 1, the left side shows an internal circuit (output circuit) 12 that operates in a first power supply system (high potential power supply vdd1 and low potential power supply vss1), and the right side shows a second power supply system (high potential power supply). An internal circuit (input circuit) 14 operating with a potential power supply vdd2 and a low potential power supply vss2) is shown. The first and second power supply systems are separated from each other, but are driven with the same voltage during normal operation.

  The electrostatic protection circuit includes a protection circuit 16 connected between the high potential power supply vdd1 and the low potential power supply vss1 of the first power supply system, and between the high potential power supply vdd2 and the low potential power supply vss2 of the second power supply system. The signal is exchanged between the protection circuit 18 connected to, the protection circuit 20 connected between the low potential power supply vss1 and the low potential power supply vss2, and the first internal circuit 12 and the second internal circuit 14. And a protection circuit 22 inserted on the signal line 24 for performing the above.

  Here, the semiconductor device 10 is manufactured by a process using two or more types of MOS devices (for example, MOS transistors) having different gate oxide film thicknesses. For example, the MOS devices that constitute the internal circuits 12 and 14 are formed of a thin film that is likely to cause gate oxide film breakdown when an electrostatic surge flows, but the MOS devices that constitute the protection circuit 22 are thick gate oxide films. It is formed with.

  The protection circuit 22 does not reduce the driving force of the internal circuit (output circuit) 12 during normal operation. That is, the protection circuit 22 does not affect the transmission / reception of signals between the internal circuit 12 and the internal circuit 14 during normal operation. On the other hand, the protection circuit 22 prevents the gate oxide film of the MOS device constituting the interface part of the internal circuit 12 and the internal circuit 14 from being destroyed when an electrostatic surge flows.

  The protection circuits 16, 18, and 20 are the same as those used in the conventional electrostatic protection circuit shown in FIG. The protection circuit 16 prevents the potential difference between vdd1 and vss1 from becoming too large due to the inflow of electrostatic surge. Similarly, the protection circuit 18 prevents the potential difference between vdd2 and vss2 from becoming too large. The protection circuit 20 prevents the potential difference between vss1 and vss2 from becoming too large.

  On the other hand, the protection circuit 22 cuts off the signal line connecting the internal circuit 12 and the internal circuit 14 when an electrostatic surge flows, and a high potential due to the electrostatic surge is applied to the gate oxide film of the MOS transistor constituting the internal circuits 12 and 14. Prevent application.

  Since the protection circuit 22 has a simple configuration of blocking the signal line, the circuit can be reduced in size. In addition, the MOS device constituting the protection circuit 22 has a thick gate oxide film, so it is difficult to be destroyed by an electrostatic surge. In addition, by connecting the two native NMOSs to the high-potential power supply of different power supply systems, it is possible to cope with electrostatic surge inflows of different reference-application combinations, and does not hinder normal operation.

  Next, a specific example of the electrostatic protection circuit 10 of the present invention will be described.

  FIG. 2 is a schematic diagram illustrating an example of the configuration of the electrostatic protection circuit illustrated in FIG. In the figure, a CMOS type inverter is shown as an interface part of the internal circuits 12 and 14. The inverter includes a PMOS (P-type MOS transistor) 26 and an NMOS (N-type MOS transistor) 28 connected in series between a high potential power supply vdd and a low potential power supply vss.

  The protection circuit 22 includes two native NMOSs 30 and 32 connected in series on a signal line connecting between the output of the inverter of the internal circuit 12 and the input of the inverter of the internal circuit 14. In FIG. 2, the gate of the left native NMOS 30 is connected to the high potential power supply vdd1 of the first power supply system, and the gate of the native NMOS 32 on the right side is connected to the high potential power supply vdd2 of the second power supply system.

  The native NMOSs 30 and 32 have a thicker gate oxide film and a higher withstand voltage against static electricity than the PMOS 26 and NMOS 28 constituting the internal circuits 12 and 14. In FIG. 2, the gates of the native NMOSs 30 and 32 are indicated by double lines for the purpose of expressing the difference in film thickness. The native NMOSs 30 and 32 are always on when the threshold value is negative and the high potential power source vdd and the low potential power source vss are normal potentials.

  Therefore, in the electrostatic protection circuit 10 shown in FIG. 2, during normal operation, the two native NMOSs 30 and 32 of the protection circuit 22 are always in an on state, and as described above, the driving power of the internal circuit (output circuit) 12 is reduced. There is nothing.

Next, consider the case where an electrostatic surge flows. When there is a possibility that voltage load is most likely applied to the inverter in the interface section in the configuration of FIG. 2, for example, the following two cases can be considered.
(1) When vdd2 is a reference (ground) node and an electrostatic surge flows into vdd1 (2) When vdd1 is a reference (ground) node and an electrostatic surge flows into vdd2

  First, the operation of the electrostatic protection circuit 10 shown in FIG.

  In the following description, the signal line 24 to which the output of the inverter of the internal circuit 12 is connected is the node 1, the signal line between the native NMOSs 30 and 32 is the node 2, and the signal to which the input of the inverter of the internal circuit 14 is connected. Let line 24 be node 3.

  As shown in FIG. 3, when the input potential of the inverter of the internal circuit 12 is vss1 <vdd1, the PMOS 26 (P1) is in the on state, the NMOS 28 (N1) is in the off state, and the node 1 has the same Vesd as vdd1. It is a potential. Further, the highest potential of Vesd is applied to the gate of the native NMOS 30 (NaN1) on the first internal circuit 12 side, and the node 2 is also at the potential of Vesd because it is always in the ON state.

  On the other hand, the gate of the native NMOS 32 (NaN2) on the internal circuit 14 side is grounded (0V). As described above, since the potential of the node 2 is a sufficiently high potential of Vesd, the on / off state of the native NMOS 32 is determined by the potential of the node 3.

  However, if the potentials of all the nodes 1 to 3 are 0 V before the electrostatic surge flows, the native NMOS 32 is turned on when the potential of the node 3 rises by the absolute value of the threshold value of the native NMOS 32. Change from state to off state. Therefore, the potential of the node 3 rises up to the absolute value of the threshold value of the native NMOS 32, but does not rise up to the potential Vesd due to electrostatic surge.

  From the above, when the native NMOS 30 and 32 are not inserted, the native NMOS 30 and 32 are inserted when the potential of Vesd is applied to the gate oxide film of the PMOS 26 (P2) of the internal circuit 14. Thus, the voltage load is reduced.

  Here, although the voltage applied to the gate oxide film of the PMOS 26 of the internal circuit 14 has been reduced, a similar potential Vesd is applied to the gate oxide film of the native NMOS 32. However, the gate oxide film of the native NMOS 32 is thicker than the gate oxide film of the PMOS 26 constituting the internal circuit 14. Therefore, the gate oxide film of the native NMOS 32 has sufficient resistance against the potential Vesd due to electrostatic surge.

  Next, the operation of the electrostatic protection circuit 10 shown in FIG. 2 will be described for the case (2).

  As shown in FIG. 4, it is assumed that the input potential of the internal circuit 12 is vdd1 (0 V), and that the node 3 is supplied with Vesd having the same potential as vdd2 where the load is greatest. Since the potential Vesd is applied to the gate of the native NMOS 32 (NaN2) on the internal circuit 14 side, the native NMOS 32 is always in the on state, and the node 2 also rises to the potential Vesd.

  On the other hand, the gate of the native NMOS 30 on the internal circuit 12 side is grounded (0 V). Since the potential of the node 2 is a sufficiently large potential called Vesd, on / off of the native NMOS 30 is determined by the potential of the node 1.

  Here, as in the case of (1), if the potentials of all the nodes 1 to 3 are 0 V before the flow of the electrostatic surge, the potential of the node 1 is increased by the absolute value of the threshold value of the native NMOS 30. At this point, the native NMOS 30 changes from the on state to the off state. Therefore, the potential of the node 1 rises up to the absolute value of the threshold value of the native NMOS 30, but does not rise to the potential Vesd due to electrostatic surge.

  From the above, when the native NMOSs 30 and 32 are not inserted, the native NMOSs 30 and 32 are inserted when the potential of Vesd is applied to the gate oxide film of the PMOS 26 (P1) of the internal circuit 12. Thus, the voltage load is reduced.

  Also in the case of (2), the gate oxide film of the native NMOS 30 and 32 is thicker than the gate oxide film of the PMOS 26 of the internal circuit 12. Therefore, the gate oxide film of the native NMOS 30 has sufficient resistance against the potential Vesd caused by electrostatic surge.

  As in the cases (1) and (2) above, even when the gate oxide film destruction of the MOS transistors constituting the internal circuits 12 and 14 is most likely to occur, the native NMOS 30, By inserting 32, the risk can be avoided.

  The protection circuits 16, 18, and 20 basically release the current due to the electrostatic surge from the higher potential toward the lower potential when the electrostatic surge flows. Since the configuration and operation of these protection circuits are known, detailed description thereof is omitted.

  The example in which the internal circuit 12 is an output circuit and the internal circuit 14 is an input circuit has been described, but the same applies to the case where the internal circuit 14 is an output circuit and the internal circuit 12 is an input circuit. Further, although an inverter is exemplified as the interface unit of the internal circuits 12 and 14, this is not limited, and the same applies to any circuit. Furthermore, the transmission / reception of signals between the two power supply systems has been illustrated, but the same applies to the case where there are three or more power supply systems.

The present invention is basically as described above.
Although the electrostatic protection circuit of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the spirit of the present invention. is there.

It is a block conceptual diagram showing the structure of the electrostatic protection circuit of this invention. It is the schematic of an example showing the structure of the electrostatic protection circuit shown in FIG. It is a conceptual diagram showing the operation | movement at the time of the electrostatic surge inflow of the electrostatic protection circuit shown in FIG. It is a conceptual diagram showing the operation | movement at the time of the electrostatic surge inflow of the electrostatic protection circuit shown in FIG. It is the schematic of an example showing the structure of the conventional electrostatic protection circuit. It is the schematic of an example showing the structure of the conventional electrostatic protection circuit. It is an example block conceptual diagram showing the structure of the conventional static electricity protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12, 14 Internal circuit 16, 18, 20, 22 Protection circuit 24 Signal line 26 PMOS (P type MOS transistor)
28 NMOS (N-type MOS transistor)
30,32 Native NMOS

Claims (1)

Static electricity protection used in a semiconductor device that has a plurality of power supply systems that are separated from each other and are driven by the same voltage during normal operation, and that exchanges signals between first and second circuits that operate in different power supply systems A circuit,
A protection circuit inserted on a signal line through which the signal is transmitted and received,
The protection circuit is two native MOS transistors connected in series and having a negative threshold value, and the gates of the two native MOS transistors are respectively connected to the high-potential power supplies of the first and second circuits. An electrostatic protection circuit, wherein the gate oxide film is connected and formed thicker than a gate oxide film of a MOS transistor constituting the first and second circuits.

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