JP2009260062A - Laminating-type semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminating-type semiconductor device with high-reliability connections between wirings and sidewall wirings, and a method of manufacturing the laminating-type semiconductor device. <P>SOLUTION: The method of manufacturing the laminating-type semiconductor device comprises the steps of: providing plural wirings 12 on each of plural semiconductor chips; providing a wiring junction part 20 with a larger width than a wiring width on an insulator 4 arranged between adjacent semiconductor chips out of the plural semiconductor chips so as to be electrically connected with the plural wirings 12; dividing the plural semiconductor chips into individual pieces to form semiconductor devices so that a side surface of the wiring junction part 20 may be exposed to each side surface of the plural semiconductor chips; laminating the plural semiconductor devices; and providing a sidewall wiring 18 extending through the side surfaces of the plural laminated semiconductor devices for interconnection of the wiring junction part 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a stacked semiconductor device formed by stacking a plurality of semiconductor devices and a manufacturing method thereof.

  Semiconductor devices are required to have large capacity and high density. In order to meet this demand, a stacked semiconductor device capable of mounting a plurality of semiconductor devices at a high density and reducing the mounting area has been developed.

  Patent Document 1 discloses a stacked semiconductor device in which semiconductor devices having wirings provided on the upper surface are stacked and connecting means for connecting the wirings of the respective semiconductor devices are provided on the side surfaces.

  Patent Document 2 discloses a stacked semiconductor device in which semiconductor devices with electrodes exposed on the side surfaces are stacked, and wirings for connecting the electrodes of the respective semiconductor devices are provided on the side surfaces.

Patent Document 3 discloses a stacked semiconductor device in which semiconductor devices having bonding wires exposed on the side surfaces are stacked and bonding wires exposed from the respective semiconductor devices are connected.
Japanese Patent Laid-Open No. 2003-243606 JP 2002-76167 A JP 2002-50737 A

  In the conventional manufacturing method, since the contact area between the wiring provided in the semiconductor device and the side wall wiring provided on the side surface of the stacked semiconductor device is small, the reliability of the connection between the wiring and the side wall wiring may be reduced. there were.

  In view of the above problems, an object of the present invention is to provide a stacked semiconductor device having a high connection reliability between a wiring and a sidewall wiring and a method for manufacturing the same.

  The present invention includes a step of providing a plurality of wirings on each of a plurality of semiconductor chips, and the plurality of wirings on an insulator disposed between adjacent semiconductor chips among the plurality of semiconductor chips. A step of providing a wiring connecting portion having a width larger than the width of the wiring so that the side surface of the wiring connecting portion is exposed on each side surface of the plurality of semiconductor chips. Side surfaces of the plurality of stacked semiconductor devices such that a plurality of semiconductor chips are singulated to form a semiconductor device, a plurality of the semiconductor devices are stacked, and the wiring connecting portions are connected to each other. A method of manufacturing a stacked semiconductor device, comprising: providing a side wall wiring extending to the substrate. According to the present invention, it is possible to improve the reliability of the connection between the wiring and the sidewall wiring.

  In the above-described configuration, the step of providing the sidewall wiring includes a side surface of the plurality of stacked semiconductor devices so as to be connected to each of the wiring connection portions exposed on each side surface of the plurality of stacked semiconductor devices. Providing the metal film in the stacking direction so that a cutting line is located between adjacent wirings among the plurality of wirings provided in each of the stacked semiconductor devices. And a first cutting step for cutting. According to this configuration, since the contact area between the wiring connecting portion and the sidewall wiring can be increased, the reliability of the connection between the wiring and the sidewall wiring can be improved.

  The said structure WHEREIN: The process of providing the said wiring connection part can be made into the process of providing the said wiring connection part which has a width | variety larger than the width | variety of the area | region which contacts the said wiring connection part of the said wiring. According to this configuration, since the contact area between the wiring connecting portion and the sidewall wiring can be increased, the reliability of the connection between the wiring and the sidewall wiring can be improved.

  In the above configuration, the step of providing the wiring connecting portion is a step of providing the strip-shaped wiring connecting portion so that all the plurality of wirings provided in each of the plurality of semiconductor devices are connected to each other. Can do. According to this configuration, since the contact area between the wiring connecting portion and the sidewall wiring can be increased, the reliability of the connection between the wiring and the sidewall wiring can be improved.

  In the above configuration, the step of providing the wiring connecting portion includes the step of providing the wiring connecting portion so that the mutually adjacent wirings provided in the adjacent semiconductor devices are connected and the adjacent wiring connecting portions are separated from each other. It can be. According to this configuration, the semiconductor device can be tested even before the sidewall wiring is formed.

  The said structure WHEREIN: The said 1st cutting process can be made into the process of cut | disconnecting the said metal film and the said wiring connection part. According to this configuration, the sidewall wiring can be formed in a single process.

  In the above configuration, after the step of laminating the plurality of separated semiconductor devices, and before the step of providing the metal film, the wiring connection is performed by a cutting line that overlaps the cutting line of the first cutting step. It can be set as the structure which has a 2nd cutting process which cut | disconnects a part in a lamination direction. According to this configuration, since the contact area between the wiring connecting portion and the side wall wiring can be increased, the reliability of the connection between the wiring and the side wall wiring can be further improved.

  In the above configuration, the step of providing the plurality of wirings may include a step of connecting a part of the plurality of wirings to a test pad.

  In the above structure, after the step of providing the sidewall wiring, a step of mounting the plurality of stacked semiconductor devices on the substrate by connecting the sidewall wiring and the substrate using solder. be able to.

  The present invention provides a plurality of stacked semiconductor devices each having a plurality of wirings and connected to each of the plurality of wirings and having a width larger than the width of the wirings. A plurality of wiring connecting portions provided on each side surface of the semiconductor device, and sidewall wiring extending on the side surfaces of the plurality of stacked semiconductor devices so that the wiring connecting portions are connected to each other. The stacked semiconductor device is characterized in that: According to the present invention, it is possible to improve the reliability of the connection between the wiring and the sidewall wiring.

  According to the present invention, it is possible to provide a stacked semiconductor device having a high connection reliability between a wiring and a sidewall wiring and a method for manufacturing the same.

  As a comparative example, the prior art will be described with reference to the drawings.

  FIG. 1 is a flowchart showing a part of the manufacturing method of the stacked semiconductor device 100 according to the comparative example. 2 (a) to 2 (e) are side views showing the manufacturing method, and FIGS. 3 (a) to 4 (c) are perspective views.

  As shown in FIGS. 2A and 2B, a pad 6 made of a metal such as Al is provided on the surface of a semiconductor chip 9 made of, for example, silicon. The plurality of semiconductor chips 9 are attached to the tape 2 so that the surface on which the pads 6 are provided is in contact.

  As shown in FIG. 2C, the surface of the semiconductor chip 9 where the pads 6 are not provided and the space between the semiconductor chips 9 are sealed with an insulator 4 made of a resin such as epoxy.

  As shown in FIG. 2D, the insulator 4 is ground, and the height from the tape 2 to the insulator 4 is reduced.

  As shown in FIG. 2E, the tape 2 is replaced with the opposite surface of the semiconductor chip 9 to expose the pads 6. Thereby, a plurality of semiconductor devices 10 are formed. Subsequent steps will be described with reference to the flowchart of FIG.

  Fig.3 (a) is a perspective view which shows the state which reversed the upper and lower sides of FIG.2 (e). Pads 6 are exposed on the upper surface of each semiconductor device 10, and the insulator 4 is located between adjacent semiconductor devices 10. The distance L1 between the semiconductor devices 10 is, for example, several tens of μm.

  As shown in FIG. 3B, in step S10 of FIG. 1, an insulating film 8 made of polyimide, for example, having an opening 8a that exposes the pad 6 on the semiconductor device 10 and the insulator 4 is formed. Form.

  As shown in FIG. 3C, in step S11, a plurality of wirings 12 made of a metal such as Cu are provided on the insulating film 8 by, for example, plating so as to fill the opening 8a. Adjacent semiconductor devices 10 are connected by wiring 12. The thickness of the wiring 12 is several μm, and the pitch L2 between the wirings 12 is, for example, 70 μm.

  As shown in FIG. 3D, in step S12, the blades 14 are used to cut the insulator 4 located between the adjacent semiconductor devices 10 and separate the semiconductor devices 10 into individual pieces.

  As shown in FIG. 4A, in step S13, a plurality of separated semiconductor devices 10 are stacked. This is referred to as a stacked semiconductor device 100. At this time, the insulating film 8 is sandwiched between the upper and lower semiconductor chips 9, and the plurality of wirings 12 are stacked so as to be exposed on the same side surface of the stacked semiconductor device 100.

  As shown in FIG. 4B, in step S14, for example, a metal made of Cu / Ni so as to be connected to each of the plurality of wirings 12 exposed on each side surface of the plurality of stacked semiconductor devices 10. The film 16 is formed on the side surface of the stacked semiconductor device 100 by, for example, electroless plating. The combined width T1 of the insulator 4 and the metal film 16 of the semiconductor device 10 is, for example, several tens of μm, and the width T2 of the metal film 16 is, for example, 10 μm or less (see FIG. 6).

  As shown in FIG. 4C, in step S15, a metal is used so that a cutting line is positioned between the adjacent wirings 12 among the plurality of wirings 12 provided in the semiconductor device 10 using, for example, a laser. The film 16 is cut in the stacking direction. Thereby, the sidewall wiring 18 is formed. At this time, you may cut | disconnect using a braid | blade. Further, the sidewall wiring 18 may be formed by an ink jet method.

  Through the above steps, the stacked semiconductor device 100 in which a plurality of semiconductor devices 10 are stacked and the corresponding pads 6 are connected via the wiring 12 and the sidewall wiring 18 is completed.

  FIG. 5 is a side view showing a mounting example of the stacked semiconductor device 100 according to the comparative example. As shown in FIG. 5, the stacked semiconductor device 100 is installed on the substrate 3, and the sidewall wiring 18 and a pad (not shown) on the substrate 3 are connected using the solder 5, thereby 100 is mounted on the substrate 3. In FIG. 5, the insulator 4, the insulating film 8, and the semiconductor chip 9 are collectively shown as a semiconductor device 10 for simplification.

  FIG. 6 is a top view of the stacked semiconductor device 100. As shown in FIG. 6, the width of the region where the wiring 12 and the sidewall wiring 18 are in contact is W1. Therefore, in the comparative example, the contact area between the wiring 12 and the sidewall wiring 18 is small, and the connection reliability between the wiring 12 and the sidewall wiring 18 is low. For example, when the side wall wiring 18 is peeled off at the cut surface 13 or the like, there is a problem that the wiring 12 and the side wall wiring 18 are disconnected.

  Embodiments for solving the above problems will be described below with reference to the drawings.

  FIG. 7 is a flowchart showing a method of manufacturing the stacked semiconductor device 110 according to the first embodiment, and FIGS. 8A to 9C are perspective views.

  In Example 1 as well, the steps up to the state shown in FIG.

  As shown in FIG. 8A, in step S21 of FIG. 7, the wiring 12 is provided on the insulating film 8 by, for example, plating a metal such as Cu so as to fill the opening 8a. Furthermore, on the insulating film 8 and on the insulator 4 located between the adjacent semiconductor devices 10, a strip-like shape made of a metal such as Cu is connected so that all of the plurality of wirings 12 are connected to each other. The wiring connection part 20 is provided. That is, the wiring connection portion 20 having a width W0 larger than the width W1 of the region in contact with the wiring connection portion 20 of the wiring 4 is provided. At this time, in order to simplify the process and improve the bonding strength between the wiring 12 and the wiring connecting portion 20, the wiring 12 and the wiring connecting portion 20 are preferably provided from the same metal layer.

  As illustrated in FIG. 8B, in step S <b> 22, the semiconductor device 10 is separated into pieces using the blade 14 so that the side surfaces of the wiring connecting portions 20 are exposed on the respective side surfaces of the semiconductor device 10.

  As shown in FIG. 9A, in step S23, a plurality of separated semiconductor devices 10 are stacked to form a stacked semiconductor device 110.

  As shown in FIG. 9B, in step S24, on the side surface of the stacked semiconductor device 110 so as to be connected to each of the wiring connecting portions 20 exposed on each side surface of the plurality of stacked semiconductor devices 10. For example, a metal film 16 made of Cu / Ni is provided.

  As shown in FIG. 9C, in step S25, the metal film 16 and the wiring are arranged such that a cutting line is located between the adjacent wirings 12 among the plurality of wirings 12 provided in each of the semiconductor devices 10. The connection part 20 is cut | disconnected in the lamination direction (1st cutting process). Thereby, the sidewall wiring 18 is formed. Through the above steps, the stacked semiconductor device 110 according to the first embodiment is completed.

  FIG. 10 is a top view of the stacked semiconductor device 110. As shown in FIG. 10, according to the first embodiment, the width of the region where the wiring connecting portion 20 and the sidewall wiring 18 are in contact is W2. This is larger than the width W1 in the comparative example. That is, the contact area between the wiring connecting portion 20 and the sidewall wiring 18 can be increased. For this reason, for example, even if the separation of the sidewall wiring 18 occurs at the cut surface 13 in the step of forming the sidewall wiring 18, the connection between the wiring connecting portion 20 and the sidewall wiring 18 is ensured. Further, as described above, the wiring 12 and the wiring connecting portion 20 are made of the same metal layer. Therefore, according to the first embodiment, the reliability of the connection between the wiring 12 and the sidewall wiring 18 is increased.

  The combined width T1 of the insulator 4 and the metal film 16 is, for example, several tens of μm. Further, the width T3 of the wiring connecting portion 20 is, for example, 10 μm or more. In order to form the sidewall wiring 18, it is preferable that the depth of the cutting line 11 is equal to or greater than the width T <b> 3 of the wiring connecting portion 20 so that the wiring connecting portion 20 is cut. Further, as described above, the cutting line 11 is located between the adjacent wirings 12.

  FIG. 11A is a perspective view showing an example in which the connected blades 22 are used in the step of forming the sidewall wiring 18, and FIG. 11B is a top view thereof.

  As shown in FIGS. 11A and 11B, the side wall wiring 18 can be formed by a single process by cutting the metal film 16 using the connected blades 22. The pitch L2 between the wirings 12 is 70 μm, for example, and is connected by the wiring connecting part 20. For this reason, for example, even when the position of the blade 22 is shifted by about 10 μm in the left-right direction in the drawing, the connection between the wiring 12 and the side wall wiring 18 is maintained, and no short circuit between adjacent wirings 12 occurs. Although it is possible to cut the metal film 16 using a laser, it is preferable to use a connected blade 22 because alignment is difficult.

  FIG. 12 is a top view showing a modification of the first embodiment.

  As shown in FIG. 12, some of the wirings 12 may be connected to a test pad 24 having a diameter R of 100 μm, for example. After the sidewall wiring 18 is formed, the stacked semiconductor device can be tested by applying a probe to the test pad 24. In FIG. 12, the wirings 12a connected to the test pads 24 and the wirings 12b that are not connected are alternately arranged, but this is not restrictive. For example, two wirings 12b may be disposed between the wirings 12a.

  The second embodiment is an example in which the shape of the wiring connecting portion 20 is changed. The flow of the manufacturing method of the stacked semiconductor device 120 according to the second embodiment is the same as the flowchart shown in FIG. 13A is a top view of the stacked semiconductor device 120 after stacking in step S23, and FIG. 13B is a top view of the stacked semiconductor device 120 after sidewall wiring formation in step S25.

  As shown in FIG. 13 (a), a plurality of wirings 12 provided in adjacent semiconductor devices 10 facing each other are connected, and adjacent wirings 12 provided in the same semiconductor device 10 are not connected. A wiring connecting portion 20a is provided. That is, the wiring connecting portions are provided so that the adjacent wiring connecting portions 20a connected to the mutually opposing wirings 12 provided in the adjacent semiconductor device 10 are separated from each other. The width W3 of the wiring connecting portion 20a is larger than the width W1 of the wiring 12 (equal to the width W1 in FIG. 8A).

  As shown in FIG. 13B, as in the first embodiment, among the plurality of wirings 12 provided in each of the semiconductor devices 10, the metal film is arranged so that the cutting line is located between the adjacent wirings 12. 16 and the wiring connecting portion 20a are cut in the stacking direction. Thereby, the sidewall wiring 18 is formed.

  According to the second embodiment, the width W4 of the region where the wiring connecting portion 20a and the sidewall wiring 18 are in contact is larger than the width W1 in the conventional example. That is, as in the first embodiment, for example, even if the side wall wiring 18 is peeled off at the cut surface 23, the connection between the wiring connecting portion 20a and the side wall wiring 18 is ensured. Therefore, the reliability of connection between the wiring 12 and the sidewall wiring 18 is improved.

  Further, as shown in FIG. 13 (a), since the wiring connecting portions 20a adjacent to each other are separated from each other, a probe is applied to each of the wiring connecting portions 20a before the sidewall wiring 18 is formed. Equipment tests can be performed.

  Example 3 is an example in which a step (second cutting step) of cutting the wiring connecting portion 20 is performed after the step of stacking the semiconductor devices 10 and before the step of providing the metal film 16. FIG. 14 is a flowchart illustrating the method for manufacturing the stacked semiconductor device 130 according to the third embodiment. FIG. 15A to FIG. 16B are top views. Steps S20 to S23 in FIG. 14 are the same as those in FIG.

  As shown in FIG. 15A, in step S <b> 34 of FIG. 14, for example, the above-described blade 22 is used to cut the wiring connecting portion 20 along the cutting line 25 in the stacking direction of the semiconductor device 10. This process is performed after the stacking process (step S23) and before the metal film forming process (step S35).

  As shown in FIG. 15B, in step S <b> 35, the metal film 16 is provided on the side surfaces of the stacked semiconductor devices 10. At this time, since the step of cutting the wiring connecting portion 20 is performed first, the metal film 16 is also formed on the cut surface 26 of the wiring connecting portion 20.

  As shown in FIG. 15C, the blade 22 is again brought into contact with the cutting line 25 to fix the position of the blade 22. Thereby, the cutting line in the process of cutting the wiring connection part 20 and the cutting line in the process of forming the sidewall wiring 18 (first cutting process) can be overlapped.

  As shown in FIG. 16A, in step S <b> 36, the metal film 16 is cut in the stacking direction of the semiconductor device 10 along the cutting line that overlaps the cutting line 25, thereby forming the sidewall wiring 18.

  As shown in FIG. 16B, the stacked semiconductor device 130 according to the third embodiment is completed through the above steps.

  As shown in FIG. 16B, according to the third embodiment, since the side wall wiring 18 is also formed on the cut surface 26, the contact area of the region where the wiring connecting portion 20 and the side wall wiring 18 are in contact is set. Compared with the case of Example 1 and Example 2, since it can be made larger, the reliability of connection of the wiring 12 and the side wall wiring 18 becomes higher.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

FIG. 1 is a flowchart showing a method for manufacturing a stacked semiconductor device 100 according to a comparative example. FIG. 2A to FIG. 2E are side views showing a method for manufacturing the stacked semiconductor device 100 according to the comparative example. FIG. 3A to FIG. 3D are perspective views showing a method for manufacturing the stacked semiconductor device 100 according to the comparative example. FIG. 4A to FIG. 4C are perspective views illustrating a method for manufacturing the stacked semiconductor device 100 according to the comparative example. FIG. 5 is a side view of the stacked semiconductor device 100 according to the comparative example. FIG. 6 is a top view of the stacked semiconductor device 100 according to the comparative example. FIG. 7 is a flowchart illustrating the method for manufacturing the stacked semiconductor device 110 according to the first embodiment. FIG. 8A to FIG. 8B are perspective views illustrating the method for manufacturing the stacked semiconductor device 110 according to the first embodiment. FIG. 9A to FIG. 9C are perspective views illustrating the method for manufacturing the stacked semiconductor device 110 according to the first embodiment. FIG. 10 is a top view of the stacked semiconductor device 110. FIG. 11A is a perspective view showing an example in which the blades 22 connected in the first embodiment are used, and FIG. 11B is a top view thereof. FIG. 12 is a top view showing a modification of the first embodiment. FIGS. 13A and 13B are top views illustrating the method for manufacturing the stacked semiconductor device 120 according to the second embodiment. FIG. 14 is a flowchart illustrating the method for manufacturing the stacked semiconductor device 130 according to the third embodiment. FIG. 15A to FIG. 15C are top views illustrating the method for manufacturing the stacked semiconductor device 130 according to the third embodiment. FIG. 16A to FIG. 16B are top views illustrating the method for manufacturing the stacked semiconductor device 130 according to the third embodiment.

Explanation of symbols

Insulator 4
Pad 6
Insulating film 8
Semiconductor chip 9
Semiconductor device 10
Cutting line 11, 25
Wiring 12
Blade 14, 22
Metal film 16
Side wall wiring 18
Wiring connecting part 20, 20a
Stacked semiconductor device 100, 110, 120, 130

Claims (10)

Providing a plurality of wirings on each of the plurality of semiconductor chips;
Wiring connection having a width larger than the width of the wiring so as to be electrically connected to the plurality of wirings on an insulator disposed between adjacent semiconductor chips among the plurality of semiconductor chips. Providing a part;
Dividing the plurality of semiconductor chips into pieces so that the side surfaces of the wiring connecting portions are exposed on the side surfaces of the plurality of semiconductor chips, and forming a semiconductor device;
Laminating a plurality of the semiconductor devices;
Providing a sidewall wiring extending on a side surface of the plurality of stacked semiconductor devices so that the wiring connecting portions are connected to each other. In the step of providing the sidewall wiring, a metal film is formed on the side surfaces of the plurality of stacked semiconductor devices so as to be connected to each of the wiring connection portions exposed on the side surfaces of the plurality of stacked semiconductor devices. Providing, and
A first cutting step of cutting the metal film in the stacking direction so that a cutting line is positioned between adjacent wirings among the plurality of wirings provided in each of the stacked semiconductor devices; The method of manufacturing a stacked semiconductor device according to claim 1, comprising:   3. The laminate according to claim 1, wherein the step of providing the wiring connection portion is a step of providing the wiring connection portion having a width larger than a width of a region of the wiring that contacts the wiring connection portion. Type semiconductor device manufacturing method.   The step of providing the wiring connecting portion is a step of providing the strip-shaped wiring connecting portion so that all the plurality of wirings provided in each of the plurality of semiconductor chips are connected to each other. The method for manufacturing a stacked semiconductor device according to claim 1.   The step of providing the wiring connection portion is a step of providing the wiring connection portion so that the wiring connection portions adjacent to each other connected to the mutually opposing wirings provided in the adjacent semiconductor chips are separated from each other. The method for manufacturing a stacked semiconductor device according to claim 1, wherein the method is a manufacturing method of a stacked semiconductor device.   6. The method of manufacturing a stacked semiconductor device according to claim 2, wherein the first cutting step is a step of cutting the metal film and the wiring connecting portion.   After the step of laminating the plurality of semiconductor devices, and before the step of providing the metal film, the wiring connecting portion is cut in the stacking direction by a cutting line that overlaps the cutting line of the first cutting step. 6. The method for manufacturing a stacked semiconductor device according to claim 2, further comprising two cutting steps.   The method of manufacturing a stacked semiconductor device according to claim 1, wherein the step of providing the plurality of wirings includes a step of connecting a part of the plurality of wirings to a test pad.   The step of mounting the plurality of stacked semiconductor devices on the substrate by connecting the sidewall wiring and the substrate using solder after the step of providing the sidewall wiring is provided. 1. A method for manufacturing a stacked semiconductor device according to claim 1. A plurality of stacked semiconductor devices each having a plurality of wirings; and
A plurality of wiring connecting portions connected to each of the plurality of wirings, having a width larger than the width of the wirings, and provided on each side surface of the stacked semiconductor devices;
A stacked semiconductor device comprising: a sidewall wiring extending to a side surface of the plurality of stacked semiconductor devices so that the wiring connecting portions are connected to each other.

Images