JP2009258789A - Backup device and semiconductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a backup device for effectively performing the backup of necessary data stored in a storage device even when power supply is interrupted. <P>SOLUTION: A backup device 20 is provided with: a backup power supply line L10 installed separately from power supply lines L1 and L2 which supply a power source from an auxiliary power source 2b to non-backup parts P11 and P21 which does not need to perform the backup of a memory 11 or a register 12, and configured to supply a power source from the auxiliary power source 2b to backup parts P12 and P22 which need to perform backup; a power source 21 for holding for performing the backup of data stored in the backup parts P12 and P22; and a switching circuit 22 for monitoring the backup power supply line L10, and for, when power supply from the auxiliary power source 2b is interrupted, switching power supply to the backup parts P12 and P22 to power supply from the power source 21 for holding. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a backup device that backs up data stored in a storage device and a semiconductor test apparatus including the device.

  A semiconductor test apparatus applies a test signal to a semiconductor device to be tested (hereinafter referred to as a DUT (Device Under Test)) and compares the signal obtained from the DUT with a predetermined expected value to test the DUT. The test apparatus is roughly divided into a test apparatus body having a power source and the like and a test head on which the DUT is placed. Patent Document 1 below discloses a configuration in which a probe card, a performance board, and the like are provided on a test head, and electric power is supplied to the test card from the power source of the test apparatus main body.

  The probe card is a jig used for testing a semiconductor device formed on a semiconductor wafer in a semiconductor wafer inspection process. The performance board is a board that is electrically connected to the test head via a contact pin (pogo pin) provided on the top of the test head and transmits various signals transmitted from the test head to a probe card or the like. It is.

In Patent Document 2 below, a non-volatile memory that stores data indicating a delay time for each pin of the DUT in the connection board, and a memory for connecting the test apparatus main body and the DUT are provided. There has been disclosed a technique for providing a flag register to which a flag indicating that access has been made is written and performing skew adjustment using data stored in a memory.
JP 2007-322372 A Japanese Patent No. 2831780

  By the way, in recent years, semiconductor devices have become highly functional and high-speed, and a circuit having a function that cannot be covered only by functions provided in a test apparatus main body or a test head, such as a probe card as described in Patent Document 2 above. Opportunities to conduct tests after adding to are increasing. Here, the probe card or the like is frequently replaced according to the type of DUT, but it is necessary to replace the probe card after the power supply to the probe card or the like is stopped in order to prevent destruction of the circuit at the time of replacement. . Further, when testing (debugging) a test program, it may be performed in a state in which only power supply such as a probe card is stopped. For this reason, the main body of the test apparatus is provided with an auxiliary power source called “SA power” that can shut off and supply power according to the user's request, in addition to the main power source.

  However, a circuit provided in a probe card or the like may be provided with a volatile storage device such as a memory (for example, a dynamic random access memory (DRAM)) or a register, and supplies power to the probe card or the like. If it stops, the data stored in these will be erased. For this reason, before the test is started after the replacement of the probe card or the like, it is necessary to store data in these storage devices again, and there is a problem that the test time is increased accordingly.

  Here, if a non-volatile memory is provided as in Patent Document 2 described above, the stored data is retained even if the power supply to the probe card or the like is shut off. However, since non-volatile memories generally have a lower writing speed and reading speed than DRAMs and the like, it is difficult to make all memories non-volatile memories.

  The present invention has been made in view of the above circumstances, and a backup device capable of effectively backing up necessary data stored in a storage device even when power supply is interrupted, and the device. An object of the present invention is to provide a semiconductor test apparatus.

In order to solve the above problem, the backup device according to the present invention does not need to back up the storage device in the backup device (20) that backs up the data stored in the storage device (11, 12). A second part (L1, L2) is provided separately from the first supply path (L1, L2) for supplying power from the power supply device (2b) to the parts (P11, P21), and the storage device needs to be backed up ( P21, P22) a second supply path (L10) for supplying power from the power supply device, a holding power supply (21) for backing up data stored in the second portion of the storage device, The power supply from the power supply device via the second supply path is monitored, and when the power supply is interrupted, the power supply to the second part of the storage device is routed via the second supply path. It is characterized in that it comprises a switching unit (22) for switching the power supply from the holding power source.
According to the present invention, power from the power supply device is supplied to the first part and the second part of the storage device via the first supply path and the second supply path, respectively, but the power supply apparatus via the second supply path. When the power supply from is interrupted, the power supply to the second part of the storage device that needs to be backed up is switched to the power supply from the holding power supply via the second supply path.
In the backup device of the present invention, when the holding power source is a rechargeable power source, and the switching unit is supplying power from the power source device to the second portion of the storage device. The holding power supply is charged using the power supplied from the power supply device.
In the backup device according to the present invention, when the switching unit switches the power supply, the backup unit outputs a signal indicating the fact to the outside.
In the backup device according to the present invention, the storage device includes a volatile memory (31) and a nonvolatile memory (32) in the second portion, and power is supplied from the power supply device to the second portion. When the signal is interrupted, the data stored in the volatile memory is written into the nonvolatile memory.
In the backup device of the present invention, the storage device writes the data stored in the nonvolatile memory to the volatile memory when the power supply from the power supply device to the second part is resumed. It is a feature.
The semiconductor test apparatus of the present invention is electrically connected to the test head and the semiconductor device in the semiconductor test apparatus (1) including the test head (3) on which the semiconductor device (8) to be tested is placed. The backup device according to any one of the above is provided for backing up data stored in a storage device provided on at least one of the jig (7) and the auxiliary substrate (5).

  According to the present invention, the power from the power supply device is supplied to the first part and the second part of the storage device via the first supply path and the second supply path, respectively. When the power supply from the device is cut off, the power supply to the second part of the storage device that needs to be backed up is switched to the power supply from the holding power supply via the second supply path. Even when the supply is interrupted, there is an effect that necessary data stored in the storage device can be effectively backed up.

  Hereinafter, a backup apparatus and a semiconductor test apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an outline of the overall configuration of a semiconductor test apparatus according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor test apparatus 1 according to the present embodiment includes a test apparatus main body 2 and a test head 3, applies a test signal to the DUT 8 mounted on the test head 3, and outputs the test signal from the DUT 8. The DUT 8 is tested by comparing the received signal with a predetermined expected value. FIG. 1 shows a state in which the DUT 8 is disposed above the test head 3. However, when testing a semiconductor device formed on a semiconductor wafer, the test head 3 is rotated to rotate the DUT 8. Is generally arranged below the test head 3.

  The test apparatus body 2 includes a main power supply 2a, an auxiliary power supply 2b (power supply apparatus), a control unit (not shown), and the like, and comprehensively controls the operation of the semiconductor test apparatus 1. Here, the auxiliary power supply 2b supplies power to the performance board 5 and the probe card 7 described later, and can cut off and supply power according to the user's desire. The test head 3 includes a plurality of printed circuit boards (not shown) called pin electronics cards as interfaces with the DUT 8, and applies test signals to the DUT 8 and outputs them from the DUT 8 under the control of the test apparatus body 2. The test signal to be compared is compared with a predetermined expected value. The test apparatus main body 2 and the test head 3 are connected by a cable 4.

  On the test head 3, a performance board 5, a contact ring 6, and a probe card 7 are provided. The performance board 5 is electrically connected to the test head 5 via contact pins provided on the upper part of the test head 3, and transmits various signals transmitted from the test head 5 through the contact ring 6. Is a substrate that transmits a signal from the test head 5 to the test head 5. The contact ring 6 is for electrically connecting the performance board 5 and the probe card 7. The probe card 7 is a jig for making electrical connection with the DUT 8 (a semiconductor device formed on a semiconductor wafer).

  Next, the operation of the semiconductor test apparatus having the above configuration will be briefly described. When testing the DUT 8, first, the DUT 8 is electrically connected to the probe of the probe card 7 by a prober (not shown). When the connection is completed, a test signal is output from the test head 3 to the performance board 5 via the contact pins. The test signal is applied to the DUT 8 via the performance board 5, the contact ring 6, and the probe card 7 in this order. As a result, a signal corresponding to the applied test signal is output from the DUT 8. The signal output from the DUT 8 is input to the test head 3 through the probe card 7, the contact ring 6, and the performance board 5 in order, and is compared with a predetermined expected value to determine the pass / fail of the DUT 8. When the above operation is completed, connection switching of the DUT 8 is performed again by the prober.

  Here, in the test of the DUT 8, the performance board 5 and the probe card 7 are exchanged according to the type of the DUT 8. In other words, the user performs an operation of exchanging with the performance board 5 provided with a circuit necessary for testing the DUT 8. At this time, in order to prevent destruction of a circuit provided in the performance board 5 or the like, the user performs replacement work after stopping the power supply from the auxiliary power supply 2b to the performance board 5 or the like. A circuit provided in the performance board 5 or the like includes a memory and a register for storing various data, but these data are erased when the power supply is stopped. Therefore, the performance board 5 and the like are provided with a backup device that backs up various stored data. Hereinafter, a backup device according to an embodiment of the present invention will be described.

  FIG. 2 is a block diagram showing a main configuration of the backup apparatus according to the embodiment of the present invention. In FIG. 2, the backup device on the performance board 5 will be described as an example, but the backup device on the probe card 7 has the same configuration. As shown in FIG. 5, a memory 11, a register 12, a logic circuit 13, and an analog circuit 14 that store various data are provided on the performance board 5.

  The memory 11 is a volatile memory such as DRAM, and the inside thereof is divided into a non-backup part P11 (first part) that does not need to be backed up and a backup part P12 (second part) that needs to be backed up. Has been. Specifically, the memory 11 includes a plurality of DRAM chips inside, and by setting a DRAM chip that is backed up and a DRAM chip that is not backed up, the first part P11 and the second part P12 described above are set. And is divided.

  Similarly to the memory 11, the register 12 is also volatile, and a non-backup part P21 (first part) that does not need to be backed up inside and a backup part P22 (second part) that needs to be backed up. ). The logic circuit 13 is a digital circuit that provides a function necessary for testing the DUT 8, and the analog circuit 14 is an analog circuit that provides the function. The non-backup unit P11 of the memory 11, the non-backup unit P21 of the register 12, the logic circuit 13, and the analog circuit 14 are supplied with power lines L1 to L4 (the first power lines L1 to L4) supplied with power from the auxiliary power supply 2b included in the test apparatus body 2. 1 supply path) is connected to each other.

  The backup device 20 of the present embodiment only backs up data stored in the memory 11 and the backup units P12 and P22 of the register 12. This can reduce the test time effectively without backing up unnecessary data and backing up the minimum necessary data that can shorten the test time without incurring large scale and significant cost increase. Because. For this reason, the backup device 20 of this embodiment includes a backup power supply line L10 (second supply path), a holding power supply 21, and a switching circuit 22 (switching unit).

  The backup power supply line L10 is connected to the power supply line to which the power from the auxiliary power supply 2b is supplied and the memory 11 and the backup parts P12 and P22 of the register, respectively, and the power supply from the auxiliary power supply 2b or the holding power supply 21. Are supplied to the memory 11 and the backup units P12 and P22 of the register 12, respectively. The holding power supply 21 is a power supply for backing up the backup units P12 and P22 of the memory 11 and the register 12. As the holding power source 21, for example, a chargeable and large-capacity electric double layer capacitor can be used. Here, the capacity of the holding power supply 21 is set to a capacity capable of backing up data stored in the memory 11 and the backup units P12 and P22 of the register 12 for about one hour to several hours.

  The switching circuit 22 monitors the power supply from the auxiliary power supply 2b via the backup power supply line L10, and when the power supply is interrupted, supplies power to the backup units P12 and P22 of the memory 11 and the register 12. The power supply is switched from the holding power supply 21 via the backup power supply line L10. When such switching is performed, the switching circuit 22 outputs a signal indicating that fact and notifies a control unit (not shown) provided in the test apparatus body 2. In addition, the switching circuit 22 uses the power supplied from the auxiliary power supply 2b when the power is supplied from the auxiliary power supply 2b to the memory 11 and the backup units P12 and P22 of the register 12. Charge the battery.

  In the above configuration, while the DUT 8 is being tested, power is supplied from the auxiliary power source 2b provided in the test apparatus body 2 to the performance board 5 and the like. As a result, power is supplied to the non-backup units P11 and P21, the logic circuit 13, and the analog circuit 14 of the memory 11 and the register 12 via the power supply lines L1 to L4. At this time, the switching circuit 22 monitors the power supply from the auxiliary power supply 2b to the backup power supply line L10. Therefore, the power from the auxiliary power supply 2b is also supplied to the memory 11 and the backup units P12 and P22 of the register 12 via the backup power supply line L10, and the holding power supply 21 is also charged.

  On the other hand, when the user performs a predetermined operation, the power supply from the auxiliary power supply 2b to the performance board 5 is cut off. As a result, the power supply to the non-backup units P11 and P21, the logic circuit 13 and the analog circuit 14 of the memory 11 and the register 12 via the power lines L1 to L4 is cut off, and the non-backup units P11 and P11 of the memory 11 and the register 12 are cut off. The data stored in P21 is deleted.

  At this time, the switching circuit 22 monitors that the power supply from the auxiliary power supply 2b to the backup power supply line L10 is cut off, and thereby the power supply to the backup units P12 and P22 of the memory 11 and the register 12 is backed up. The power supply is switched from the holding power supply 21 via the power supply line L10. By such switching, data stored in the backup units P12 and P22 of the memory 11 and the register 12 is backed up without being erased. When the above switching is performed, the switching circuit 22 outputs a signal indicating that the switching has been performed and notifies a control unit (not shown) provided in the test apparatus body 2.

  Next, when the user performs a predetermined operation, power supply from the auxiliary power supply 2b to the performance board 5 is resumed. As a result, power is supplied to the non-backup units P11 and P21, the logic circuit 13, and the analog circuit 14 of the memory 11 and the register 12 via the power supply lines L1 to L4. Further, when the power supply is resumed, the switching circuit 22 monitors the power supply from the auxiliary power supply 2b to the backup power supply line L10 again. As a result, the switching circuit 22 supplies power from the auxiliary power supply 2b via the backup power supply line L10 to the backup units P12 and P22 of the memory 11 and the register 12 again, and also charges the holding power supply 21.

  When power supply from the auxiliary power supply 2b to the performance board 5 is resumed, the control unit (not shown) of the test apparatus body 2 receives a signal from the switching circuit 22 (a signal indicating that the power supply has been switched). Check for presence. When the signal is present, the control unit (not shown) of the test apparatus main body 2 can know that necessary data is backed up by the backup device 20 and no initial setting is required.

  As described above, in the present embodiment, the power supply from the auxiliary power supply 2b via the backup power supply line L10 connected to the backup units P12 and P22 of the memory 11 and the register 12 is monitored, and this power supply is cut off. In this case, the power supply to the backup units P12 and P22 of the memory 11 and the register 12 is switched to the power supply from the holding power supply 21 via the backup power supply line L10. For this reason, even if the power supply is interrupted, necessary data stored in the backup units P12 and P22 of the memory 11 and the register 12 can be effectively backed up.

  Thereby, it is not necessary to store the erased data in the memory 11 and the register 12 again, and the time required to start the test of the DUT 8 can be shortened. As a result, the time required for the test of the DUT 8 can be shortened. In the present embodiment, since not all of the data stored in the memory 11 and the register 12 but the minimum necessary data stored in the backup units P12 and P22 are backed up, the scale is increased and the cost is greatly increased. It will not cause any increase.

  Next, a modification of this embodiment will be described. FIG. 3 is a diagram showing a modification of one embodiment of the present invention. As shown in FIG. 3, in the present modification, the memory 11 includes a volatile memory 31 and a nonvolatile memory 32 in the backup unit P12. The volatile memory 31 is a volatile memory such as a DRAM and stores various data necessary for the test of the DUT 8. The non-volatile memory 32 is a memory that stores data stored in the volatile memory 31 when power supply from the auxiliary power supply 2b is interrupted. The capacity of the nonvolatile memory 32 is set to be greater than or equal to the capacity of the volatile memory 31. In FIG. 3, a controller that controls reading and writing of data with respect to the volatile memory 21 and the nonvolatile memory 32 is omitted.

  In the above configuration, while the DUT 8 is being tested, the power from the auxiliary power supply 2b is supplied to the backup unit P12 of the memory 11 via the backup power supply line L10, as in the first embodiment described above. Is done. Further, when the power supply from the auxiliary power supply 2b to the performance board 5 is cut off by the user performing a predetermined operation, the power supply from the holding power supply 21 to the backup unit P12 of the memory 11 is switched by the switching circuit 22. Supply is made. When the above switching is performed, the data stored in the volatile memory 31 is written into the nonvolatile memory 32. As a result, the data stored in the volatile memory 31 is backed up.

  Next, when power supply from the auxiliary power supply 2b to the performance board 5 is resumed by performing a predetermined operation by the user, the power supply from the auxiliary power supply 2b is again returned to the backup unit P12 of the memory 11 by switching the switching circuit 22. To be supplied. Then, the data stored in the nonvolatile memory 32 is written into the volatile memory 31, and various data necessary for the test of the DUT 8 are set in the volatile memory 31.

  As described above, in the present modification, when the power supply from the auxiliary power supply 2b is interrupted, the power supply to the backup unit P12 of the memory 11 is made via the backup power supply line L10 as in the above-described embodiment. The power supply from the holding power supply 21 is switched to, but when the switching is performed, the data stored in the volatile memory 31 is written to the nonvolatile memory 32. For this reason, in this modification, the backup unit P12 of the memory 11 only needs to be backed up until the data stored in the volatile memory 31 is completely written to the nonvolatile memory 32, and the capacity of the holding power supply 21 is increased. Can be reduced.

  Further, in this modification, when the power supply from the auxiliary power source 2 b is resumed, the data in the nonvolatile memory 32 is automatically written back to the volatile memory 31. For this reason, it is not necessary to transfer the data to be written to the volatile memory 31 from the test apparatus body 2 to the test head 3 and write it, so that the time required for the test of the DUT 8 does not increase. In the above modification, the configuration in which the volatile memory 31 and the nonvolatile memory 32 are provided in the backup unit P12 of the memory 11 has been described. However, the backup unit P22 of the register 12 can also have the same configuration. .

  The backup apparatus and the semiconductor test apparatus according to the embodiment of the present invention have been described above. However, the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the above embodiment, the backup apparatus provided in the semiconductor test apparatus has been described as an example. However, the backup apparatus of the present invention is applicable to any apparatus that requires backup of a memory or a register other than the semiconductor test apparatus. can do.

It is a figure showing the outline of the whole composition of the semiconductor test equipment by one embodiment of the present invention. It is a block diagram which shows the principal part structure of the backup apparatus by one Embodiment of this invention. It is a figure which shows the modification of one Embodiment of this invention.

Explanation of symbols

1 Semiconductor Test Equipment 2b Auxiliary Power Supply 3 Test Head 8 DUT
5 Performance Board 7 Probe Card 11 Memory 12 Register 20 Backup Device 21 Holding Power Supply 22 Switching Circuit 31 Volatile Memory 32 Nonvolatile Memory L1, L2 Power Supply Line L10 Backup Power Supply Line P11, P21 Non-Backup Part P12, P22 Backup Part

Claims (6)

In a backup device that backs up data stored in a storage device,
A first supply path that supplies power from a power supply device to the first portion that does not require backup of the storage device is provided separately from the second portion that requires backup of the storage device. A second supply path for supplying power from the power supply device;
A holding power source for backing up data stored in the second portion of the storage device;
The power supply from the power supply device via the second supply path is monitored, and when the power supply is interrupted, the power supply to the second part of the storage device is performed via the second supply path. And a switching unit that switches to power supply from the holding power supply. The holding power source is a rechargeable power source,
When the power supply from the power supply device to the second part of the storage device is being performed, the switching unit charges the holding power supply using the power supplied from the power supply device. The backup device according to claim 1, wherein   3. The backup device according to claim 1, wherein when the power supply is switched, the switching unit outputs a signal indicating the fact to the outside. 4. The storage device includes a volatile memory and a nonvolatile memory in the second portion,
4. The data stored in the volatile memory is written into the nonvolatile memory when power supply from the power supply device to the second portion is interrupted. 5. The backup device according to one item. The backup device according to claim 4, wherein the storage device writes data stored in the nonvolatile memory to the volatile memory when power supply from the power supply device to the second portion is resumed. apparatus. In a semiconductor test apparatus including a test head on which a semiconductor device to be tested is placed,
6. The data stored in a storage device provided in at least one of a jig electrically connected to the test head and the semiconductor device and an auxiliary substrate is backed up. 6. A semiconductor test apparatus comprising a backup apparatus.

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