JP2009253441A - Image processor, and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor which performs high speed processing without deteriorating data transfer efficiency even when data is transferred by an optional endian from a plurality of CPUs etc., and to provide an image forming apparatus. <P>SOLUTION: The image processor includes: an external interface part 11 for performing connection and communication with the CPUs 2, 3 which are connected via an external bus 1; an endian changeover register part 15 for setting an endian changeover method; a data converting part 12 for converting the data configuration of input data when the endian of the input data differs from an endian in the processor; a register part 14 for storing the data which is transferred by way of an internal bus 13B; and image processing parts 16-18 for performing image processing by using the data stored in the register part 14. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image forming apparatus that have a data conversion device that enables communication even when endian is different depending on CPU-specific specifications, and realize high-speed processing without reducing transfer efficiency. .

  The data bus has a specific specification, and communication between devices such as a CPU and an ASIC is restricted. Therefore, when communicating between a plurality of devices, an interface unit is designed based on a CPU specification designated in advance to cope with the endian of the CPU.

  In addition, when encrypting data from an interface having an arbitrary data width, the bus width of the input data register is controlled based on a preset value of the bus width, and the preset endian value is set. Based on this, a technique has been proposed in which the byte order of input data is controlled and stored in an input data register (see Patent Document 1).

The endian is set by the initial setting operation of the CPU when the power is turned on. When data from an interface having an arbitrary data width is encrypted, the byte order of the CPU on the system side is changed. This reduces the processing burden and speeds up the data transfer process.
JP 2003-263105 A

  However, in Patent Document 1 described above, it is proposed to set the endian of data transferred from the CPU in advance. However, there are a plurality of CPUs on the system, and little endian and big endian are mixed. In this case, since the number of procedures in which each CPU performs communication after switching the endian is increased, efficient communication such as waiting time on software cannot be performed.

  In addition, when the endian is switched to the little endian, if an access is accidentally generated from the big endian CPU, normal communication cannot be performed, which may cause a problem. The same applies to the reverse case.

  The present invention has been made in view of such circumstances, and an image processing apparatus that realizes high-speed processing without lowering transfer efficiency even when transferred in an arbitrary endian from a plurality of CPUs, and the like. An object of the present invention is to provide an image forming apparatus provided with the image processing apparatus.

  An image processing apparatus according to the present invention is connected to a plurality of external CPUs via an external bus configured with an arbitrary bus width, and transmits and receives data to and from each external CPU via the external bus, and An endian for setting an endian switching method for data input from the external interface unit via an internal bus in an image processing apparatus including an image processing unit that performs image processing according to data input through the external interface unit A switching register unit, a data conversion unit that converts input data in order to switch the endian according to a set endian switching method, and a register unit that stores data output by the data conversion unit To do.

  When an image processing apparatus typified by an ASIC (Application Specific Integrated Circuit) is connected to an external CPU via a data bus, there is a case where it cannot be directly connected due to a CPU-specific bus specification. In the present invention, a data conversion unit is provided on the internal bus between the external interface unit and the internal processing block (image processing unit), and endian switching is performed by performing data conversion by the data conversion unit. Therefore, even when data is transferred from a plurality of external CPUs with an arbitrary endian, high-speed processing is realized without reducing transfer efficiency.

  An image processing apparatus according to the present invention is connected to an external CPU via an external bus having an arbitrary bus width, and transmits and receives data to and from the external CPU via the external bus, and the external In an image processing apparatus including an image processing unit that performs image processing according to data input through an interface unit, an endian switching method for data input from the external interface unit via the first and second internal buses The endian switching register unit for setting the endian, the internal CPU connected to the first internal bus, and the first CPU from the external CPU or the internal CPU to switch the endian according to the switching method set by the endian switching register unit. A data conversion unit for converting data input via the internal bus of Over data conversion unit is characterized by comprising a register unit for storing data to be output through the second internal bus.

  In the present invention, a data conversion unit is provided on the internal bus between the external interface unit and the internal processing block (image processing unit), and endian switching is performed by performing data conversion by this data conversion unit. Therefore, even when data is transferred with an arbitrary endian from the external CPU and the internal CPU connected to the internal bus, high-speed processing is realized without reducing the transfer efficiency.

  In the image processing apparatus according to the present invention, when the bus width of the external bus and the bus width of the internal bus are different, a predetermined bit is input to the input data so as to match the bus width of the internal bus. A bit extraction unit for extraction is provided.

  In the present invention, since predetermined bits are extracted from input data so as to match the bus width of the internal bus, even if the internal bus has a data width different from that of the external bus, the transfer efficiency is improved. Realize high-speed processing without degrading.

  An image forming apparatus according to the present invention includes: the image processing apparatus according to any one of the above-described inventions; and an image forming unit that forms an image processed by the image processing apparatus on a sheet. To do.

  In the present invention, since the transfer efficiency of data to the image processing apparatus does not decrease, the overall processing efficiency during image formation can be increased.

  According to the present invention, a data conversion unit is provided on the internal bus between the external interface unit and the internal processing block (image processing unit), and endian switching is performed by performing data conversion by this data conversion unit. Therefore, even when data is transferred from a plurality of external CPUs with an arbitrary endian, high-speed processing can be realized without reducing transfer efficiency.

  Further, according to the present invention, even when data is transferred in an arbitrary endian from the external CPU and the internal CPU connected to the internal bus, high-speed processing can be realized without reducing transfer efficiency. it can.

  Furthermore, according to the present invention, since predetermined bits are extracted from input data so as to match the bus width of the internal bus, even if the internal bus has a data width different from that of the external bus, the transfer efficiency is increased. High-speed processing can be realized without lowering. For example, if the data width of the external bus provided with the external CPU is 32 bits and the data width of the internal bus in the device is 16 bits, the input data cannot be received in the upper 16 bits or the lower 16 bits. However, in the present invention, only an arbitrary bit can be masked in such a case.

  Furthermore, according to the present invention, since the data transfer efficiency to the image processing apparatus does not decrease, the overall processing efficiency at the time of image formation can be increased.

Hereinafter, the present invention will be specifically described with reference to the drawings illustrating embodiments thereof.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a system configuration according to the first embodiment. The image processing apparatus 10A according to the first embodiment is connected to the external interface unit 11 that performs connection and communication with the external bus 1 configured with an arbitrary bus width, and the external interface unit 11 via the internal bus 13A. Data conversion unit 12 that converts the data structure of input data when it is different from the endian in the apparatus 10A, a register unit 14 that stores data transferred via the internal bus 13B, and an endian switching register that sets an endian switching method And image processing units 16 to 18 that perform image processing using data stored in the unit 15 and the register unit 14.

  Examples of the image processing devices executed by the image processing units 16 to 18 include input tone correction, region separation processing, color correction, black generation and under color removal processing, spatial filter processing, output tone correction, tone reproduction processing, and the like. Is mentioned.

  Two CPUs 2 and 3 having different endians are connected to the outside of the image processing apparatus 10 </ b> A via the external bus 1. These CPUs 2 and 3 are configured to communicate with the image processing apparatus 10 </ b> A through the external interface unit 11 and the data conversion unit 12.

  FIG. 2 is an explanatory diagram for explaining the processing contents executed by the data converter 12. First, the endian switching register unit 15 sets conditions for switching little endian or big endian for an arbitrary address signal. For example, the determination can be made with reference to the upper bits of the address to be accessed. When the address accessed by the CPU 2 is 1000h and the address accessed by the CPU 3 is 2000h, the data conversion unit 12 does not convert the data structure if the 12th and 13th bits of the address are “01”. If the 12th and 13th bits are “10”, the data structure is converted when the CPU 3 accesses the data structure. For example, when the input data is “0x1234ABCD”, if there is an access from the CPU 3, the data is converted to “0xCDAB3412”.

  Next, the data configuration is determined from the specific bit of the address signal of the external CPU (CPU 2 and 3) input from the external interface unit 11. After determining the data structure, the data structure is converted from the lower byte if it is little endian and from the upper byte if it is big endian. The converted data is written as necessary parameters in the register unit 14 in the image processing apparatus 10A.

  FIG. 3 is a flowchart showing a procedure of processing executed by the image processing apparatus 10A according to the first embodiment. First, the image processing apparatus 10A confirms the number of externally connected CPUs, and determines whether there are a plurality of externally connected CPUs (external CPUs) (step S11).

  When it is determined that there are a plurality of external CPUs (S11: YES), the image processing apparatus 10A confirms the endian of each CPU and determines whether different endians are mixed (step S12).

  When it is determined that the number of external CPUs is one (S11: NO), or when it is determined that the endian of each CPU is common (S12: NO), the data input through the external interface unit 11 is input to the register unit 14. Write (step S19).

  When it is determined in step S12 that different endians are mixed (S12: YES), the image processing apparatus 10A sets an endian switching method. Specifically, a specific bit on the address signal for determining each CPU and a determination value of the specific bit are set in the endian switching register unit 15 (steps S13 and S14), and the determination is made based on the set specific bit and determination value. The data conversion method when data is input from the CPU is set in the endian switching register unit 15 (step S15).

  Next, the image processing apparatus 10A refers to a specific bit of the address signal issued from the external CPU (step S16), and determines whether or not a data conversion process is necessary (step S17).

  If it is determined that data conversion processing is necessary (S17: YES), the data structure of the input data is converted by the data converter 12 (step S18), and the converted data is written in the register unit 14 (S19). If it is determined that the data conversion process is unnecessary (S17: NO), the data structure of the input data is written into the register unit 14 without being converted (S19).

Embodiment 2. FIG.
In the first embodiment, a system configuration in which a plurality of CPUs are connected to the outside of the image processing apparatus 10A has been described. However, the above-described endian switching is also applied to a system configuration including one or more CPUs inside and outside the apparatus. The method can be applied. In the present embodiment, a system configuration including one CPU inside and outside the apparatus will be described.
The same components as those in the first embodiment will be described with the same reference numerals.

  FIG. 4 is a block diagram showing a system configuration according to the second embodiment. The image processing apparatus 10B according to the second embodiment is connected via the external interface unit 11 that performs connection and communication with the external bus 1 configured with an arbitrary bus width, the CPU 19 that is connected to the internal bus 13A, and the internal bus 13A. A data conversion unit 12 that is connected to the external interface unit 11 and converts the data structure of input data when it is different from the endian in the image processing apparatus 10B; a register unit 14 that stores data transferred via the internal bus 13B; An endian switching register unit 15 that sets an endian switching method, and image processing units 16 to 18 that perform image processing using data stored in the register unit 14 are provided.

  A CPU 19 having a different endian from the CPU 19 inside the apparatus is connected via the external bus 1 to the outside of the image processing apparatus 10B. When the CPU 4 as an external CPU also controls the operation of other devices (for example, a scanner device) including the image processing device 10B, the image processing is initialized when the power is turned on, and the CPU 19 as an internal CPU. The present invention can be applied when detailed control of the individual image processing units 16 to 18 is performed. Examples of the control performed by the CPU 19 include setting of parameters for region separation processing, spatial filter processing, and gradation reproduction processing based on the document type determination result.

  FIG. 5 is an explanatory diagram for explaining the processing contents executed by the data converter 12. First, the endian switching register unit 15 sets conditions for switching little endian or big endian for an arbitrary address signal. The condition setting method is the same as in the first embodiment.

  Next, the data structure is determined based on an address signal from the external CPU 4 input from the external interface unit 11 or a specific bit of the address signal from the CPU 19 arranged on the internal bus 13A. After determining the data structure, the data structure is converted from the lower byte if it is little endian and from the upper byte if it is big endian. The converted data is written as necessary parameters in the register unit 14 in the image processing apparatus 10B.

Embodiment 3 FIG.
In this embodiment, a method for switching endian in a system configuration in which the bus width of the internal bus used in the apparatus is different from the bus width of the external bus will be described.
The same components as those in the first embodiment will be described with the same reference numerals.

  FIG. 6 is a block diagram showing a system configuration according to the third embodiment. The image processing apparatus 10C according to the third embodiment is connected to the external interface unit 11 through the external interface unit 11 and the internal bus 13A that perform connection and communication with the external bus 1 configured with a bus width different from that in the apparatus. The data conversion unit 12 that converts the data structure when it is different from the endian in the image processing apparatus 10C, extracts only an arbitrary bit of the converted data, and outputs it via the bit extraction unit 12A and the internal bus 13B. A register unit 14 for storing the data, an endian switching register unit 15 for setting an endian switching method, a bit mask register unit 20 for setting an arbitrary bit to be masked, and data stored in the register unit 14. Image processing units 16 to 18 that perform processing are provided.

  Two CPUs 5 and 6 having different endians are connected via the external bus 1 to the outside of the image processing apparatus 10C. These CPUs 5 and 6 are configured to communicate with the image processing apparatus 10 </ b> C through the external interface unit 11 and the data conversion unit 12.

  In the case of the above-described configuration, it can be applied when one ASIC is used for another model having a different number of bits.

  FIG. 7 is an explanatory diagram for explaining the processing contents executed by the data converter 12. First, the endian switching register unit 15 sets conditions for switching little endian or big endian for an arbitrary address signal. The condition setting method is the same as in the first embodiment.

  Next, the bit mask register unit 20 sets conditions for masking arbitrary bits with respect to the input data. The bit to be masked is determined, for example, by comparing the number of bits processed by the CPU with the number of bits in the ASIC. In the example of FIG. 7, since the external CPUs 5 and 6 are 32 bits and the image processing apparatus 10C is 16 bits, the bit mask register unit 20 is set to mask 16 bits.

  Then, the bit extracting unit 12A of the data converting unit 12 refers to the 12th and 13th bits of the address accessed by the CPUs 5 and 6, and when the 12th and 13th bits are “01”, the upper 16 bits are masked and “10 ", The lower 16 bits are masked.

  Next, the data configuration and the mask bit are determined from the specific bits of the address signal of the CPU 5 or CPU 6 input from the external interface unit 11.

  After determining the data structure and mask bit, the data structure is converted from the lower bit if it is little endian, and the upper byte if it is big endian, and only valid data that is not masked by the bit extraction unit 12A Is output. The converted data is written as a necessary parameter in the register unit 14 in the image processing apparatus 10C.

  FIG. 8 is a flowchart showing a procedure of processing executed by the image processing apparatus 10C according to the third embodiment. First, the image processing apparatus 10C confirms the number of externally connected CPUs, and determines whether there are a plurality of externally connected CPUs (external CPUs) (step S21).

  When it is determined that there are a plurality of external CPUs (S21: YES), the image processing apparatus 10C confirms the endian of each CPU and determines whether different endians are mixed (step S22).

  When it is determined that the number of external CPUs is one (S21: NO), or when it is determined that the endian of each CPU is common (S22: NO), the data input through the external interface unit is written to the register unit 14. (Step S31).

  When it is determined in step S22 that different endians are mixed (S22: YES), the image processing apparatus 10C sets an endian switching method. Specifically, a specific bit and a determination value of the specific bit on the address signal for determining each CPU are set in the endian switching register unit 15 (steps S23 and S24), and the determination is made based on the set specific bit and determination value. The data conversion method when data is input from the CPU is set in the endian switching register unit 15 (step S25).

  Further, the image processing apparatus 10C sets a bit to be masked for the bit mask register unit 20 (step S26).

  Next, the image processing apparatus 10C refers to a specific bit of the address signal issued from the external CPU (step S27), and performs a bit mask process corresponding to the specific bit (step S28).

  Further, the image processing apparatus 10C determines whether or not data conversion processing is necessary based on the referenced specific bit (step S29), and determines that data conversion processing is necessary (S29: YES). The data structure of the input data is converted (step S30). The data whose data structure has been converted is written to the register unit 14 (S31). If it is determined that the data conversion process is unnecessary (S29: NO), the input data is written in the register unit 14 without the data structure being converted (S31).

  In the third embodiment, the configuration in which the bit extraction unit 12A and the bit mask register unit 20 are added to the system configuration shown in the first embodiment has been described. However, the system configuration shown in the second embodiment is different from the system configuration shown in the second embodiment. You may apply to. In this case, the same effect as in the third embodiment can be obtained.

Embodiment 4 FIG.
Hereinafter, an embodiment in which the image forming apparatus according to the present invention is applied to a digital color copying machine will be described.

  FIG. 9 is a block diagram showing the internal configuration of the digital color copying machine according to the present embodiment. The digital color copier according to the present embodiment optically reads a document and outputs a digital RGB signal (image data), and the image data output by the color image input device 121. A color image processing apparatus 100 that performs image processing as will be described later, a color image output apparatus 122 that forms an image on a sheet based on image data processed by the color image processing apparatus 100, and information to be notified to the user , And an operation panel 123 that accepts operation support by the user. These are connected to each other via the external bus 120.

  The color image input apparatus 121 includes a scanner unit including a device such as a CCD that converts optical information into an electrical signal, an AD conversion unit that converts an analog RGB signal output from the scanner unit into a digital signal, and a digital format. A digital format obtained by optically reading a manuscript, including a shading correction unit that performs processing for removing various distortions generated in the illumination system, imaging system, and imaging system of the color image input device 121 for RGB signals RGB signals are output. Further, the color image input device 121 performs a process of converting color balance adjustment and a signal such as a density signal that can be easily handled by the image processing system employed in the color image processing device 100.

  The color image processing apparatus 100 is connected to the external interface unit 101 via the external interface unit 101 for connecting and communicating with the external bus 120, the CPU 103 connected on the internal bus 102A, and the internal bus 102A. A data conversion unit 104 that converts the data structure of input data when it is different from the endian, a register unit 105 that stores data transferred via the internal bus 102B, and an endian switching register unit 106 that sets the endian switching method. , And an image processing unit 110 that performs image processing using data stored in the register unit 105.

  The image processing unit 110 includes, for example, a document type automatic discrimination unit 111, an input tone correction unit 112, a region separation processing unit 113, a color correction unit 114, a black generation and under color removal unit 115, a spatial filter processing unit 116, and an output tone. The correction unit 117, the gradation reproduction processing unit 118, and the like are included.

  Hereinafter, processing executed by the data conversion unit 104 of the color image processing apparatus 100 will be described. First, the endian switching register unit 106 sets conditions for switching little endian or big endian for an arbitrary address signal. The condition setting method is the same as in the first embodiment.

  Then, based on the address signal from the external device (that is, the color image input device 121 and the operation panel 123) input from the external interface unit 101 or the specific bit of the address signal from the CPU 103 arranged on the internal bus 102A. Determine the data structure. After determining the data structure, the data structure is converted from the lower byte if it is little endian and from the upper byte if it is big endian. The converted data is written as necessary parameters in the register unit 105 in the color image processing apparatus 100.

  Next, processing contents in the image processing unit 110 will be described. In the original type automatic discrimination unit 111, whether the original read from the RGB signal (RGB density signal) from which various distortions have been removed and the color balance has been adjusted by the color image input device 121 is a character original, The document type is determined, for example, whether it is a printed photo document or a character-printed photo document in which characters and printed photos are mixed.

  The input tone correction unit 112 performs image quality adjustment processing such as background density removal and contrast on the RGB signals output from the document type automatic discrimination unit 111.

  The region separation processing unit 113 separates each pixel in the input image into one of a character region, a halftone dot region, and a photo region from the RGB signal. Based on the separation result, the region separation processing unit 113 sends a region identification signal indicating to which region the pixel belongs to the black generation and under color removal unit 115, the spatial filter processing unit 116, and the gradation reproduction processing unit 118. In addition to the output, the input signal output from the input gradation correction unit 112 is output to the subsequent color correction unit 114 as it is.

  The color correction unit 114 performs a process of removing color turbidity based on the spectral characteristics of the CMY color material including unnecessary absorption components in order to achieve faithful color reproduction.

  The black generation and under color removal unit 115 generates black (K) signals from the CMY three-color signals after color correction, and subtracts the K signals obtained by black generation from the original CMY signals to generate new CMY signals. The process to generate is performed. As a result, the CMY three-color signal is converted into a CMYK four-color signal.

  The spatial filter processing unit 116 performs spatial filter processing using a digital filter on the image data of the CMYK signal input from the black generation and under color removal unit, and corrects the spatial frequency characteristics. As a result, blurring of the output image and deterioration of graininess can be reduced. Similar to the spatial filter processing unit, the gradation reproduction processing unit 118 performs predetermined processing described later on the image data of the CMYK signal based on the region identification signal.

  For example, in a region separated into characters by the region separation processing unit 113, a filter with a high enhancement amount of a high-frequency component is used as a spatial filter in the spatial filter processing unit 116 in order to improve the reproducibility of characters. At the same time, the tone reproduction processing unit 118 performs binarization or multi-value processing using a high-resolution screen suitable for reproducing high-frequency components.

In addition, with respect to the region separated into halftone dots by the region separation processing unit 113, the spatial filter processing unit 116 performs low-pass filter processing for removing the input halftone component. The output tone correction unit 117 performs an output tone correction process for converting a signal such as a density signal into a halftone dot area ratio that is a characteristic value of the color image output device. A gradation reproduction process is performed in which the image is finally separated into pixels and processed so that each gradation can be reproduced. With respect to the region separated into photographs by the region separation processing unit 113, binarization or multi-value processing is performed on the screen with an emphasis on gradation reproducibility.
The image data that has been subjected to each processing described above is temporarily stored in a memory (not shown), read at a predetermined timing, and input to the color image output device 122.

  The color image output apparatus 122 is an apparatus that outputs an image based on the image data processed by the color image processing apparatus 100 onto a sheet such as paper or an OHP film. For example, an image output apparatus such as an electrophotographic system or an inkjet system Can be adopted. Note that the image output method is not limited to the electrophotographic method and the inkjet method.

  In this embodiment, the embodiment applied to the digital color copying machine has been described. However, the present invention may be applied to a digital color multifunction machine having a copier function, a printer function, a facsimile transmission function, a scan to e-mail function, and the like.

In this case, the digital color multi-function peripheral further includes a communication device such as a modem or a network card. When sending a facsimile, if the modem is ready for transmission by the transmission procedure with the other party, the image data compressed in a predetermined format (image data read by the scanner) is stored in the memory. The data is read from the data, and the necessary processing such as changing the compression format is performed, and the data is sequentially transmitted to the other party via the communication line. When receiving a facsimile, the CPU receives image data transmitted from the other party while performing a communication procedure, and inputs the received image data to the color image processing apparatus. The color image processing apparatus receives the received image data (not shown). The compression / decompression processing unit performs decompression processing. The decompressed image data is subjected to rotation processing and resolution conversion processing as necessary, subjected to output tone correction and tone reproduction processing, and is output from the image output device.
In addition, data communication is performed with a computer or other digital multi-function peripheral connected to the network via a network card or a LAN cable.

  In this embodiment, the color digital copying machine has been described. However, a monochrome multifunction machine may be used. A single facsimile communication apparatus may be used.

1 is a block diagram showing a system configuration according to Embodiment 1. FIG. It is explanatory drawing explaining the processing content which a data conversion part performs. 3 is a flowchart illustrating a procedure of processing executed by the image processing apparatus according to the first embodiment. 6 is a block diagram showing a system configuration according to Embodiment 2. FIG. It is explanatory drawing explaining the processing content which a data conversion part performs. FIG. 10 is a block diagram showing a system configuration according to a third embodiment. It is explanatory drawing explaining the processing content which a data conversion part performs. 10 is a flowchart illustrating a procedure of processing executed by the image processing apparatus according to the third embodiment. 1 is a block diagram showing an internal configuration of a digital color copying machine according to the present embodiment.

Explanation of symbols

1 External bus
2-5 CPU
10A, 10B, 10C Image processing device 11 External interface unit 12 Data conversion unit 13A, 13B Internal bus 14 Register unit 15 Endian switching register unit 16-18 Image processing unit 19 CPU
20-bit mask register section

Claims (4)

An external interface unit that is connected to a plurality of external CPUs via an external bus configured with an arbitrary bus width and transmits / receives data to / from each external CPU via the external bus, and data input through the external interface unit In an image processing apparatus including an image processing unit that performs image processing according to
For the data input from the external interface unit via the internal bus, the endian switching register unit that sets the endian switching method and the input data to switch the endian according to the set endian switching method are converted. An image processing apparatus comprising: a data conversion unit that performs data conversion; and a register unit that stores data output from the data conversion unit. An external interface unit that is connected to an external CPU via an external bus having an arbitrary bus width and transmits / receives data to / from the external CPU via the external bus, and an image according to data input through the external interface unit In an image processing apparatus including an image processing unit that performs processing,
An endian switching register for setting an endian switching method for data input from the external interface via the first and second internal buses; an internal CPU connected to the first internal bus; A data conversion unit for converting data input from the external CPU or internal CPU via the first internal bus so as to switch the endian according to the switching method set by the endian switching register unit; An image processing apparatus comprising: a register unit that stores data to be output through the second internal bus.   When the bus width of the external bus is different from the bus width of the internal bus, a bit extraction unit that extracts predetermined bits from the input data is provided so as to match the bus width of the internal bus. The image processing apparatus according to claim 1, wherein the image processing apparatus is characterized.   An image forming apparatus comprising: the image processing apparatus according to claim 1; and an image forming unit that forms an image processed by the image processing apparatus on a sheet.

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