JP2009253401A - Capacity-switching circuit, vco, and pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacity-switching circuit capable of improving the oscillation characteristics of a PLL and of a VCO. <P>SOLUTION: Capacitors C1k (k=0 to n), FETs (Q1k), and capacitors C2k are connected in series between a terminal P1 and a terminal P2. Drains of FETs (Q3k) are connected to the sources of FETs (Q1k), and the drains of FETs (Q4k) are connected to drains of FETs (Q1k). Gates of FETs (Q3k and Q4k) are connected to each other, and sources of these FETs are connected to each other. Control data bk controlling turning-on/off of the FETs (Q1k) are supplied to gates of FETs (Q1k). Source bias voltages VSk, which turn off the FETs (Q3k and Q4k), at least during turning-off of FETs (Q1k) are supplied to sources of FETs (Q4k). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a capacitance switching circuit, a VCO, and a PLL circuit.

  When a superheterodyne receiver is configured as a synthesizer, its local oscillation signal is formed by a PLL circuit, but a VCO resonance circuit that is a part of the PLL circuit is generally configured by an LC resonance circuit.

  In FIG. 7, reference numeral 11 indicates an example of such a VCO. That is, the sources of the N-channel MOS-FETs (Q1, Q2) are connected to each other and grounded through the constant current source Q0. The drains of the FETs (Q1, Q2) are connected to the power supply terminal T1 through the resonance coils L1, L2, and are connected to the other gate. Further, a variable capacitance element CD such as a variable capacitance diode is connected between the drains of the FETs (Q1, Q2), and a resonance circuit 21 is constituted by the variable capacitance element CD and the coils L1, L2. Note that the control voltage VC is supplied to the variable capacitance element CD.

  Therefore, since the capacitance of the variable capacitance element CD is changed by the control voltage VC, the oscillation frequency fVCO of the VCO 11 can be changed.

  However, when the PLL having the VCO 11 as described above is made into an IC, if the variable capacitance element CD is also made on-chip, the variable range of the capacitance becomes narrower than when not made on-chip, and the resonance frequency of the resonance circuit 21, That is, the variable range of the oscillation frequency fVCO is narrowed. In particular, when the power supply voltage + VDD at the terminal T1 is low for the purpose of reducing the power consumption of the IC, the change range of the control voltage VC is narrowed. As a result, the variable range of the oscillation frequency fVCO is even narrower.

  Therefore, it is considered to switch the resonance capacitance in the resonance circuit 21 by the capacitance switching circuit 22 as shown in FIG. In FIG. 7, connection points between the drains of the FETs (Q1, Q2) and the coils L1, L2 are defined as points P1, P2.

  In the capacity switching circuit 22 of FIG. 8, n pairs (n is an integer of 1 or more) N-channel MOS-FETs Q1k and Q2k (k = 0 to n) are provided, and their sources are grounded. These drains are connected to connection points P1, P2 also shown in FIG. 7 through capacitors C1k, C2k. Further, the control bits bk (control data DD) for ON / OFF control of the FETs (Q1k, Q2k) are supplied.

The capacitance of the capacitors C1k and C2k is, for example,
C1k = C2k = C0 ・ 2 ^ k (1)
C0: A predetermined capacity.

  Therefore, for example, when b0 = "L", the FETs (Q10, Q20) are turned off, which is equivalent to the case where the capacitors C10, C20 are not connected to the connection points P1, P2. However, when b0 = "H", the FETs (Q10, Q20) are turned on, so that the connection points P1, P2 are connected to the ground through the capacitors C10, C20. At this time, the capacitors C10, C20 are connected. Are connected in parallel to the coils L1, L2. Accordingly, the resonance frequency of the resonance circuit 21 at this time, that is, the oscillation frequency fVCO of the VCO 11, is determined by the values of the coils L1, L2, the values of the capacitors C10, C20, and the value of the variable capacitance element CD.

  Similarly, the other FETs (Q11, Q21) to (Q1n, Q2n) are turned off or on in accordance with the levels of the bits b1 to bn, so that the capacitors C11, C21 to (C1n, C2n) are replaced with the coil L1. , L2 is selectively connected in parallel.

  Accordingly, capacitors (C10, C20) to (C1n, C2n) are selectively connected to the coils L1, L2 corresponding to the levels of the control bits b0 to bn, and at this time, the capacitors (C10 , C20) to (C1n, C2n) are set as shown in equation (1), so the capacitance of the capacitors connected in parallel to the coils L1, L2 is changed in increments of 2 ^ k steps by the value C0. can do.

  As a result, one reception band is divided into 2 ^ k subbands by the control bits b0 to bn, and the oscillation frequency fVCO is changed by the variable capacitance element CD and the control voltage VC in each of the subbands. It will be. Therefore, even if the change range of the capacitance of the variable capacitance element CD becomes narrow, a necessary frequency can be obtained as the oscillation frequency fVCO of the VCO 11.

  On the other hand, in the capacitance switching circuit 22 of FIG. 9, the capacitor C1k, the source-drain of the N-channel MOS-FET (Q1k), and the capacitor C2k are connected in series between the connection points P1 and P2. At the same time, the source and drain of the FET (Q1k) are grounded through bias resistors R1k and R2k. The control bit bk is supplied to the gate of the FET (Q1k).

  Therefore, for example, when b0 = "L", the FET (Q10) is turned off, which is equivalent to the case where the capacitors C10 and C20 are not connected between the connection points P1 and P2. However, when b0 = "H", the FET (Q10) is turned on, so that the connection points P1 and P2 are connected through a series circuit of capacitors C10 and C20. At this time, the capacitor C10 , C20 are connected in parallel to the variable capacitance element CD. Accordingly, the oscillation frequency fVCO of the VCO 11 at this time is determined by the values of the coils L1 and L2, the values of the capacitors C10 and C20, and the value of the variable capacitance element CD.

  Similarly, the other FETs (Q11, Q21) to (Q1n, Q2n) are turned off or on in accordance with the levels of the bits b1 to bn, so that the capacitors (C11, C21) to (C1n, C2n) The series circuit is selectively connected in parallel to the variable capacitance element CD.

  Accordingly, a series circuit of capacitors (C10, C20) to (C1n, C2n) is selectively connected to the variable capacitance element CD in accordance with the levels of the control bits b0 to bn. Since the values of the capacitors (C10, C20) to (C1n, C2n) are set as shown in the equation (1), the capacitance of the capacitors connected in parallel to the coils L1, L2 is set to 2 by the value C0 / 2. It can be changed over ^ k steps.

  As a result, also in the case of the capacitance switching circuit 22 of FIG. 9, one reception band is divided into 2 ^ k subbands by the control bits b0 to bn, and in each of the subbands, the variable capacitance element CD and the control are controlled. The oscillation frequency fVCO is changed by the voltage VC. Therefore, even if the change range of the capacitance of the variable capacitance element CD becomes narrow, a necessary frequency can be obtained as the oscillation frequency fVCO of the VCO 11.

For example, there are the following prior art documents.
JP 2001-156629 A JP-A-9-93125 Japanese Patent Laid-Open No. 11-308101

  Here, with respect to the capacitance switching circuit 22 of FIG. 8, the FETs (Q10, Q20) and the capacitor C10 are representative of the FETs (Q10, Q20) to (Q1n, Q2n) and the capacitors (C10, C20) to (C1n, C2n). , C20. That is, for the sake of simplicity, it is assumed that the capacitance switching circuit 22 in FIG. 8 includes only FETs (Q10, Q20) and capacitors C10, C20.

And
CON: capacitance seen from points P1, P2 when FET (Q10, Q20) is turned on COFF: capacitance seen from points P1, P2 when FET (Q10, Q20) is turned off.

  Then, as the capacitance ratio CON / COFF increases, the change range (bandwidth due to subband switching) of the oscillation frequency fVCO due to the on / off of the FETs (Q10, Q20) can be increased.

And
CP: When the parasitic capacitance between the source and the back gate of the FET (Q10) is turned off, when the FET (Q10) is off, the parasitic capacitance CP is connected in series to the capacitor C1O.
COFF = C10 ・ CP / (C10 + CP) (2)
It becomes. Therefore, the capacitance ratio CON / COFF is calculated from the equation (2): CON / COFF = 1 + C10 / CP (3)
It becomes.

Also,
α: constant W: the gate width of the FET (Q10, Q20), the parasitic capacitance CP is proportional to the gate width W,
CP = α · W (4)
It is. Therefore, substituting equation (4) into equation (3), equation (3) becomes
CON / COFF-1 = C10 / (α · W) (5)
It becomes. The same applies to the FET (Q20) and the capacitor C20.

  That is, as the gate width W of the FET (Q10) becomes narrower, the capacitance ratio CON / COFF becomes larger, and the change range of the oscillation frequency fVCO due to on / off of the FETs (Q10, Q20) can be widened.

On the other hand, when FET (Q10) is on,
RON: When the ON resistance of the FET (Q10) is assumed, the ON resistance RON is connected in series with the capacitor C10. Therefore, the Q value of the resonance circuit 21 increases as the ON resistance RON decreases. That is,
QON: When the Q value of the resonance circuit 21 when the FETs (Q10, Q20) are on,
QON = 1 / (2πfVCO · C10 · RON) (6)
It becomes.

The on-resistance RON is inversely proportional to the gate width W,
RON = β / W (7)
β: constant. Therefore, substituting equation (7) into equation (6), equation (6) becomes
QON ＝ γ ・ W (8)
γ = 1 / (2πfVCO · C10 · β)
It becomes.

  That is, the narrower the gate width W of the FETs (Q10, Q20), the higher the Q value (QON) of the resonant circuit 21, and the phase noise characteristics of the oscillation signal SVCO of the VCO 11 are improved.

  From the above, according to the equations (5) and (8), the gate width W of the FET (Q10, Q20) is increased in order to widen the change range of the oscillation frequency fVCO due to the on / off of the FET (Q10, Q20). In order to improve the phase noise characteristics of the VCO 11, it is required to reduce the gate width W of the FETs (Q10, Q20).

  That is, the expansion of the change range of the oscillation frequency fVCO due to the on / off of the FETs (Q10, Q20) and the improvement of the phase noise characteristics of the oscillation signal SVCO of the VCO 11 are in a trade-off relationship, and it is difficult to achieve both.

  Moreover, in the capacitance switching circuit 22 of FIG. 8, the on-resistances RON and RON of the FETs (Q10 and Q20) are added in series to the capacitors C10 and C20, respectively, and become resistance values for two elements. It becomes a high value.

  In that respect, the capacitance switching circuit 22 of FIG. 9 has the Q value (QON) when the FET (Q10) is on determined only by the FET (Q10). When the gate width W of Q20) is equal, the Q value (QON) can be increased by a factor of two.

  However, in the capacitance switching circuit 22 of FIG. 9, in order to correctly turn on / off the FET (Q10) according to the level of the control bit b0, as shown in FIG. 9, resistors R10 and R20 are connected to connect the FET (Q10). ) Source and drain must be biased.

  At this time, since the resistors R10 and R20 are connected to the resonance circuit 21, the resistors R10 and R20 are required to have a sufficiently large value as compared with the impedances of the capacitors C10 and C20. However, if the values of the resistors R10 and R20 are increased, the physical size of the resistors R10 and R20 on the IC chip increases and the parasitic capacitance increases. As a result, when the FET (Q10) is off. This increases the capacitance COFF and decreases the capacitance ratio CON / COFF.

  That is, the expansion of the change range of the oscillation frequency fVCO due to the on / off of the FET (Q10) and the improvement of the phase noise characteristic of the oscillation signal SVCO of the VCO 11 are in a trade-off relationship, and it is difficult to achieve both. turn into.

  The present invention is intended to solve the above problems.

In this invention,
A first MOS-FET;
A first capacitor connected in series between a first terminal and the source of the first MOS-FET;
A second capacitor connected in series between the drain of the first MOS-FET and a second terminal;
A second MOS-FET having a drain connected to the source of the first MOS-FET;
A third MOS-FET having a drain connected to the drain of the first MOS-FET;
The gates of the second and third MOS-FETs are connected to each other, and the sources of the second and third MOS-FETs are also connected to each other,
Control data for controlling on / off of the first MOS-FET is supplied to the gate of the first MOS-FET,
A gate bias voltage for turning off the second and third MOS-FETs is supplied to the second and third MOS-FETs when at least the first MOS-FET is off.
The capacitance switching circuit is configured to be supplied with a source bias voltage that turns off the parasitic diode between the drain and back gate of the second and third MOS-FETs.

  According to the present invention, it is possible to achieve both the expansion of the change range of the oscillation frequency fVCO due to the on / off of the FET and the improvement of the phase noise characteristic of the oscillation signal SVCO of the VCO.

[1] Example of PLL Circuit In FIG. 1, reference numeral 10 denotes an example of a PLL circuit according to the present invention. In this PLL circuit 10, the oscillation signal SVCO of the VCO 11 is supplied to the variable frequency dividing circuit 12, and is divided into a frequency divided signal SDIV having a frequency of 1 / N (N is a positive integer), and this frequency divided signal SDIV is phase-shifted. It is supplied to the comparison circuit 13. Although not shown, the reference signal generation circuit 14 includes, for example, a crystal oscillation circuit and a frequency dividing circuit. A reference signal SREF having a reference frequency fREF is extracted from the reference signal generation circuit 14, and the reference signal SREF is It is supplied to the phase comparison circuit 13.

  Then, the phase comparison circuit 13 compares the phase of the frequency-divided signal SDIV with the reference signal SREF, and supplies the comparison output to the charge pump circuit 15 to generate a pulse corresponding to the phase difference between the frequency-divided signal SDIV and the reference signal SREF. A phase comparison output with varying width is taken out. Then, this comparison output is supplied to the loop filter 16, and a voltage VC whose level changes corresponding to the phase difference between the frequency-divided signal SDIV and the reference signal SREF is taken out, and this voltage VC is supplied to the VCO 11 with the oscillation frequency fVCO. Supplied as a control voltage.

As a result, in the steady state, the oscillation frequency fVCO of the VCO 11 is
fVCO = N ・ fREF (11)
Therefore, if the frequency division ratio N is changed, the oscillation frequency fVCO of the VCO 11 can be changed.

  Therefore, the frequency of the received signal is converted using the oscillation signal SVCO (or its frequency-divided signal) of the VCO 11 as a local oscillation signal, and the reception frequency can be changed by changing the frequency division ratio N. That is, synthesizer type reception can be performed.

  Although details will be described later, the VCO 11 is supplied with control data DD for switching and controlling the change range (oscillation frequency band from the lowest frequency to the highest frequency) of the oscillation frequency fVCO.

[2] Example of VCO 11 FIG. 2 shows an example of the VCO 11 according to the present invention. That is, the sources of the N-channel MOS-FETs (Q1, Q2) are connected to each other and connected to one reference potential point, for example, ground, through the constant current source Q0. Further, the drains of the FETs (Q1, Q2) are connected to the other potential point, for example, the power supply terminal T1, through the resonance coils L1, L2, and to the other gate. Note that connection points between the drains of the FETs (Q1, Q2) and the coils L1, L2 are connection points P1, P2.

  Further, a variable capacitance element CD is connected between the drains of the FETs (Q1, Q2), and a capacitance switching circuit 22 to be described later is connected. These variable capacitance element CD and capacitance switching circuit 22, coils L1, L2 and Thus, the resonance circuit 21 is configured. The capacity switching circuit 22 is supplied with control data DD, and the capacity between the connection points P1 and P2 is changed to a step type. The variable capacitance element CD is supplied with a control voltage VC and its capacitance is continuously changed. Examples of the variable capacitance element CD include a variable capacitance diode and a MOS varactor.

  Accordingly, in the intended reception band, the subband is switched by the control data DD, and the oscillation frequency fVCO of the VCO 11 is changed by the control voltage VC in the switched subband.

[3] Example of Capacitance Switching Circuit 22 [3-1] Configuration Example FIG. 3 shows an example of the capacitance switching circuit 22 according to the present invention. That is, in this switching circuit 22, n (n is an integer of 1 or more) N-channel MOS-FETs (Q1k) (k = 0 to n) are provided, and the connection point P1 is a resonance capacitor C1k. Is connected to the source of the FET (Q1k), and its drain is connected to the connection point P2 through the resonance capacitor C2k.

  Further, a control bit bk for controlling on / off of the FET (Q1k) is supplied to the gate of the FET (Q1k). The control data DD described above is the control bits b0 to bn.

The capacitance of the capacitors C1k and C2k is, for example,
C1k = C2k = C0 ・ 2 ^ k (12)
C0: A predetermined capacity.

  Further, the source of the FET (Q1k) is connected to the drain of the N-channel MOS-FET (Q3k), and the drain of the FET (Q1k) is connected to the drain of the N-channel MOS-FET (Q3k). A gate voltage VGk is supplied as a bias voltage to the gates of the FETs (Q3k, Q4k), and a source voltage VSk is supplied as a bias voltage to their sources.

  In this case, the gate voltage VGk, the source voltage VSk, and the control data DD (control bits b0 to bn) are, for example, any one of the voltages shown in FIGS. The connection points P1 and P2 are connection points between the drains of the FETs (Q1 and Q2) and the coils L1 and L2 in the VCO 11 shown in FIG. Further, a circuit unit configured by the elements Q1k, Q3k, Q4k, C1k, and C2k corresponding to the control bit bk is defined as a capacitance switching unit 22k.

  According to such a configuration, the following operation is performed according to the control data DD (bits b0 to bn), the gate voltage VGk, and the source voltage VSk. In the capacitance switching circuit 22, the operations of the capacitance switching units 220 to 22n are the same, and therefore, the operation will be described below by using the capacitance switching unit 220 for the sake of simplicity.

[3-2] Operation Example [3-2-1] First Control Example In this example, the capacity switching unit 220 has a control bit bO, a gate voltage VG0, and a source voltage VS0 as shown in FIG. 4A, for example. Supplied.

In this case, the gate voltage VG0 and the source voltage VS0 are fixed bias voltages,
VS0> VG0−VTH
VTH: A predetermined voltage relationship is established.

  The control bit b0 is b0> VS0 + VTH when it is at "H" level, and VS0 + VTH> b0 when it is at "L" level.

  Therefore, regardless of the level of the control bit b0, the FETs (Q30, Q40) are reverse-biased and turned off, and the drain-source is always high impedance.

  When b0 = "H", the FET (Q10) is forward-biased and turned on, so that the capacitors C10 and C20 are connected in series between the connection points P1 and P2.

  However, when b0 = "L", the FET (Q10) is reverse-biased and turned off. Therefore, the connection points P1 and P2 are separated, and the capacitors C10 and C20 are not connected. become.

  The same applies to the other capacity switching units 221 to 22n. Accordingly, the capacity between the connection points P1 and P2 can be changed over 2 ^ k steps by the value C0 / 2 corresponding to the control bits b0 to bn. As a result, in the intended reception band, the subbands can be switched by the control bits b0 to bn. In the switched subband, the oscillation frequency fVCO of the VCO 11 can be changed by the control voltage VC.

  In this example, the source and drain potentials of the FET (Q10) are obtained through the drain and source of the FET (Q30, Q40), but between the drain and source when the FET (Q30, Q40) is off. Is sufficiently larger than the impedance of the capacitors C10 and C20 (as compared with the resistors R10 and R20 in FIG. 9). Therefore, the Q value of the resonance circuit 21 is not lowered.

  Moreover, since it is not necessary to increase the physical size of the FET (Q30, Q40) on the IC chip in order to obtain a large impedance, the parasitic capacitance does not increase, and as a result, the FET (Q10) is turned off. In this case, the capacitance COFF is reduced, and the capacitance ratio CON / COFF can be increased.

  Therefore, the phase noise characteristic of the oscillation signal SVCO of the VCO 11 can be improved, and the change range of the oscillation frequency fVCO due to the on / off of the FET (Q10) can be expanded.

[3-2-2] Second Control Example In this example, the capacity switching unit 220 is supplied with a control bit bO, a gate voltage VG0, and a source voltage VS0 as shown in FIG. 4B, for example.

  That is, the gate voltage VG0 is a fixed bias voltage, but the source voltage VSO is lower than that in the case of FIG. 4A in the range of VS0> VG0−VTH when b0 = “H”, and b0 = “L”. In the case of "", the voltage is set higher than in the case of FIG.

  Therefore, the same operation as in [3-2-1] is performed, the phase noise characteristic of the oscillation signal SVCO of the VCO 11 can be improved, and the change range of the oscillation frequency fVCO due to the on / off of the FET (Q10) can be reduced. Can be enlarged.

  Furthermore, in the VCO 11, when the FET (Q10) is off, the oscillation signal SVCO of the VCO 11 is applied at almost the same level between the source and drain of the FET (Q10), so that a parasitic diode generated at the source and drain of the FET (Q10). May turn on. However, in this example, since the source voltage VS0 is changed as described above and becomes higher than the back gate potential VB of the IC, the parasitic diode generated at the source and drain of the FET (Q10) is not turned on.

  Further, when the FET (Q10) is on and the source voltage VS0 is higher than the back gate potential VB, the on-resistance RON of the FET (Q10) slightly increases, but in this example, the source voltage VS0 is the back voltage of the IC. Since it is not higher than the gate potential VB, the on-resistance RON does not increase.

[3-2-3] Third Control Example In this example, the capacity switching unit 220 is supplied with a control bit bO, a gate voltage VG0, and a source voltage VS0 as shown in FIG. 4C, for example. That is, the source voltage VS0 is a fixed bias voltage, but the gate voltage VG is at a level equal to the control bit b0.

  Therefore, the same operation as in [3-2-1] is performed, the phase noise characteristic of the oscillation signal SVCO of the VCO 11 can be improved, and the change range of the oscillation frequency fVCO due to the on / off of the FET (Q10) can be reduced. Can be enlarged.

  According to this example, when the FET (Q10) is turned on, the FETs (Q30, Q40) are also turned on at the same time, so that the on-resistance RON can be further reduced.

[3-2-4] Fourth Control Example In this example, the capacity switching unit 220 is supplied with a control bit bO, a gate voltage VG0, and a source voltage VS0 as shown in FIG. 4D, for example. That is, it is a case where the source voltage VS0 in [3-2-2] and the gate voltage VG0 in [3-2-3] are combined, which is more effective than the case where each is executed alone.

[3-2-5] Fifth Control Example In this example, the capacity switching unit 220 is supplied with a control bit bO, a gate voltage VG0, and a source voltage VS0 as shown in FIG. 4E, for example. That is, in [3-2-4], the gate voltage VG0 is delayed by a predetermined time with respect to the control bit b0. In order to obtain the gate voltage VG0 delayed by a predetermined time with respect to the control bit b0 as described above, for example, a delay circuit as shown in FIG. 5A or B can be used.

  For example, in [3-2-2], when the FET (Q10) is off, the FETs (Q30, Q40) exhibit high impedance. Therefore, when the FET (Q10) is turned on from off, the source voltage VSO The source potential and drain potential of the FET (Q10) are set to a predetermined value with a large time constant even if the switching is performed. Therefore, when used for the VCO 11, it takes time until the oscillation frequency fVCO is settled.

  However, in this example, since the gate voltage VG0 is delayed with respect to the control bit b0, the time until the source potential and drain potential of the FET (Q10) are settled can be shortened. The time until the oscillation frequency fVCO is settled can be shortened.

  For example, when the PLL circuit 10 is used as a local oscillation circuit of a receiver, the subband is switched by the capacitance switching circuit 22 and the oscillation frequency fVCO of the VCO 11 may be automatically calibrated for each subband. In such a case, since the oscillation frequency fVCO cannot be measured and calibrated until the oscillation frequency fVCO is settled, if the time until the oscillation frequency fVCO is settled can be shortened, the time required for automatic calibration is shortened. be able to.

[4] Others The capacity switching circuit 22 shown in FIG. 3 is configured by an N-channel MOS-FET, but can also be configured by a P-channel MOS-FET, for example, as shown in FIG. In this case, the polarities of the control bit b0, the gate voltage VG0, and the source voltage VS0 may be reversed from those in FIG.

[5] Summary According to the capacitance switching circuit 22 described above, a bias voltage is applied to the source and drain of the FET (Q1k) through the drain and source of the FET (Q3k, Q4k), but the FET (Q3k, Q4k) The impedance between the drain and source when is turned off is sufficiently larger than the impedance of the capacitors C1k and C2k than in the case of the resistors R1k and R2k in FIG.

  Therefore, since the Q value of the resonance circuit 21 is not lowered, the phase noise characteristic of the oscillation signal SVCO of the VCO 11 can be improved.

  Further, since the bias voltage of the source and drain of the FET (Q1k) is applied through the FET (Q3k, Q4k), the physical size of the FET (Q3k, Q4k) on the IC chip is obtained in order to obtain a large impedance. Does not need to be increased as in the case of resistors. Therefore, the parasitic capacitance does not increase, the capacitance COFF when the FET (Q1k) is OFF is reduced, and the capacitance ratio CON / COFF can be increased. As a result, the change range of the oscillation frequency fVCO due to the on / off of the FET (Q1k) can be expanded.

  Furthermore, since a TV tuner requires a low-noise local oscillation signal for a very wide frequency range of about 40 MHz to 900 MHz, the VCO 11 is also required to have a very wide variable range. The VCO 11 can cope with the request.

[List of abbreviations]
IC: Integrated Circuit
FET: Field Effect Transistor
MOS: Metal Oxide Semiconductor
PLL: Phase Locked Loop
Q value: Quality Factor
VCO: Voltage Controlled Oscillator

It is a systematic diagram showing one embodiment of the present invention. It is a connection diagram showing one embodiment of the present invention. It is a connection diagram showing one embodiment of the present invention. It is a wave form diagram which shows one form of this invention. It is a systematic diagram which shows an example of a part. It is a connection diagram which shows the other form of this invention. It is a connection diagram for explaining the present invention. It is a connection diagram for explaining the present invention. It is a connection diagram for explaining the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... PLL circuit, 11 ... VCO, 12 ... Variable frequency dividing circuit, 13 ... Phase comparison circuit, 14 ... Reference signal generation circuit, 15 ... Charge pump circuit, 16 ... Loop filter, 21 ... Resonance circuit, 22 ... Capacitance switching circuit

Claims (8)

A first MOS-FET;
A first capacitor connected in series between a first terminal and the source of the first MOS-FET;
A second capacitor connected in series between the drain of the first MOS-FET and a second terminal;
A second MOS-FET having a drain connected to the source of the first MOS-FET;
A third MOS-FET having a drain connected to the drain of the first MOS-FET;
The gates of the second and third MOS-FETs are connected to each other, and the sources of the second and third MOS-FETs are also connected to each other,
Control data for controlling on / off of the first MOS-FET is supplied to the gate of the first MOS-FET,
A gate bias voltage for turning off the second and third MOS-FETs is supplied to the second and third MOS-FETs when at least the first MOS-FET is off.
A capacitance switching circuit that is supplied with a source bias voltage that turns off a parasitic diode between the drain and back gate of the second and third MOS-FETs. The capacitance switching circuit according to claim 1,
A capacitance switching circuit in which the gate bias voltage supplied to the gates of the second and third MOS-FETs and the source bias voltage are made constant regardless of whether the first MOS-FET is on or off. The capacitance switching circuit according to claim 1,
The gate bias voltage is made constant regardless of whether the first MOS-FET is on or off, and
A capacitance switching circuit configured to bring the source bias voltage close to the gate bias voltage when the first MOS-FET is on. The capacitance switching circuit according to claim 1,
While keeping the source bias voltage constant regardless of whether the first MOS-FET is on or off,
A capacitance switching circuit that changes the gate bias voltage in the same polarity direction as the control data. The capacitance switching circuit according to claim 1,
While changing the gate bias voltage in the same polarity direction as the control data,
A capacitance switching circuit that changes the source bias voltage in the direction of the opposite polarity to the control data. The capacitance switching circuit according to claim 1,
While changing the gate bias voltage in the same polarity direction as the control data,
Delay from the change of the control data,
A capacitance switching circuit that changes the source bias voltage in the direction of the opposite polarity to the control data. The resonance circuit is a capacitive means for resonance.
A capacity switching circuit;
A variable capacitance element connected in parallel to the capacitance switching circuit;
The capacitance switching circuit is
A first MOS-FET;
A first capacitor connected in series between the first connection point for the parallel connection and the source of the first MOS-FET;
A second capacitor connected in series between the drain of the first MOS-FET and the second connection point for the parallel connection;
A third MOS-FET having a drain connected to the drain of the first MOS-FET,
The gates of the second and third MOS-FETs are connected to each other, and the sources of the second and third MOS-FETs are also connected to each other,
Control data for controlling on / off of the first MOS-FET is supplied to the gate of the first MOS-FET,
A gate bias voltage for turning off the second and third MOS-FETs is supplied to the second and third MOS-FETs when at least the first MOS-FET is off.
A source bias voltage is supplied to turn off the parasitic diode between the drain and back gate of the second and third MOS-FETs, and the change range of the oscillation frequency is changed by turning on and off the control data.
A VCO whose oscillation frequency is changed by a control voltage supplied to the variable capacitance element. VCO,
A variable frequency dividing circuit for dividing the oscillation signal of the VCO;
A phase comparison circuit that compares the phase of the output signal of the variable frequency dividing circuit with a reference signal having a reference frequency;
A charge pump circuit to which the output of the phase comparison circuit is supplied;
The output of the charge pump circuit is supplied to output a voltage whose level changes in accordance with the phase difference between the output signal of the variable frequency dividing circuit and the reference signal, and this voltage is used as the control voltage for the VCO. A loop filter to supply,
The VCO has a resonance circuit as a capacitive means for resonance.
A capacity switching circuit;
A variable capacitance element connected in parallel to the capacitance switching circuit;
The capacitance switching circuit is
A first MOS-FET;
A first capacitor connected in series between the first connection point for the parallel connection and the source of the first MOS-FET;
A second capacitor connected in series between the drain of the first MOS-FET and the second connection point for the parallel connection;
A second MOS-FET having a drain connected to the source of the first MOS-FET;
A third MOS-FET having a drain connected to the drain of the first MOS-FET;
The gates of the second and third MOS-FETs are connected to each other, and the sources of the second and third MOS-FETs are also connected to each other,
Control data for controlling on / off of the first MOS-FET is supplied to the gate of the first MOS-FET,
A gate bias voltage for turning off the second and third MOS-FETs is supplied to the second and third MOS-FETs when at least the first MOS-FET is off.
A source bias voltage is supplied to turn off the parasitic diode between the drain and back gate of the second and third MOS-FETs, and the change range of the oscillation frequency is changed by turning on and off the control data.
A PLL circuit in which the oscillation frequency is changed by changing the frequency dividing ratio of the variable frequency dividing circuit.

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