JP2009253115A - Wafer stage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer stage which prevents the occurrence of friction between a wafer and the wafer stage. <P>SOLUTION: The wafer stage 10 is applied to a semiconductor processor, and has a wafer bearing surface 11 on which the semiconductor wafer W is placed. The wafer bearing surface 11 is formed so that the outer peripheral edge 11e of the surface 11 is situated more inwardly than the outer peripheral edge We of the semiconductor wafer back surface Wb that is in contact with the wafer bearing surface 11. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor processing apparatus for performing CVD or heat treatment on a semiconductor wafer or the like, and more particularly to a wafer stage used for mounting a semiconductor wafer in a semiconductor processing apparatus.

As a semiconductor processing apparatus, for example, as well known in Patent Document 1, there is a multi-chamber apparatus that performs processing in a single wafer type. This multi-chamber apparatus is provided with a plurality of chambers, that is, a transfer chamber disposed in the center in plan view, and a semiconductor wafer (hereinafter simply referred to as a wafer) disposed around the transfer chamber. A process chamber in which various processes such as CVD processing and heat treatment are performed, and a load lock chamber in which a wafer cassette is placed. The central transfer chamber stores a transfer robot for transferring a semiconductor wafer, and can transfer the semiconductor wafer between the wafer stage of the load lock chamber and each process chamber.
JP 2004-265894 A

By the way, as described above, the wafer placed on the wafer stage is transferred to a transfer destination such as each process chamber by a handling tool such as a transfer robot.
However, when the wafer placed on the wafer stage is unloaded using this handling tool, rubbing (friction) occurs between the back surface (contact surface) of the wafer and the placement surface of the wafer stage, and the wafer. Problems such as scratches and dirt may occur on the back side.
If scratches occur on the back surface of the wafer, silicon based on the scratches may grow abnormally during, for example, silicon epitaxial growth performed in subsequent processing, and defects may occur.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a wafer stage in which the occurrence of rubbing between the wafer and the wafer mounting surface of the wafer stage is prevented.

  The invention according to claim 1 is a circular wafer stage used for mounting a semiconductor wafer applied to a semiconductor processing apparatus, and includes a flat wafer mounting surface on which a semiconductor wafer is mounted, The outer peripheral edge of the wafer mounting surface is a wafer stage formed on the inner side of the outer peripheral edge of the back surface of the semiconductor wafer in contact with the wafer mounting surface.

  As a result of intensive investigations on the occurrence of scratches and dirt on the backside of the wafer, scratches and dirt were likely to occur on the outer periphery of the wafer, and further investigations revealed that scratches and dirt were most likely to occur on the outer peripheral edge of the wafer backside. In this regard, as in the present invention, if the wafer mounting surface is formed so that the outer peripheral edge is located inside the outer peripheral edge of the back surface of the semiconductor wafer that is in contact with the wafer mounting surface, the wafer is mounted on the wafer stage. Sometimes, contact between the outer peripheral edge of the wafer back surface and the wafer placement surface of the wafer stage is prevented. Therefore, when unloading the wafer from the wafer stage, the occurrence of rubbing between the outer periphery of the wafer back surface and the wafer mounting surface of the wafer stage is reliably prevented, and scratches and dirt on the wafer back surface are more reliably generated. Is prevented.

  According to a second aspect of the present invention, an annular outer groove is formed on the outer side of the wafer mounting surface adjacent to the outer peripheral edge of the wafer mounting surface, and the diameter of the inner wall of the outer groove A diameter smaller than the diameter of the back surface of the semiconductor wafer placed on the placement surface, and the diameter of the outer wall of the outer groove is larger than the diameter of the back surface of the semiconductor wafer placed on the wafer placement surface. The wafer stage according to Item 1.

  When such an annular outer groove having a predetermined width is formed, contact between the outer peripheral edge of the wafer back surface and the wafer placement surface of the wafer stage is prevented, and the generation of scratches and dirt is prevented. Further, such a structure is a structure obtained by forming an outer groove on a conventional wafer stage that is not provided with a groove, and the present invention can be easily applied to a conventional wafer stage.

  The invention according to claim 3 is another wafer placement for placing a semiconductor wafer having a diameter different from that of the semiconductor wafer placed on the wafer placement surface inside or outside the wafer placement surface. One or more surfaces are formed, and an annular surface on which a large-diameter semiconductor wafer is mounted among two adjacent wafer mounting surfaces that are arbitrarily selected from the plurality of formed wafer mounting surfaces The inner peripheral edge of the large-diameter wafer mounting surface is located outside the outer peripheral edge of the small-diameter wafer mounting surface on which the small-diameter semiconductor wafer is mounted. Is larger than the diameter of the semiconductor wafer to be placed on the small-diameter wafer placement surface, and the large-diameter wafer placement surface is disposed at a position higher than the small-diameter wafer placement surface. The way of claim 1 It is a stage.

  If a plurality of wafer placement surfaces are formed in this way, scratches and dirt on the wafer back surface can be prevented for all types of wafers on a wafer stage on which a plurality of types of wafers can be placed.

  According to a fourth aspect of the present invention, an annular intermediate groove is provided between the large-diameter wafer mounting surface and the small-diameter wafer mounting surface. 4. The wafer stage according to claim 3, which is an inner peripheral edge of the diameter wafer mounting surface, and an inner wall of the intermediate groove is an outer peripheral edge of the small diameter wafer mounting surface.

  As described above, the structure with grooves can be obtained by forming the grooves on a conventional wafer stage that does not have grooves, so that the conventional multi-wafer stage that can mount wafers of multiple types of diameters can be obtained. Also, the present invention can be easily applied.

  According to a fifth aspect of the present invention, there is provided a chucking method or mounting in which the semiconductor wafer transport means provided in the semiconductor processing apparatus includes an operation of pressing the outer peripheral portion of the surface of the semiconductor wafer mounted on the wafer mounting surface. 5. The wafer stage according to claim 1, wherein a chucking method including an operation of adsorbing the front surface or the back surface of the semiconductor wafer is used.

  After examining the occurrence of scratches and dirt on the backside of the wafer, the chucking method including the operation of pressing the outer peripheral portion of the surface of the semiconductor wafer placed on the wafer placement surface as a wafer chucking method in a transfer means such as a transfer robot Or when using the chucking method including the operation of adsorbing the front surface or the back surface of the semiconductor wafer, scratches and dirt are likely to occur on the back surface of the wafer, particularly the outer peripheral edge of the wafer back surface. In this regard, according to the present invention, as described above, when the wafer is placed on the wafer stage, the outer peripheral edge of the wafer back surface does not contact the wafer placement surface of the wafer stage, and the wafer is unloaded from the wafer stage. In addition, the occurrence of rubbing between the outer peripheral edge of the wafer back surface and the wafer placement surface of the wafer stage is reliably prevented. Therefore, the wafer stage according to the present invention is suitable as a wafer stage of a semiconductor processing apparatus in which the above chucking method is used.

  If the wafer mounting surface of the wafer stage is made of a softer metal than the silicon wafer, the silicon wafer may be contaminated with heavy metal due to rubbing between the outer peripheral edge of the wafer back surface and the wafer mounting surface of the wafer stage. is there. In addition, if the material of the wafer mounting surface is made of quartz, the high purity prevents the occurrence of heavy metal contamination of the wafer, and the incorporation of the present invention more reliably prevents the generation of scratches and dirt. .

  A sixth aspect of the present invention is a semiconductor processing apparatus including the wafer stage according to any one of the first to fifth aspects.

  Such a semiconductor processing apparatus having a jig for automatically transporting a wafer between a load lock chamber and a reaction chamber, such as a silicon epitaxial furnace, when the wafer is placed on the wafer stage, The outer peripheral edge of the wafer does not come into contact with the wafer mounting surface of the wafer stage. Therefore, when unloading the wafer from the wafer stage, the occurrence of rubbing between the outer peripheral edge of the wafer back surface and the wafer placement surface of the wafer stage is reliably prevented, and the generation of scratches and dirt on the wafer back surface is suppressed. .

  According to the present invention, the occurrence of rubbing between the wafer placement surface of the wafer stage and the outer peripheral edge portion of the back surface of the wafer placed thereon is reliably prevented, and the generation of scratches and dirt on the back surface of the wafer is prevented. It is suppressed. Moreover, adhesion of particles (dust) is prevented.

  Hereinafter, embodiments of a wafer stage (wafer mounting table) according to the present invention will be described in detail with reference to the drawings.

  A wafer stage (see FIG. 2) 10 according to the present embodiment is used in the semiconductor processing apparatus 50 shown in FIG. First, the semiconductor processing apparatus 50 will be briefly described.

  A semiconductor processing apparatus 50 shown in FIG. 1 is an apparatus that performs a predetermined process such as heat treatment or epitaxial growth on a silicon wafer (hereinafter referred to as a wafer) W that is an object to be processed. The apparatus 50 includes a transfer chamber 51 disposed in the center thereof in plan view, a plurality of process chambers 52 disposed around the transfer chamber 51, and a load lock chamber 53 into which a wafer is loaded / unloaded. Yes.

  A transfer robot 55 is installed in the transfer chamber 51 arranged close to each chamber. The transfer robot 55 is used for transferring a wafer between the load lock chamber 53 and the process chamber 52, and includes a robot arm 55a. A vacuum chuck (not shown) for attracting and chucking the wafer surface is attached to the tip of the robot arm 55a. Since the chucking and chucking methods are well known, the description thereof is omitted here.

Specifically, the process chamber 52 is a heat treatment chamber such as a heat treatment reactor or a CVD chamber for performing a CVD process. A wafer mounting table (not shown) is installed in each process chamber 52 so that the silicon wafer W can be loaded and mounted.
The load lock chamber 53 is provided with a wafer stage (see FIG. 2) 10 used for placing a wafer.

  In FIG. 1, reference numeral “56” denotes a cassette case in which wafers are stored, reference numeral “57” denotes a cassette elevator used for loading / unloading the cassette case 56, and reference numeral “58” denotes a cassette case. 56 is a robot for carrying the wafer between the load lock chamber 53 and the reference numeral “59” is a monitor used for the operation of the semiconductor manufacturing apparatus.

As shown in FIG. 2, the wafer stage 10 includes a wafer placement surface 11 on which the wafer W is placed at the upper end thereof. The wafer placement surface 11 is a flat surface in contact with the placed wafer W, and is a horizontal plane. Further, the wafer placement surface 11 has a circular shape in plan view, and the outer peripheral edge 11e of the wafer placement surface 11 has a circular shape in plan view. It is a circular shape that is large enough to place a wafer.
That is, the wafer mounting surface 11 is formed such that the outer peripheral edge 11 e is positioned on the inner side of the outer peripheral edge We of the back surface Wb of the semiconductor wafer that is in contact with the wafer mounting surface 11.

  Here, the outer peripheral edge We of the wafer back surface Wb is a boundary (boundary line) between the wafer back surface Wb which is a flat surface and an inclined surface (so-called chamfered surface) Ws outside thereof. In this semiconductor wafer W, there are a wafer having a shape in which the boundary portion between the wafer back surface Wb and the outer chamfered surface Ws has an obtuse angle (cross section) and a wafer having a gentle arc surface (cross section). In the wafer having the shape of the boundary portion of the surface (cross section), the outer peripheral edge We of the wafer back surface Wb is an annular boundary line between the wafer back surface Wb and the chamfered surface Ws. The outer peripheral edge We is formed by the point where the flat back surface and the chamfered surface curved in an arc shape intersect with each other to form an annular shape in plan view.

Outside the wafer mounting surface 11 (when the mounting surface is a predetermined circular flat surface, a position radially outward from the mounting surface on the flat surface), an outside of a U-shaped cross section having a predetermined depth opened upward. A groove 12 is formed. The outer groove 12 is formed in an annular shape so as to surround the wafer placement surface 11, and the diameter of the inner wall 12 a of the outer groove 12 is the semiconductor wafer back surface Wb placed on the wafer placement surface 11. Is smaller than the diameter of the outer peripheral edge We. The diameter of the outer wall 12 b of the outer groove 12 is larger than the diameter of the outer peripheral edge of the back surface Wb of the semiconductor wafer W placed on the wafer placement surface 11. An outer peripheral portion 13 is formed outside the outer groove 12 so that the upper end surface position is higher than the wafer placement surface 11. In other words, a circular pocket having a predetermined depth is formed by the wafer mounting surface 11 and the outer peripheral portion 13 located on the outer periphery, and the wafer is mounted and held in the pocket.
When the wafer W is mounted on the wafer stage 10 having such a shape, the outer peripheral edge We of the wafer W is positioned at the position of the outer groove 12 outside the outer peripheral edge 11e of the wafer mounting surface 11. That is, the outer peripheral edge We of the wafer W is not in contact with the wafer placement surface 11. The outer peripheral edge portion (the outer peripheral edge portion including the chamfered surface portion) of the wafer W is in an overhang state.
In addition, although the stage material which comprises a wafer mounting surface is formed with quartz, the friction coefficient can also be reduced as much as possible as a mounting surface which coated other materials, such as a fluororesin.

  When unloading the wafer W placed on the wafer stage 10, the central portion of the surface Wa of the wafer W is sucked by the chuck at the tip of the robot arm 55 a of the transfer robot 55. Then, the tip of the robot arm 55a is moved upward to separate the wafer W from the wafer stage 10 and carry it out.

  By the way, when picking up the wafer W by moving the tip of the robot arm 55a upward, at the start of the picking operation, the center of the wafer W is swollen upward and the outer periphery of the wafer W is warped downward. A condition is likely to occur. When such warpage occurs, the outer peripheral edge We of the wafer back surface Wb may move differently from the upward movement, so that rubbing may occur between the outer peripheral edge We of the wafer back surface Wb and the wafer stage 10. . When rubbing occurs, scratches and dirt are likely to occur on the wafer back surface Wb due to this. Further, among the wafer back surface Wb, the outer peripheral edge We is a portion where the cross section changes, and is a position where defects such as scratches and dirt due to rubbing are likely to occur. Furthermore, a wafer having a shape in which the boundary portion between the wafer back surface Wb and the outer chamfered surface Ws has an obtuse angle (cross section) is likely to suffer from defects such as scratches and dirt due to rubbing.

  In order to improve the processing efficiency of the wafer W, it is preferable that the transfer speed of the wafer W is as high as possible. However, as the rising speed of the robot arm 55a is increased, the warp as described above tends to occur. Until now, in order to prevent the generation of scratches and dirt, it was necessary to make the ascending speed of the robot arm 55a as slow as possible.

In this regard, if the wafer stage 10 of the present embodiment is used, contact between the outer peripheral edge We of the wafer back surface Wb and the wafer mounting surface 11 is prevented, so that scratches and dirt are generated on the outer peripheral edge We of the wafer back surface Wb. Is prevented. Therefore, by using the wafer stage 10 of the present embodiment, it is possible to improve the processing efficiency of the wafer W by increasing the rising speed of the robot arm 55a while preventing the generation of scratches and dirt.
It should be noted that the warp as described above during the picking up operation of the wafer W is the same even if the chucking method is a method of attracting the wafer back surface. Therefore, the use of the wafer stage 10 of the present embodiment is effective in preventing the occurrence of kisses and dirt even in a semiconductor processing apparatus using a chucking method for attracting the wafer back surface Wb.

  Further, if the wafer stage 10 of the present embodiment is used so that the outer peripheral edge We of the wafer back surface Wb and the wafer mounting surface 11 do not come into contact with each other, the outer peripheral portion of the front surface of the wafer mounted on the wafer mounting surface 11 is changed. Even when pressed to the wafer stage 10 side, the wafer back surface Wb, which is likely to be scratched or soiled, does not come into contact with the wafer placement surface 11, and the gap between the outer peripheral edge We of the wafer back surface Wb and the wafer placement surface 11 is not reached. Scratches and dirt do not occur due to rubbing. Therefore, using the wafer stage 10 of the present embodiment means that a semiconductor processing apparatus using a chucking method including an operation of pressing the outer peripheral portion of the surface Wa of the wafer W placed on the wafer placement surface 11 toward the wafer stage 10 side. Is effective in preventing the occurrence of kisses and dirt.

  Next, a wafer stage according to another embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to a common structure etc. and the description is abbreviate | omitted.

  The wafer stage 20 shown in FIG. 3 is capable of mounting semiconductor wafers W having two or more types (here, three types) in diameter. The wafer stage 20 includes a large-diameter wafer mounting surface 21 for a large-diameter wafer W, a small-diameter wafer mounting surface 22 for a large-diameter wafer W, and a smaller diameter. And a wafer mounting surface 23 for a minimum diameter intended for the wafer W. An annular outer groove 24 is formed outside the outer peripheral edge 21 b of the large diameter wafer mounting surface 21, and the inner peripheral edge 21 a of the large diameter wafer mounting surface 21 and the small diameter wafer mounting surface 22. Between the outer peripheral edge 22b of the small-diameter wafer and between the inner peripheral edge 22a of the small-diameter wafer mounting surface 22 and the outer peripheral edge 23b of the minimum-diameter wafer mounting surface 23, respectively. , 26 are formed.

  The large-diameter wafer mounting surface 21 which is a substantially annular flat surface having a predetermined width in plan view has an inner peripheral edge 21 a located outside the outer peripheral edge 22 b of the small-diameter wafer mounting surface 22. The shortest diameter of the inner peripheral edge 21a of the large-diameter wafer placement surface 21 is the diameter of the wafer W to be placed on the substantially annular small-diameter wafer placement surface 22 in plan view. The larger diameter wafer mounting surface 21 is arranged at a position higher than the smaller diameter wafer mounting surface 22. The relationship between the small diameter wafer mounting surface 22 and the minimum diameter wafer mounting surface 23 is the same as the relationship between the large diameter wafer mounting surface 21 and the small diameter wafer mounting surface 22. Description is omitted.

In this way, in the single wafer stage 20 on which the wafers W having a plurality of types of diameters can be placed, the generation of scratches and dirt on the wafer back surface Wb can be prevented for the wafers W of all the diameters. it can.
The embodiment according to the present invention is not limited to the above-described embodiment, and various modified embodiments are included in the present invention without departing from the spirit of the invention.

  Next, in the wafer stage 20A shown in FIG. 4, the outer peripheral edges 21b, 22b, and 23b of the wafer mounting surfaces 21, 22, and 23 are not perpendicular to the cross section shown in the above embodiment, but have a predetermined curved surface or inclined surface. It is a round shape composed of faces.

When the outer peripheral edges 21b, 22b, and 23b of the wafer mounting surfaces 21, 22, and 23 are positioned inside the outer peripheral edge We of the wafer back surface Wb, the outer peripheral edge We of the wafer back surface Wb that easily generates scratches and dirt is placed on the wafer. The surfaces 21, 22, and 23 are not in contact with each other, and the generation of scratches and dirt can be prevented.
Here, as in the wafer stage 20A shown in FIG. 4, the outer peripheral edges of the wafer mounting surfaces 21, 22, and 23 are rounded in a round shape R (a shape with a gentle downward inclination toward the outside). This reliably prevents the edge-shaped portions of the wafer mounting surfaces 21, 22, and 23 from coming into contact with the wafer back surface Wb. Thereby, generation | occurrence | production of the flaw and dirt in wafer back surface Wb is prevented more reliably.

By the way, as described above, as a method of chucking the wafer W, in addition to the method of adsorbing the wafer surface Wa used in this embodiment, the outer peripheral portion of the surface of the wafer W placed on the wafer placement surface is used. A chucking method including a pressing operation or a chucking method including an operation of sucking the back surface Wb of the wafer W may be used.
However, when a chucking method including an operation of sucking the wafer back surface Wb is used, the suction portion of the transfer robot 55 can reach the position of the back surface Wb of the wafer W placed on the wafer stage. It is necessary to secure the space.

In addition, in products with a CVD oxide film formed on the backside of the wafer, if generation of scratches on the backside of the wafer can be prevented, abnormal growth based on scratches can be prevented during epitaxial growth, and abnormal protrusions can be prevented. Is done.
In the case of a thick epitaxial growth type, abnormal silicon growth occurs based on scratches during epitaxial growth. In the worst case, the wafer and the susceptor may stick to each other, so-called sticking may occur, but scratches can be prevented. In this case, such a problem is prevented from occurring.

  In addition, where it is necessary to accurately place the wafer stage in the counterbore part of the susceptor of this furnace, such as an epitaxial growth furnace, the wafer stage is preferably as hard as possible in order to prevent occurrence of misalignment. Since the harder the wafer, the easier it is to scratch the wafer, so far it has been necessary to use a wafer stage that is not as hard as possible in order to prevent scratches. However, if the wafer stage of this embodiment is used, contact between the outer peripheral edge of the wafer back surface and the wafer mounting surface can be prevented, and generation of scratches and dirt on the outer peripheral edge of the wafer back surface can be suppressed. Therefore, if the wafer stage of this embodiment is used, it is possible to improve the installation accuracy of the wafer stage by using a hard wafer stage while suppressing the generation of scratches and dirt.

It is a top view which shows schematic structure of the principal part of the semiconductor processing apparatus with which the wafer stage which concerns on one Example of this invention is used. It is a sectional side view showing the wafer stage of a 1st embodiment. It is a sectional side view showing the wafer stage of a 2nd embodiment. It is a sectional side view which shows the wafer stage of another embodiment.

Explanation of symbols

10, 20, 20A wafer stage,
11 Wafer mounting surface,
12 outer groove,
21 Large diameter wafer mounting surface,
22 Small wafer mounting surface,
23 Wafer mounting surface for minimum diameter,
24 outer groove,
25, 26 Intermediate groove,
50 semiconductor processing equipment,
51 transfer chamber,
52 process chambers,
53 Load lock chamber,
55 Transfer robot,
W wafer,
Wb Wafer backside,
We outer periphery.

Claims (6)

A circular wafer stage for mounting a semiconductor wafer applied to a semiconductor processing apparatus, comprising a flat wafer mounting surface,
A wafer stage characterized in that the outer peripheral edge of the wafer mounting surface is formed on the inner side of the outer peripheral edge of the back surface of the semiconductor wafer in contact with the wafer mounting surface.   An annular outer groove is formed on the outer side of the wafer mounting surface adjacent to the outer peripheral edge of the wafer mounting surface, and the diameter of the inner wall of the outer groove is mounted on the wafer mounting surface. 2. The wafer stage according to claim 1, wherein the diameter is smaller than the diameter of the back surface of the semiconductor wafer, and the diameter of the outer wall of the outer groove is larger than the diameter of the back surface of the semiconductor wafer placed on the wafer placement surface. One or more other wafer placement surfaces for placing a semiconductor wafer having a diameter different from that of the semiconductor wafer placed on the wafer placement surface are formed inside or outside the wafer placement surface. ,
Of two annular wafer placement surfaces that are arbitrarily selected from a plurality of formed wafer placement surfaces, an annular large-diameter wafer placement surface on which a large-diameter semiconductor wafer is placed The peripheral edge is located outside the outer peripheral edge of the small-diameter wafer placement surface on which the small-diameter semiconductor wafer is placed,
The diameter of the inner periphery of the large-diameter wafer mounting surface is larger than the diameter of the semiconductor wafer to be mounted on the small-diameter wafer mounting surface,
The wafer stage according to claim 1, wherein the large-diameter wafer placement surface is disposed at a position higher than the small-diameter wafer placement surface. An annular intermediate groove is provided between the large-diameter wafer mounting surface and the small-diameter wafer mounting surface,
4. The wafer stage according to claim 3, wherein an outer wall of the intermediate groove is an inner peripheral edge of the large-diameter wafer mounting surface, and an inner wall of the intermediate groove is an outer peripheral edge of the small-diameter wafer mounting surface. .   The semiconductor wafer transporting means provided in the semiconductor processing apparatus includes a chucking method including an operation of pressing the outer peripheral portion of the front surface of the semiconductor wafer placed on the wafer placement surface, or the front or back surface of the placed semiconductor wafer. The wafer stage according to any one of claims 1 to 4, wherein a chucking method including an operation for adsorbing the wafer is used.   A semiconductor processing apparatus provided with the wafer stage of any one of Claims 1-5.

Images