JP2009252649A - Phase control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a phase control device capable of easily selecting a formation of an optimal systematic system, according to the states of peripheral devices. <P>SOLUTION: Conditions when a timing control function is excluded in advance are stored in exception condition storing circuits 28a, 28b, state information of the peripheral devices 70 is read; a circuit formation for opening a pole or closing a pole is selected, without performing control of timing when the state information of the peripheral devices 70 and an exception conditions agree with each other; and a circuit formation for opening a pole or closing a pole is selected, by performing the control of timing when the state information of the peripheral devices 70 and the exception condition do not agree with each other. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to power switching that controls the switching timing of a circuit breaker to prevent the occurrence of a phenomenon that is harmful to the system and equipment, and more particularly to a phase control device.

  Patent Document 1 discloses a phase in which an opening control signal or a closing control signal is output after a delay time has elapsed so as to perform opening or closing at a desired phase in response to an opening command or closing command for a circuit breaker. A control device is described.

JP 2001-135205 A

  Although the above-described phase control device controls the opening / closing timing, it may be incorporated in a complicated electric power system, and the opening / closing timing may not be controlled depending on the state of the peripheral device. In that case, there is a problem that a large circuit for removing the phase control device from the system must be configured outside the device so as to open and close the circuit breaker without going through the phase control device.

  Further, when the external circuit that excludes the phase control device from the system is rearranged, there is a problem that a person needs to work near the high-voltage device.

  Further, when the phase control device is excluded from the system, there is a problem that it is necessary to take a power failure of peripheral devices and the phase control device, which may affect the power system.

  The present invention has been made to solve the above-described problems, and provides a phase control device capable of easily selecting an optimal system configuration according to the state of peripheral devices and the like. With the goal.

  In order to solve the above-described problems and achieve the object, a phase switchgear according to the present invention opens or closes the circuit breaker at a preset target phase of a main circuit current or an interelectrode voltage of the circuit breaker. In the phase control device capable of controlling the switching timing of the circuit breaker, the opening command signal is used as the opening control signal after the delay time has elapsed, or the closing command signal is used as the closing control signal after the delay time has elapsed. Output to the circuit breaker as a timing control unit for controlling the switching timing, and the opening command signal as it is as an opening control signal, or the closing command signal as it is as a closing control signal The timing non-control unit that does not control the opening / closing timing, the process for controlling the opening / closing timing by the timing control unit, and the timing non-control unit. Switching unit capable of switching between processing without controlling the opening / closing timing, a state information reading unit for reading peripheral device state information, and an exclusion condition storing conditions for the peripheral device state when the timing control function is excluded A comparison is made between the storage unit and the read state information and the condition stored in the exclusion condition storage unit, and when the comparison result matches, the switching timing by the timing non-control unit with respect to the switching unit And a collation unit that instructs the switching unit to switch to a process for controlling the opening / closing timing by the timing control unit when the comparison result does not match. It is characterized by that.

  According to the present invention, the condition regarding the state of the peripheral device when excluding the timing control function is stored in the exclusion condition storage unit, the state information of the peripheral device is read into the phase control device, and the state information of the peripheral device is stored. Since the timing control function is excluded when the condition stored in the exclusion condition storage unit matches, the timing control function can be easily excluded according to the status information of the peripheral device. Thus, the optimum system configuration can be easily selected.

  Hereinafter, embodiments of a phase control device according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. First, after describing an example of a conventional phase control device, an embodiment of the present invention will be described.

  FIG. 2 is a block diagram showing an example of the configuration of a conventional phase control device 150. In FIG. 2, a phase control device 150 that receives an opening command signal or a closing command signal, which is a command signal from a host device (not shown), and outputs an opening control signal or a closing control signal, and this phase control A circuit breaker 60 that is opened or closed by the opening control signal or the closing control signal output from the device 150 is shown.

  Next, the configuration of the phase control device 150 will be described. The phase controller 150 includes an opening command signal connector 14, an opening command bypass connector 15, an opening external jumper wire 50, an opening switching relay 10, an opening high-speed semiconductor relay 11, and an opening control signal. Connector 16, closing command signal connector 17, closing command bypass connector 18, closing external jumper wire 51, closing switching relay 12, closing high-speed semiconductor relay 13, closing control signal connector 19, a delay circuit 6, and an abnormality detector 7. Of the command signals from the host device, the opening command signal is input to the opening command signal connector 14, and the closing command signal is input to the closing command signal connector 17.

  One end of an external jumper wire 50 is connected to the opening command signal connector 14, and the other end of the external jumper wire 50 is connected to the opening command bypass connector 15. The external jumper line 50 is a detachable external connection attached to the phase control device 150, and functions as a circuit for excluding the phase control device 150 from the system.

  The opening switching relay 10 has a contact 10a and a contact 10b, and when one of the contacts 10a and 10b is in contact, the other contact is separated. Specifically, when the opening switching relay 10 is energized, the contact 10a is in contact and the contact 10b is separated, and when the opening switching relay 10 is not energized, the contact 10a is separated and the contact 10b is in contact. As shown in the figure, the opening command signal connector 14 and the opening switching relay 10 are connected on the contact 10a side. Further, the opening command bypass connector 15 and the opening switching relay 10 are connected on the contact 10b side.

  One end of the opening high-speed semiconductor relay 11 is connected to the contact 10a side of the opening switching relay 10, and when the opening switching relay 10 is excited, the opening command signal connector 14 is the opening switching relay. The high-speed semiconductor relay 11 for opening is connected via 10 contacts 10a. The other end of the opening high-speed semiconductor relay 11 is connected to the opening control signal connector 16. Furthermore, a connection line branched from the other end of the opening high-speed semiconductor relay 11 and the opening control signal connector 16 is connected to the contact 10 b side of the opening switching relay 10. In a state where the opening switching relay 10 is not excited, the opening command bypass connector 15 is connected to the opening control signal connector 16 via the contact 10b of the opening switching relay 10 and this connection line. The opening high-speed semiconductor relay 11 is ON / OFF controlled by a delay circuit 6 as described below.

  The above are the opening command signal connector 14, the opening command bypass connector 15, the opening external jumper wire 50, the opening switching relay 10, and the opening high-speed semiconductor, which are components related to the opening control. Although the configurations of the relay 11 and the opening control signal connector 16 have been described, as is apparent from the figure, the closing command signal connector 17 and the closing command bypass connector 18 which are components related to the closing control. The external jumper wire 51 for closing, the switching relay 12 for closing, the high-speed semiconductor relay 13 for closing, and the connector 19 for closing control signal are the same as those of the components related to the opening control. Therefore, the description is omitted.

  When an opening command signal or a closing command signal is input, the delay circuit 6 opens after a delay time so that the circuit opens or closes at a desired phase of the main circuit current or the voltage between the circuit breakers 60. The high-speed semiconductor relay 11 for pole or the high-speed semiconductor relay 13 for closing is turned on. For example, when an opening command signal is input to the opening command signal connector 14 in a state where the opening switching relay 10 is excited (that is, the contact 10a is in contact), the opening command signal is opened. The signal is input to the delay circuit 6 through a connection line branched from the pole command signal connector 14 and the contact 10a of the opening switching relay 10. When detecting the opening command signal, the delay circuit 6 switches the opening high-speed semiconductor relay 11 from OFF to ON after the delay time elapses. Thus, the opening command signal input from the opening command signal connector 14 passes through the contact 10a of the opening switching relay 10 and the high-speed semiconductor relay 11 for opening, and then from the opening control signal connector 16. Output as an opening control signal. The same applies to the closing command signal.

  The abnormality detection circuit 7 is a circuit that detects when an abnormality occurs in the phase control device 150, and outputs a switching relay control signal for opening to the switching relay 10 for opening, and the switching relay 12 for closing. Is output a switching relay control signal for closing. Generally, it is used in a state where the switching relay for opening 10 is excited, that is, in a state where the timing (or phase) is controlled. However, if the abnormality detection circuit 7 for detecting an abnormality inside the apparatus detects any abnormality, there is a possibility that correct control may not be performed. The signal is output as it is as an opening control signal.

  Specifically, for example, the switching relay control signal for opening is composed of a signal “1” (exclusion) or a signal “0” (connection), and “1” is output when the abnormality detection circuit 7 detects an abnormality. Otherwise, “0” is output. When the opening switching relay control signal is ‘1’, the opening switching relay 10 that has received this signal is not excited, and the contact 10a of the opening switching relay 10 is separated. As will be described later, in this case, the opening command signal is output from the opening control signal connector 16 via the external jumper line 50 without being controlled in timing, so the phase control device 150 is excluded from the system. It will be. On the other hand, when the opening switching relay control signal is “0”, the opening switching relay 10 receiving this is in an excited state, and the contact 10a of the opening switching relay 10 is in contact. . In this case, since the opening command signal is output from the opening control signal connector 16 with the timing controlled via the opening high-speed semiconductor relay 11, the phase control device 150 is connected to the system. . The same applies to the switching relay control signal for closing.

  Next, the configuration of the circuit breaker 60 will be described. The circuit breaker 60 includes an opening coil 61, an opening interlock circuit 62, a closing coil 63, and a closing interlock circuit 64. The opening coil 61 generates an opening operation by a flowing current, and the interlock circuit 62 is a protection circuit thereof. The same applies to the closing coil 63 and the closing interlock circuit 64. The opening control signal connector 16 is connected to the opening coil 61, and the opening control signal output from the phase control device 150 is input to the circuit breaker 60. Similarly, the closing pole control signal connector 19 is connected to the closing coil 63, and the closing pole control signal output from the phase controller 150 is input to the circuit breaker 60. The interlock circuits 62 and 64 are each connected to the negative side (N side) of the control power supply.

  Next, the operation of the phase control device 150 will be described. Hereinafter, the opening operation will be described, but the same applies to the closing operation. First, a case where the opening command signal is opened by controlling the opening timing via the inside of the phase control device 150 will be described. In this case, the abnormality detection device 7 is in a state where no abnormality is detected, and the opening switching relay control signal output from the abnormality detection circuit 7 to the opening switching relay 10 is in a state of “0” (connection). is there. Accordingly, the opening switching relay 10 is in an excited state, the contact 10a of the opening switching relay 10 is in contact, and the contact 10b is separated. In this state, when an opening command signal is input from the opening command signal connector 14, the opening command signal is opened via the contact 10 a of the opening switching relay 10 and the opening high-speed semiconductor relay 11. It is output from the control signal connector 16 as an opening control signal. More specifically, the opening command signal input from the opening command signal connector 14 is detected by the delay circuit 6, and the delay circuit 6 has a delay time so that the delay circuit 6 opens at a desired phase of the main circuit current or the inter-electrode voltage. Thereafter, the opening high-speed semiconductor relay 11 is turned on. As a result, the opening command signal is output from the opening control signal connector 16 as an opening control signal after the delay time has elapsed (that is, with timing control). The opening control signal output from the opening control signal connector 16 is input to the circuit breaker 60 and then flows through the opening coil 61, and the circuit breaker 60 is opened by the opening coil 61.

  Next, a case where the opening is performed without controlling the timing will be described. In this case, the abnormality detection device 7 is in a state of detecting an abnormality, and the opening switching relay control signal output from the abnormality detection circuit 7 to the opening switching relay 10 is in a state of “1” (exclusion). is there. Accordingly, the opening switching relay 10 is not excited, the contact 10a of the opening switching relay 10 is separated, and the contact 10b is in contact. In this state, when the opening command signal is input from the opening command signal connector 14, the opening command signal is connected to the opening command signal connector 14 and the opening command bypass connector 15. Then, it is outputted as an opening control signal from the opening control signal connector 16 via the contacts 10b of the opening switching relay 10 in sequence. In this case, the opening command signal is output as it is as the opening control signal without timing control. The opening control signal output from the opening control signal connector 16 is input to the circuit breaker 60 and then flows through the opening coil 61, and the circuit breaker 60 is opened by the opening coil 61.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a schematic configuration of the phase control device according to the present embodiment, and FIG. 3 is a block diagram showing an example of the configuration of the phase control device according to the present embodiment.

  In FIG. 1, a phase control device 1 according to the present embodiment, a peripheral device 70 such as a disconnector, and a circuit breaker 60 are shown.

  In FIG. 1, among the components of the phase control device 1, in particular, a plurality of connectors and an external jumper line 50 that is provided outside the phase control device 1 and is used as a circuit for excluding the phase control device 1 from the system. , 51, and other components are not shown. Below, the function which the phase control apparatus 1 has with the component specified in FIG. 1 is demonstrated.

  The phase control device 1 includes an opening command signal connector 14, an opening command bypass connector 15, an opening external jumper wire 50, an opening control signal connector 16, a closing command signal connector 17, and a closing command. A bypass connector 18, a closing external jumper wire 51, and a closing control signal connector 19 are provided. Since these are the same as in FIG. 2, the same reference numerals are given to the same components. Yes.

  An opening command signal or a closing command signal is input to the phase control device 1 as a command signal from a host device (not shown). Specifically, the opening command signal is input from the opening command signal connector 14, and the closing command signal is input from the closing command signal connector 17. Further, the opening control signal that is the output of the phase control device 1 is output from the opening control signal connector 16, the closing control signal is output from the closing control signal connector 19, and these control signals are output from the circuit breaker 60. Is input. The circuit breaker 60 is opened by the opening control signal or closed by the closing control signal.

  The phase control device 1 opens the command signal from the host device after the delay time has elapsed so as to open or close the circuit breaker 60 at a preset target phase of the main circuit current or the interelectrode voltage of the circuit breaker 60. It has a timing control part (not shown) which outputs to the circuit breaker 60 as a control signal or a closing control signal.

  In addition, the phase control device 1 outputs a command signal from the host device as it is as an opening control signal or a closing control signal to the circuit breaker 60 so as not to control the opening / closing timing (not shown). Have That is, the phase control device 1 is provided with an external jumper line 50 for connecting the opening command signal connector 14 and the opening command bypass connector 15. The external jumper line 50 is used for opening timing. A non-control unit is realized, and the external jumper line 50 bypasses the signal path of the opening command signal to the timing control unit as in the case of FIG. 2, and opens the control as it is without performing delay control. It is a circuit that enables output as a signal. The same applies to the external jumper wire 51 that connects the closing command signal connector 17 and the closing command bypass connector 18, and has the same function as in FIG. Realized. By using such external jumper lines 50 and 51, it is not necessary to configure a large external circuit outside the apparatus and recombine, and it is excluded from the system of the phase control device 1 with a simple configuration (exclusion of timing control function) ) Can be realized.

  The phase control device 1 further controls the opening / closing timing of the circuit breaker 60 according to the state of the peripheral device 70 and the like, and the case of opening / closing the circuit breaker 60 without controlling the opening / closing timing. Has a switching unit (not shown) for switching between. That is, the switching unit controls the opening / closing timing by the timing control unit according to state information 90a, 90b, 90c, 90d from the peripheral device 70 described later, and does not control the opening / closing timing by the timing non-control unit. Switch to processing.

  The phase control device 1 further includes a state information reading unit (not shown) for reading the state information of the peripheral device 70 (in the illustrated example, for example, four state information 90a, 90b, 90c, 90d), and a timing control function in advance. If the exclusion condition storage unit (not shown) that stores the condition (exclusion condition) about the condition of the peripheral device in the case of exclusion is compared with the read state information and the exclusion condition, and the comparison result matches When the switching unit is instructed to switch to a process that does not control the opening / closing timing by the timing non-control unit, and the comparison result does not match, the switching unit controls the switching timing by the timing control unit. And a collation unit (not shown) for instructing switching to processing to be performed.

  In FIG. 1, the timing control unit, the switching unit, the state information reading unit, the exclusion condition storage unit, and the collation unit are not illustrated, but are specifically illustrated in FIG. 3 as described later.

  As described above, the phase control device 1 detects the state of the peripheral device 7, compares the read state information with the exclusion condition, and controls the opening / closing timing using the timing control unit according to the comparison result. It is possible to switch between the case of opening and closing and the case of opening and closing without using the external jumper line 50 or 51 to control the opening and closing timing.

  Next, an example of the configuration of the phase control device 1 according to the present embodiment will be described in detail with reference to FIG. FIG. 3 shows an example of a specific aspect of the phase control apparatus having the schematic configuration of FIG. In FIG. 3, the phase control apparatus 1 which concerns on this Embodiment, the peripheral device 70, and the circuit breaker 60 are shown.

  First, the configuration of the phase control device 1 will be described. The phase control device 1 includes an opening command signal connector 14, an opening command bypass connector 15, an opening external jumper wire 50, an opening switching relay 10, an opening high-speed semiconductor relay 11, and an opening control signal. Connector 16, closing command signal connector 17, closing command bypass connector 18, closing external jumper wire 51, closing switching relay 12, closing high-speed semiconductor relay 13, closing control signal connector 19 and a delay circuit 6. Since these are the same as those shown in FIGS. 1 and 2, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the phase control device 1 receives an opening command signal or a closing command signal as a command signal from a host device (not shown), and these are respectively used for the opening command signal connector 14 or the closing command signal. The opening control signal or the closing control signal that is input from the connector 17 and the output of the phase control device 1 is output from the opening control signal connector 16 or the closing control signal connector 19, respectively. The same is applied to the circuit breaker 60. The circuit breaker 60 is opened or closed by an opening control signal or a closing control signal, respectively.

  Here, in correspondence with the above description made with reference to FIG. 1, the delay circuit 6, the opening high-speed semiconductor relay 11, and the closing high-speed semiconductor relay 13 constitute a timing control unit 80. In particular, the delay circuit 6 and the high-speed semiconductor relay 11 for opening are responsible for the function of performing the timing control of the opening, and the delay circuit 6 and the high-speed semiconductor relay 13 for closing are of the function of performing the timing control of the closing. I'm in charge. Further, as described above, the external jumper lines 50 and 51 form a timing non-control unit. Further, the opening switching relay 10 and the closing switching relay 12 constitute a switching unit. That is, the opening switching relay 10 performs the above switching with respect to the opening command, and the opening switching relay 10 performs the above switching with respect to the closing command. In FIG. 3, the timing control unit 80 includes a switching relay 10 for opening and a switching relay 12 for closing, which are switching units, but these are provided outside the timing control unit 80. It is good also as a structure.

  In addition to the above configuration, the phase control device 1 includes an abnormality detection circuit 7, a signal state reading circuit 27, an opening exclusion determination unit 29a, a closing exclusion determination unit 29b, an opening OR circuit 30a, and An OR circuit 30b for closing is provided.

  Similar to the case of FIG. 2, the abnormality detection circuit 7 is an abnormality detection unit that detects when an abnormality occurs in the phase control device 1. When the abnormality detection circuit 7 detects any abnormality, a signal “1” (exclusion) is output to each of the OR circuit 30a and the OR circuit 30b as a control signal for excluding the timing control function. When the abnormality detection circuit 7 has not detected an abnormality, the signal “0” (connection) is used as a control signal for connecting the phase control device 1 to the system and using the timing control function, and the OR circuit 30a and the logic It outputs to each sum circuit 30b.

  The signal state reading circuit 27 functions as a state information reading unit that reads state information of the peripheral device 70. The signal state reading circuit 27 reads, for example, four pieces of state information 90a, 90b, 90c, 90d, and the read state information is set as, for example, a “1” or “0” signal, respectively, and the opening time exclusion determination unit 29a and the closing time It outputs to the exclusion determination part 29b.

  Depending on the state of the peripheral device 70, the opening-time exclusion determining unit 29a determines whether to perform the opening by controlling the timing at the time of opening, or to perform the opening without controlling the timing, in other words, For example, it is determined whether or not to exclude the timing control function. The open time exclusion determination unit 29a includes a verification circuit 70a and an exclusion condition storage circuit 28a.

  The exclusion condition storage circuit 28a stores in advance conditions (exclusion conditions) regarding the state of the peripheral device 70 when the phase control device 1 is excluded (that is, the timing control function is excluded). A signal is output to the verification circuit 70a. In addition to the signal related to the exclusion condition from the exclusion condition storage circuit 28a, the collation circuit 70a receives a signal related to the status information of the peripheral device 70 from the signal state reading circuit 27.

  The collation circuit 70a compares and collates the signal from the signal state reading circuit 27 and the signal from the exclusion condition storage circuit 28a, and excludes the phase control device 1 when the comparison results match (that is, timing control). The signal '1' (excluded) is output to the OR circuit 30a in order to obtain a circuit configuration that excludes the function, and when the comparison result does not match, the phase control device 1 is connected (ie, the timing control function is used) The signal '0' (connection) is output to the OR circuit 30a for the circuit configuration. In correspondence with the explanation given with reference to FIG. 1, the exclusion condition storage circuit 28a corresponds to an exclusion condition storage unit, and the matching circuit 70a corresponds to a matching unit.

  Here, Table 1 shows an example of the exclusion condition stored in the exclusion condition storage circuit 28a. As the status information of the peripheral device 70, for example, disconnection monitoring information, bus voltage drop information, peripheral device failure information, The “exclusion condition pattern” when maintenance information is selected is shown. In Table 1, for example, four patterns (1) to (4) are shown as the exclusion condition patterns.

  The disconnection monitoring information monitors disconnection in the host device outputting the command signal, and becomes “1” when disconnection occurs. In this case, the timing control function is excluded regardless of the value of information other than the disconnection monitoring information (that is, regardless of whether it is ‘1’ or ‘0’). The pattern (1) represents such a condition. Information other than the disconnection monitoring information is “*”, and regardless of these values, if the disconnection monitoring information is “1”, timing control is performed. Indicates that the function is excluded.

  The bus voltage drop information is “1” when the bus voltage drops. In this case, the timing control function is excluded regardless of the value of information other than the bus voltage drop information (that is, whether it is ‘1’ or ‘0’). The pattern (2) represents such a condition, and other information other than the bus voltage drop information is “*” regardless of these values, and if the bus voltage drop information is “1”, This indicates that the timing control function is excluded.

  Peripheral device failure information monitors failures of disconnectors, breakers, etc., and becomes “1” when a failure occurs. In this case, the timing control function is excluded regardless of the value of information other than the peripheral device failure information (that is, regardless of whether it is ‘1’ or ‘0’). Pattern (3) represents such a condition, and other information other than peripheral device failure information is “*” regardless of these values, and if the peripheral device failure information is “1”, This indicates that the timing control function is excluded.

  The maintenance information is information that becomes “1” during the inspection work, and is not disconnected, the bus voltage is not reduced, and there is no failure in the peripheral device 70, and the inspection work is in progress. Only the timing control function is excluded. Pattern (4) represents such a condition. All information other than peripheral device failure information is “0”, and if the maintenance information is “1”, the timing control function is excluded. It is shown that.

  Thus, the exclusion condition pattern can be determined in advance according to the input signal from the peripheral device 70.

  When the exclusion conditions stored in the exclusion condition storage circuit 28a are the conditions shown in Table 1, the collation circuit 70a performs comparison and collation as follows. The state information of the peripheral device 70 read by the signal state reading circuit 27 is, for example, disconnection monitoring information “0”, bus voltage drop information “0”, peripheral device failure information “1”, and maintenance information “0”. In this case, the collation circuit 70a sequentially compares and collates the peripheral device state information with the patterns (1) to (4) obtained from the exclusion condition storage circuit 28a. In this case, since the status information of the peripheral device matches the pattern (3), the collation circuit 70a outputs a signal “1” (exclusion) for excluding the timing control function to the OR circuit 30a. Further, the status information of the peripheral device 70 read by the signal status reading circuit 27 is, for example, disconnection monitoring information “0”, bus voltage drop information “0”, peripheral device failure information “0”, and maintenance information “0”. If there is, the collation circuit 70a sequentially compares and collates the status information of the peripheral device 70 with the patterns (1) to (4) obtained from the exclusion condition storage circuit 28a. In this case, the status information of the peripheral device 70 is Since these patterns do not match all the patterns, the collation circuit 70a outputs a signal “0” (connection) for using the timing control function to the OR circuit 30a.

  The same applies to the closing time exclusion determination unit 29b, and the closing time exclusion determination unit 29b determines whether to exclude the timing control function according to the state of the peripheral device 70. The closed-circuit exclusion determination unit 29b includes a collation circuit 70b and an exclusion condition storage circuit 28b, which also have the same functions as the collation circuit 70a and the exclusion condition storage circuit 28a. Detailed description thereof is omitted. In correspondence with the description given with reference to FIG. 1, the exclusion condition storage circuit 28b corresponds to an exclusion condition storage unit, and the matching circuit 70b corresponds to a matching unit.

  The logical sum circuit 30a calculates a logical sum of the output signal from the collation circuit 70a of the open circuit exclusion determination unit 29a and the output signal from the abnormality detection circuit 7, and the calculation result is used as the switching relay control signal for opening circuit. Is output to the switching relay 10 for opening. The switching relay control signal for opening is composed of “1” (exclusion) or “0” (connection), and in the case of “1” (exclusion), the switching relay for opening 10 that has received this is not excited. Thus, the contact 10a of the opening switching relay 10 is in a separated state. In this case, since the opening command signal is output from the opening control signal connector 16 via the external jumper line 50 without controlling the timing, the phase control device 1 is excluded from the system. On the other hand, when the signal is ‘0’ (connection), the switching relay for opening 10 that has received the signal is excited, and the contact 10a of the switching relay for opening 10 is in contact. In this case, since the opening command signal is output from the opening control signal connector 16 with the timing controlled via the opening high-speed semiconductor relay 11, the phase control device 1 is connected to the system. .

  Since the logical sum circuit 30a calculates the logical sum of the output signal from the matching circuit 70a of the open circuit exclusion determination unit 29a and the output signal from the abnormality detection circuit 7, at least one of these output signals is calculated. Is “1” (excluded), “1” (excluded) is output as the switching relay control signal for opening. In other words, ‘0’ (connection) is output as the opening switching relay control signal only when any of these output signals is ‘0’ (connection). As described above, when it is necessary to exclude the timing control function from the state of the peripheral device 70, when the abnormality detection circuit 7 detects an abnormality, a '1' (exclusion) signal is output to the opening switching relay 10. I am doing so. Since the OR circuit 30a outputs a control signal to the opening switching relay 10, the OR circuit 30a functions as a switching control unit that controls the switching unit.

  The logical sum circuit 30b is the same as the logical sum circuit 30a, and calculates the logical sum of the output signal from the collation circuit 70b of the closing exclusion determination unit 29b and the output signal from the abnormality detection circuit 7, The calculation result is output to the closing switching relay 12 as a closing switching relay control signal. As with the switching relay control signal for opening, the switching relay control signal for closing is composed of “1” (exclusion) or “0” (connection), and in the case of “1” (exclusion), this is received. The closing switching relay 12 is not excited, and the contact 12a of the closing switching relay 12 is separated. In this case, since the closing command signal is output from the closing control signal connector 19 via the external jumper line 51 without controlling the timing, the phase control device 1 is excluded from the system. On the other hand, when the signal is ‘0’ (connection), the closing switching relay 12 that receives the signal is excited, and the contact 12a of the closing switching relay 12 is in contact. In this case, since the closing command signal is output from the closing control signal connector 19 with the timing controlled via the closing high-speed semiconductor relay 13, the phase control device 1 is connected to the system. .

  Since the logical sum circuit 30b calculates the logical sum of the output signal from the collation circuit 70b of the closing exclusion determination unit 29b and the output signal from the abnormality detection circuit 7, at least one of these output signals is calculated. If the output signal is “1” (exclusion), “1” (exclusion) is output as the switching relay control signal for closing. In other words, only when these output signals are “0” (connection), “0” (connection) is output as the closing switching relay control signal. As described above, when it is necessary to exclude the timing control function from the state of the peripheral device 70, when the abnormality detection circuit 7 detects an abnormality, a '1' (exclusion) signal is output to the closing relay 10. I am doing so. Since the OR circuit 30b outputs a control signal to the closing switching relay 10, the OR circuit 30b functions as a switching control unit that controls the switching unit.

  Next, the configuration of the circuit breaker 60 will be described. The circuit breaker 60 includes an opening coil 61, an opening interlock circuit 62, a closing coil 63, and a closing interlock circuit 64, which have the same configuration as shown in FIG. Therefore, the same components are denoted by the same reference numerals, and detailed description thereof is omitted. The interlock circuits 62 and 64 are respectively connected to the negative side (N side) of the control power supply.

  Next, the opening operation of the phase control device 1 will be described. In addition, although description is abbreviate | omitted about closing operation, it can explain similarly to closing operation.

  The signal state reading circuit 27 reads the state information of the peripheral device 70 and outputs the read state information to the open time exclusion determination unit 29a and the close time exclusion determination unit 29b.

  In the collation circuit 70a of the open time exclusion determination unit 29a, the state information from the signal state reading circuit 27 and the exclusion condition from the exclusion condition storage circuit 28a are compared and collated. If the comparison results match, the signal '1' (exclusion) is output to the OR circuit 30a. If the comparison results do not match, the signal '0' (connection) is output to the OR circuit 30a. Output.

  On the other hand, the abnormality detection circuit 7 outputs a signal “1” (exclusion) to the OR circuit 30a and the OR circuit 30b when an abnormality is detected, and a signal “0” (connection) when no abnormality is detected. Is output to the OR circuit 30a and the OR circuit 30b.

  The logical sum circuit 30a calculates the logical sum of the output signal from the collation circuit 70a of the open circuit exclusion determination unit 29a and the output signal from the abnormality detection circuit 7, and uses the calculated result as the switching relay control signal for opening circuit. Is output to the switching relay 10 for opening.

  When receiving the signal “1” (excluded), the opening switching relay 10 is not excited, and the contact 10a of the opening switching relay 10 is in a separated state. In this case, the opening command signal is output from the opening control signal connector 16 via the external jumper line 50 without controlling the timing. Further, the opening switching relay 10 is energized when receiving the signal ‘0’ (connection), and the contact 10 a of the opening switching relay 10 is in contact. In this case, the opening command signal is output from the opening control signal connector 16 with the timing controlled via the opening high-speed semiconductor relay 11. Note that the operation in the case of opening by controlling the timing and in the case of opening without controlling the timing are the same as the operation of the phase control device 150 in FIG.

  According to the present embodiment, the condition (exclusion condition) regarding the state of the peripheral device 70 when excluding the timing control function is stored in the exclusion condition storage unit (exclusion condition storage circuits 28a and 28b) in advance. When the state information of the device 70 is read into the phase control device 1 and the state information matches the exclusion condition, a process that does not control the opening / closing timing by the timing non-control unit (external jumper lines 50 and 51) is performed. When the information and the exclusion condition do not match, a process in which the timing control unit 80 controls the opening / closing timing can be performed. In this manner, the timing control function can be easily excluded according to the state of the peripheral device 70, and the optimum system configuration can be easily selected.

  Further, when excluding the timing control function, since the external jumper lines 50 and 51 are used as the exclusion circuit, it is not necessary to configure a large external circuit and rearrange it, and it is easily excluded with a simple configuration. Can do.

  Further, when an abnormality occurs in the phase control device 1 and the abnormality detection circuit 7 detects the abnormality, a process that does not control the opening / closing timing by the timing non-control unit (external jumper lines 50 and 51) is selected. Thereby, the phase control device 1 is excluded from the system, and an abnormality occurring inside the phase control device 1 does not adversely affect the peripheral device 70.

  Further, when excluding the timing control function, it is not necessary for a person to work near the high voltage apparatus.

  Moreover, when excluding the timing control function, it is not necessary to take a power failure of the peripheral device 70 or the phase control device 1, and the power system is not affected.

  Moreover, since the phase control apparatus 1 can be easily realized by, for example, a commercially available one-chip microcomputer, it is inexpensive and can flexibly cope with the system.

  In the present embodiment, the opening and closing exclusion conditions are separated into an exclusion condition storage circuit 28a of the opening exclusion determination unit 29a and an exclusion condition storage circuit 28b of the closing exclusion determination unit 29b, respectively. For example, if the condition that the opening control is not performed in any state of the peripheral device 70 is set in the exclusion condition storage circuit 28a, a system that performs only the closing control can be constructed.

  In the present embodiment, the OR circuits 30a and 30b are used as the switching control unit. However, the present invention is not limited to this, and a switching control unit having other functions is used according to the configuration of the phase control device 1. You can also. For example, a priority order is set in advance for the input signal to be input to the switching control unit, and based on this priority order, the content of the input signal having the highest priority order is given priority and the switching relay control signal for opening or closing is closed. It can also be output as a pole switching relay control signal.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing a configuration of the phase switching device according to the present embodiment. The phase control device 2 according to the present embodiment includes a communication circuit 32 in addition to the configuration of the phase control device 1 according to the first embodiment (see FIG. 3). In FIG. 4, a personal computer (personal computer) 31 is installed outside the phase control device 2, and this personal computer 31 can transmit and receive messages to and from the phase control device 2 via the communication circuit 32. The communication circuit 32 functions as a communication processing unit of the phase control device 2. In FIG. 4, the same components as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  A telegram for excluding the phase control device 2 (ie, excluding the timing control function) is transmitted from the personal computer 31 to the phase control device 2 by remote control. When the communication circuit 32 receives this message and interprets the contents, the communication circuit 32 switches to a circuit configuration for excluding the timing control function (that is, to perform processing using the timing non-control unit). Exclusion) is output to the OR circuits 30a and 30b. In the OR circuit 30 a, at least the signal ‘1’ (exclusion) is input from the communication circuit 32, so the signal ‘1’ is output to the opening switching relay 10 as the opening switching relay control signal. The same applies to the OR circuit 30b. Thereby, opening or closing is performed without controlling the opening / closing timing.

  In the present embodiment, the contents of the exclusion condition storage circuits 28a and 28b can be rewritten from the personal computer 31. That is, when the exclusion condition is transmitted as a message from the personal computer 31, the communication circuit 32 can receive the message, interpret the contents thereof, and rewrite the contents of the exclusion condition storage circuits 28a and 28b.

  According to the present embodiment, by providing the phase control device 2 with the communication circuit 32, the timing control function of the phase control device 2 can be excluded by remote control. Therefore, it is not necessary for a person to switch circuits in order to exclude the timing control function in the vicinity of the apparatus.

  In addition, since the contents of the exclusion condition storage circuits 28a and 28b can be rewritten by remote operation, a flexible system can be configured.

  FIG. 5 is a block diagram showing a configuration of the power switching device described in Patent Document 1. In FIG. 5, the main circuit 100, the circuit breaker 200 connected to this main circuit 100, the operating device 300 of this circuit breaker 200, and the phase control apparatus 400 are shown.

  Next, components of the phase control device 400 will be described. The interelectrode voltage detection means 101 detects the interelectrode voltage of the circuit breaker 200. The main circuit current measuring unit 102 detects the current of the main circuit 100. The zero point detecting means 103 obtains the zero time of the interpole voltage and the main circuit current from the voltage signal and the current signal detected by the interpole voltage measuring means 101 and the main circuit current measuring means 102, and always detects the interpole voltage and the main circuit. The latest zero time for the current is stored.

  The operation time predicting means 104 predicts the closing time or opening time of the circuit breaker 200. When the control signal output unit 105 detects the closing command or the opening command, the latest zero point stored in the zero point detecting unit 103 so as to perform the closing or opening at a desired phase of the interelectrode voltage or the main circuit current. A delay time is obtained based on the predicted closing time or the predicted opening time obtained by the time and operation time predicting means 104, and the closing control signal or the opening control signal is output after the delay time has elapsed.

  The operation time measuring means 141 is linked with the movable contactor based on the operation time of the auxiliary switch 201 that operates simultaneously with the contact of the contactor during the closing operation and the opening during the opening operation. Find the opening time. The environmental temperature measuring means 142 measures the environmental temperature around the circuit breaker 200, and the control voltage measuring means 143 measures the control voltage.

  Such a configuration of the conventional phase control device 400 is not configured to exclude the phase control device 400 from the system and disconnect it from the peripheral device according to the state of the peripheral device or the internal state of the phase control device 400. . Therefore, in order to exclude the phase control device 400 from the system, it is necessary to rearrange the circuit by providing a large exclusion circuit outside.

  Even if such an exclusion circuit is provided, it is necessary for a person to work in the vicinity of the apparatus in order to switch the circuit.

  Furthermore, when switching circuits, it is necessary to take a power failure of peripheral devices and phase control devices, which may affect the power system.

  According to Embodiments 1 and 2 of the present invention, such conventional problems can be solved.

1 is a block diagram illustrating a schematic configuration of a phase control device according to a first embodiment. It is a block diagram which shows an example of a structure of the conventional phase control apparatus. 3 is a block diagram illustrating an example of a configuration of a phase control device according to Embodiment 1. FIG. FIG. 6 is a block diagram illustrating a configuration of a phase control device according to a second embodiment. It is a block diagram which shows the structure of the electric power switch apparatus of patent document 1. FIG.

Explanation of symbols

1, 2 Phase control device 6 Delay circuit 7 Abnormality detection circuit 10 Opening switching relay 11 Opening high-speed semiconductor relay 12 Closing switching relay 13 Closing high-speed semiconductor relay 14 Opening command signal connector 15 Open Polarity command bypass connector 16 Opening control signal connector 17 Closing command signal connector 18 Closing command bypass connector 19 Closing control signal connector 27 Signal state reading circuit 28a Exclusion condition memory circuit 28b Exclusion condition memory circuit 29a Open Exclusion judgment part 29b Closure exclusion judgment part 30a OR circuit 30b OR circuit 31 PC 32 Communication circuit 50, 51 External jumper wire 60 Breaker 61 Opening coil 62, 64 Interlock circuit 63 Closed coil 70 Peripheral Equipment 70a Verification circuit 70b Verification circuit

Claims (5)

In a phase control device capable of opening or closing the circuit breaker at a target phase of a main circuit current or a voltage between electrodes set in advance, and controlling the switching timing of the circuit breaker,
A timing control unit for controlling the opening / closing timing by setting the opening command signal as the opening control signal after the delay time has elapsed, or outputting the closing command signal as the closing control signal after the delay time has elapsed,
A timing non-control unit that does not control the opening and closing timing by outputting the opening command signal as it is as an opening control signal, or by outputting the closing command signal as it is as a closing control signal to the circuit breaker,
A switching unit capable of switching between a process for controlling the opening and closing timing by the timing control unit and a process for not controlling the opening and closing timing by the timing non-control unit;
A status information reading unit for reading peripheral device status information;
An exclusion condition storage unit that stores conditions about the state of the peripheral device when excluding the timing control function;
A process of comparing and comparing the read state information with the condition stored in the exclusion condition storage unit, and when the comparison result matches, a process of not controlling the switching timing by the timing non-control unit with respect to the switching unit When the comparison result does not match, the collation unit instructing the switching unit to switch to the process for controlling the opening / closing timing by the timing control unit,
A phase control device comprising:   The timing non-control unit is configured by an external connection attached to the phase control device, and the external connection bypasses the signal path of the opening command signal or the closing command signal to the timing control unit. The phase control apparatus according to claim 1, wherein the phase control apparatus is provided. When an abnormality inside the phase control device is detected, the switching unit is instructed to switch to a process that does not control the opening / closing timing by the timing non-control unit, and when no abnormality is detected, the switching unit An abnormality detection unit that instructs switching to processing for controlling the opening and closing timing by the timing control unit,
A switching instruction to the switching unit by the verification unit and a switching instruction to the switching unit by the abnormality detection unit are input, and at least one of these instructions instructs processing by the timing non-control unit. If it is, the switching control unit for instructing the switching unit to perform processing by the timing non-control unit, otherwise, the switching control unit for instructing the switching unit to perform processing by the timing control unit;
The phase control apparatus according to claim 1, further comprising: A communication processing unit capable of transmitting and receiving messages to and from a computer installed outside the phase control device;
When a message instructing processing by the timing non-control unit is transmitted from the computer to the phase control device, the communication processing unit that has received the message transmits the switching unit to the switching unit by the timing non-control unit. The phase control apparatus according to claim 3, wherein processing is instructed.   When a message instructing rewriting of the contents of the exclusion condition storage unit is transmitted from the computer to the phase control device, the communication processing unit that has received the message rewrites the contents of the exclusion condition storage unit based on the rewriting instruction. The phase control apparatus according to claim 4.

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