JP2009251818A - Apparatus and method for writing data for ic chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and a method for writing data for IC chips capable of increasing the speed of processes while solving security problems with a method of subtracting from a retry counter prior to processing even if a caching system is employed for a multi-application IC card having a virtual machine incorporated therein, and guaranteeing the security of the IC card. <P>SOLUTION: The apparatus for writing data for IC chips includes a virtual machine, a processing unit for processing designated data in response to instructions from the virtual machine, a cache memory for temporarily accumulating the data processed by the processing unit, and a nonvolatile memory for writing data output from the cache memory, in response to writing instructions from the processing unit. When processing computations about secret information, the processing unit writes the data accumulated in the cache memory to the nonvolatile memory prior to execution of the computations. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an IC chip mounted on an IC (Integrated Circuit) card, and more particularly to a technique for writing data to a nonvolatile memory in the IC chip.

  Conventionally, it is known that the processing speed of writing data to a nonvolatile memory (for example, EEPROM) in an IC chip has become a bottleneck of the processing speed of the entire IC chip. For this reason, a system that caches the writing process to the nonvolatile raw memory is known (see, for example, Patent Document 1 and Patent Document 2). The speed of one write process to the non-volatile memory is constant regardless of the data capacity to be written, and the data capacity to be written is gathered to some extent, rather than executing multiple times of writing the small capacity data. It is possible to reduce the number of times to write to speed up the processing.

  By the way, in general, in a process for ensuring security, for example, a comparison process related to authentication of a password or the like, internal data stored inside is compared with external data input from the outside, and if they match, the authentication is successful. Although the process proceeds to the next process, if they do not match, the comparison process is retried until the preset number of retries (restricted number) is reached as an authentication failure. Here, the number of retries may be the “number of retries” or the “number of retries”.

  The number of times the comparison process is retried is managed by, for example, a retry counter that is decremented by 1 each time the retry is performed, and the value of the retry counter is stored in the nonvolatile memory. In general, the retry counter is subtracted before the comparison process. This is because in the method in which the retry counter is subtracted after the comparison process, if the power supply is cut off after the comparison process and before the retry counter value is written to the nonvolatile memory, the authentication process fails in the comparison process. This is because the retry counter does not decrease and comparison processing can be executed any number of times.

Conventionally, since the data capacity of a nonvolatile memory (for example, EEPROM) in an IC chip has a very small capacity (for example, several kilobytes), a native IC card in which an application cannot be added / deleted has been mainstream. . However, as disclosed in Patent Document 3, for example, due to recent advances in semiconductor technology, an IC chip having a nonvolatile memory capacity exceeding several tens of kilobytes to over 100 kilobytes has been released. In addition, a multi-application IC card in which a virtual machine having a high-level language interpretation function represented by JAVA (registered trademark) is incorporated and an application can be added / deleted is becoming widespread.
JP 2001-147855 A JP 2007-034344 A JP 2007-206765 A

  However, when the caching system is used in a multi-application IC card in which the above-described virtual machine is incorporated, in the method in which the retry counter is subtracted before the comparison process, the program performs an unintended operation. Will occur. For example, if the power supply is cut off before the data is written back from the cache to the nonvolatile memory, there is a problem that the value of the retry counter in the nonvolatile memory does not decrease when authentication fails. This is the same not only in the comparison process but also in other processes for ensuring security.

  Therefore, the present invention has been made in view of such problems and the like, and even when a caching system is adopted for a multi-application IC card in which a virtual machine is incorporated, the retry counter is processed. An object of the present invention is to provide an IC chip data writing apparatus and a data writing method capable of accelerating the processing while eliminating security problems in the previous method and ensuring the security (safety) of the IC card. And

  In order to solve the above-mentioned problem, the invention according to claim 1 is directed to a virtual machine, a processing unit that processes data specified by receiving a command from the virtual machine, and temporarily processes data processed by the processing unit. An IC chip data writing device comprising: a cache memory for storing data; and a nonvolatile memory for writing data output from the cache memory in response to a write command from the processing unit, wherein the processing unit includes: When processing an operation related to secret information, data stored in a cache memory is written to a nonvolatile memory before the operation is executed.

  The invention according to claim 2 is the IC chip data writing device according to claim 1, wherein the processing relating to the secret information is an arithmetic processing for performing comparison processing or cryptographic processing for ensuring security. It is characterized by being.

  The invention according to claim 3 is a virtual machine, a processing unit that processes data specified by receiving an instruction from the virtual machine, a cache memory that temporarily stores data processed by the processing unit, A data writing method in a data writing device for an IC chip, comprising: a non-volatile memory that writes data output from the cache memory in response to a write command from the processing unit, wherein the processing unit performs an operation related to secret information Is processed, the data stored in the cache memory is written into the nonvolatile memory before the calculation is executed.

  According to the present invention, the processing unit is configured to write the data accumulated in the cache memory before executing the calculation when processing the calculation related to the secret information. Even when it is employed in a multi-application IC card with a built-in virtual machine, it is possible to eliminate the security problem and to speed up the processing while ensuring the security of the IC card.

  Hereinafter, the best embodiment of the present invention will be described in detail with reference to the drawings. The embodiment described below is an implementation when the present invention is applied to an IC chip mounted (embedded) in an IC card used as a cash card, credit card, membership card, employee card, student card, or the like. It is a form.

  First, the configuration and function of an IC chip according to an embodiment of the present invention will be described with reference to FIG.

  FIG. 1 is a diagram illustrating a hardware configuration example of an IC chip according to the present embodiment.

  As shown in FIG. 1, an IC chip 1 includes a CPU (Central Processing Unit) 11 having a calculation function, a ROM (Read Only Memory) 12 in which a program and data are stored, a working RAM (Random Access Memory) 13, A nonvolatile memory (for example, EEPROM (Electrically Erasable and Programmable Read Only Memory)) 14 and an I / O circuit 16 for data communication with an external device are configured. A cache memory 15 for caching the writing process to the nonvolatile raw memory 14 is assigned to a predetermined storage area of the RAM 13. Note that data communication with an external device via the I / O circuit 16 may be either a contact method or a non-contact method.

  FIG. 2 is a diagram illustrating a software configuration example based on the hardware illustrated in FIG.

  As shown in FIG. 2, an application 11a and a VM (also referred to as a virtual machine or a virtual machine) 11b operate on the OS 11d. The VM 11b is an interpreter that converts a program language into a machine language and executes it.

  The application 11a is described in a program language such as JAVA (registered trademark), for example, and the VM 11b receives a process according to a command from the application 11a, and receives a write processing unit (a processing unit that is a write control engine) 11c (a processing unit). In one example), a process for issuing a write command is executed. The write processing unit 11c is configured to process specified data in response to an instruction from the VM 11b.

  The cache memory 15 temporarily accumulates data processed by the write processing unit (processing unit that is a write control engine) 11c, and the nonvolatile memory 14 writes data from the VM 11b (hereinafter referred to as “write back”). ) The data output from the cache memory 15 is written in response to the command. This is intended to speed up the processing by reducing the number of times of writing to the nonvolatile memory 14 by collecting the data capacity to be written to some extent by the cache memory 15 having a writing speed faster than that of the nonvolatile memory 14.

  In the present embodiment, the case where the write processing unit 11c executes a comparison process for ensuring security as an example of a calculation process related to secret information is taken as an example. However, the present invention is not limited to this. For example, it may be an arithmetic process for performing an encryption process or the like. Here, the secret information means, for example, information related to a PIN (Personal identification number) and a key.

  Then, in response to an instruction from the VM 11b, for example, the write processing unit 11c performs a comparison process related to authentication of a password or the like, for example, data stored in the cache memory 15 (for example, The remaining number of retries of the comparison process (an example of information related to the number of processes) is written (write back) in the non-volatile memory 14. This enables the power supply even though the comparison process is performed and the authentication fails. It can be prevented that the value of the retry counter does not decrease due to the supply interruption, and it can be avoided that the comparison process can be executed any number of times.

  In the comparison process, for example, a password input from an external device via the I / O circuit 16 is compared with a password stored in advance in the IC chip 1 (for example, the nonvolatile memory 14). If both match, it is processed as authentication success, and if both do not match, it is processed as authentication failure.

  FIG. 3 is a sequence diagram illustrating an operation example when the comparison process is successful.

  First, in the operation example of FIG. 3, first, when the comparison process is started, the application 11a gives an instruction to decrement the retry counter by 1 to the VM 11b (step S1). In response to this instruction, the VM 11b gives a command to the cache memory 15 to decrease the retry counter (retry count is defined) by 1 (step S2), and sets the value of the retry counter to “N” (N is a natural number) → “N−1”. (That is, the remaining number of retries for the comparison process is accumulated).

  Next, the application 11a gives an instruction to execute the comparison process to the VM 11b (step S3). In response to this instruction, the VM 11b (write processing unit 11c) gives a write back command to the cache memory 15 to the cache memory 15, and sets the value of the retry counter (the remaining number of retries) stored in the cache memory 15. The included data is written back to the nonvolatile memory 14 (step S4). Thus, the value of the retry counter stored in the cache memory 15 is written into the nonvolatile memory 14.

  Thereafter, the VM 11b performs a comparison process (step S5). If the retry counter value stored in the cache memory 15 is written back to the nonvolatile memory 14 after the comparison process, the nonvolatile memory 14 is turned off after the power supply is turned off after the comparison process related to the authentication failure. In the volatile memory 14, the value of the retry counter does not decrease, and comparison processing can be performed any number of times by power restoration (by intentionally turning off the power). In the above embodiment, since the value of the retry counter stored in the cache memory 15 is written back to the nonvolatile memory 14 at the timing before the comparison process, the power supply is cut off after the comparison process related to the authentication failure. However, it is possible to prevent the value of the retry counter from being reduced, and it is possible to avoid that the comparison process can be executed any number of times.

  In the comparison process in step S5, if the authentication is successful, the application 11a gives a retry counter initialization command to the VM 11b (step S6). In response to this instruction, the VM 11b (write processing unit 11c) gives a retry counter initialization command to the cache memory 15 to the cache memory 15 (step S7), and initializes the retry counter value.

  When the application is terminated, the VM 11b (write processing unit 11c) gives a write back command to the cache memory 15 to the cache memory 15, and stores the data including the retry counter value stored in the cache memory 15 in a nonvolatile manner. Write back to the memory 14 (step S8).

  On the other hand, FIG. 4 is a sequence diagram showing an operation example when the comparison process fails. In this case, the processes from Steps S10 to S14 are the same as Steps S1 to S5 in FIG. Processing corresponding to step S6 and subsequent steps is not performed.

  As described above, according to the above embodiment, the VM 11b, the write processing unit 11c that receives the command from the VM 11b and processes the specified data, and the data processed by the write processing unit 11c are temporarily stored. A cache memory 15 and a non-volatile memory 14 that writes data output from the cache memory 15 in response to a write command from the write processing unit 11c. The write processing unit 11c is, for example, a comparison process for ensuring security. When processing an operation related to secret information such as, the data stored in the cache memory 15 is written to the nonvolatile memory 14 before the operation is executed, so the retry counter is subtracted before the processing. Multi-application IC card with built-in virtual machine Even when employing a de eliminates a security problem, while ensuring the IC card security (safety), it is possible to speed up the process.

It is a figure which shows the hardware structural example of the IC chip which concerns on this embodiment. It is a figure which shows the example of a software structure on the assumption of the hardware shown in FIG. It is a sequence diagram which shows the operation example when a comparison process is successful. It is a sequence diagram which shows the operation example when a comparison process fails.

Explanation of symbols

1 IC chip 11 CPU
11a application 11b VM
11c Write processing unit 11d OS
12 ROM
13 RAM
14 Nonvolatile memory 15 Cache memory 16 I / O circuit

Claims (3)

In response to a virtual machine, a processing unit that receives a command from the virtual machine, processes specified data, a cache memory that temporarily stores data processed by the processing unit, and a write command from the processing unit A data writing device for an IC chip, comprising: a nonvolatile memory for writing data output from the cache memory;
In the IC chip data writing device, the processing unit writes data stored in the cache memory into the nonvolatile memory before executing the calculation when processing the calculation related to the secret information. The IC chip data writing device according to claim 1,
The IC chip data writing device according to claim 1, wherein the calculation processing relating to the secret information is a calculation processing for performing comparison processing or encryption processing for ensuring security. In response to a virtual machine, a processing unit that receives a command from the virtual machine, processes specified data, a cache memory that temporarily stores data processed by the processing unit, and a write command from the processing unit A data writing method in an IC chip data writing device comprising: a nonvolatile memory for writing data output from the cache memory,
The processing unit writes data accumulated in a cache memory to a nonvolatile memory before executing the calculation when processing the calculation related to secret information.

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