JP2009251205A - Display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device capable of correcting variation of characteristics of drive transistors formed in respective pixels. <P>SOLUTION: The pixel 2 includes the drive transistor Trd outputting a drive current according to a picture signal and a light emitting element EL emitting light at the luminance according to the drive current. The drive transistor Trd includes a pair of current ends connected between a power supply and the light emitting element EL, a channel region between the pair of current ends, a first gate electrode into which a signal is written from a signal line, and a second gate electrode disposed facing the first gate electrode via the channel region. A correction circuit 6 applies a correction electric potential for correcting the variation of the characteristics of the drive transistor Trd to the second gate electrode via a control line CL. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix display device using a light emitting element for a pixel. More specifically, the present invention relates to a technique for correcting variation in threshold voltage of a transistor that drives a light emitting element.

A conventional active matrix display device includes a pixel array portion and a circuit portion. The pixel array section includes row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at portions where each scanning line and each signal line intersect. The circuit unit includes a scanning circuit that selects pixels in units of rows via each scanning line, and a signal circuit that supplies signals to the selected pixels via each signal line. The pixel includes a driving transistor that outputs a driving current in accordance with a signal and a light emitting element that emits light with luminance corresponding to the driving current. An active matrix display device having such a configuration is described in Patent Document 1 below, for example.
JP2007-310311

  The driving transistor formed in each pixel outputs a driving current in accordance with the video signal supplied from the circuit unit, and drives the light emitting element. However, the drive transistor does not necessarily have uniform electrical characteristics and varies among pixels. As a result of this characteristic variation, the drive current varies, and there is a problem in that unevenness occurs in the light emission luminance of the pixels in the pixel array portion, thereby impairing uniformity.

  In view of the above-described problems of the related art, an object of the present invention is to provide an active matrix display device capable of correcting variation in characteristics of drive transistors formed in each pixel. In order to achieve this purpose, the following measures were taken. That is, the display device according to the present invention includes a pixel array unit and a circuit unit, and the pixel array unit intersects row-like scanning lines, column-like signal lines, and each scanning line and each signal line. The circuit unit includes a scanning circuit that selects pixels in units of rows via each scanning line, and supplies a signal to each of the selected pixels via each signal line. Signal circuit. The pixel includes a driving transistor that outputs a driving current in accordance with the signal and a light emitting element that emits light with a luminance in accordance with the driving current, and the driving transistor is connected between a power source and the light emitting element. A pair of current ends, a channel region between the pair of current ends, a first gate electrode to which a signal is written from the signal line, and a second gate facing the first gate electrode with the channel region in between The circuit unit includes a correction circuit that applies a correction potential for correcting variation in characteristics of the drive transistor to the second gate electrode.

  Preferably, the pixel array unit includes a control line for commonly connecting the second gate electrodes of the driving transistors included in each pixel in a row unit or a column unit, and the correction circuit applies a correction potential to each control line. Apply. The drive transistor has a drive current that varies in accordance with variations in threshold voltage characteristics, and the correction circuit applies a correction potential for correcting variations in the threshold voltage to the second gate electrode. The circuit unit including the correction circuit is arranged on the same panel as the pixel array unit, and the correction circuit automatically detects a correction potential for each control line and outputs the detected correction potential. Apply to the corresponding control line. The correction circuit comprises a set of correction units arranged corresponding to each control line, and the correction unit comprises a detection transistor and a resistance element connected in series between a power supply line and a ground line, A control line corresponding to each correction unit is connected to the midpoint of the detection transistor and the resistance element. Alternatively, the correction unit includes a pair of detection transistors and complementary transistors connected in series between a power supply line and a ground line, and a control line corresponding to each correction unit is at the midpoint between the detection transistor and the complementary transistor. Connected. Also, the correction potential is automatically detected by turning on the pair of detection transistors and complementary transistors, and then the pair of detection transistors and complementary transistors are turned off to hold the detected correction potential at the intermediate point and corresponding control. Apply to the wire. The detection transistors are on the same line and have the same size as the drive transistors connected to the corresponding control lines.

  According to the present invention, the driving transistor has a so-called double gate structure (sandwich gate structure). That is, the drive transistor has a first gate electrode and a second gate electrode that face each other with the channel region interposed therebetween. The first gate electrode is directly or indirectly connected to the signal line. On the other hand, the second gate electrode is connected to the correction circuit. This correction circuit corrects variations in characteristics by applying a correction potential to the second gate electrode of each drive transistor. With this configuration, the pixel array unit can eliminate local luminance unevenness and improve uniformity.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic plan view showing a first embodiment of a display device according to the present invention. As shown in the figure, this display device includes a pixel array section 1 and a circuit section. The pixel array unit 1 is formed on the panel 0. A part of the circuit unit is also mounted on the panel 0. The pixel array unit 1 includes row-like scanning lines, column-like signal lines, and matrix-like pixels 2 arranged at portions where each scanning line and each signal line intersect. In the present embodiment, any one of the three primary colors red, green, and blue (RGB) is assigned to the pixel 2 to perform color display. However, the present invention is not limited to a color display device, and includes, for example, a monochrome single-color display device.

  On the other hand, the circuit unit includes a selector 3 and a scanner 4. In this embodiment, the scanner 4 is mounted on the panel 0 and is a scanning circuit that selects the pixels 2 in units of rows via each scanning line. The selector 3 is also mounted on the panel 0 and supplies a video signal to each selected pixel 2 via each signal line. A terminal 9 is formed on the panel 0. The terminal 9 is for supplying a video signal and a control signal from an external circuit unit to the scanner 4 and the selector 3 in the panel.

  Each pixel 2 includes at least a drive transistor Trd and a light emitting element EL. The drive transistor Trd outputs a drive current in accordance with a video signal (hereinafter sometimes simply referred to as a signal) supplied from the selector 3. The light emitting element EL is composed of, for example, a two-terminal type organic electroluminescence element, and emits light with a luminance corresponding to the drive current. The drive transistor Trd includes a pair of current ends (source / drain) connected between the power source and the light emitting element EL, a channel region between the pair of current ends, a first gate electrode, and a second gate electrode. And have. The drive transistor Trd includes a pair of gate electrodes and has a so-called double gate type or sandwich gate structure. The first gate electrode is directly or indirectly connected to the signal line. On the other hand, the second gate electrode faces the first gate electrode with the channel region in between. The circuit unit includes a correction circuit in addition to the selector 3 and the scanner 4 described above. In this embodiment, this correction circuit is provided outside the panel 0. The correction circuit applies a predetermined correction potential to the second gate electrode of each drive transistor Trd. This correction potential corrects the characteristic variation of each drive transistor Trd. As a result, there is no variation in drive current over the entire pixel array unit 0, the light emission luminance of each pixel is made uniform, and the uniformity of the screen can be improved.

  In the present embodiment, the pixel array section 1 has a control line CL in addition to the row-like scanning lines and column-like signal lines described above. The control line CL commonly connects the second gate electrodes of the drive transistors Trd included in each pixel 2 in units of rows. In other words, the control lines CL are arranged in rows in parallel with the scanning lines. Each control line CL is connected to a terminal provided on the outer peripheral portion of the panel 0. A correction circuit outside the panel is connected to these terminals. The correction circuit applies correction potentials Vbg (1) to Vbg (n) to the row-like control lines CL. The numbers shown in parentheses indicate the row numbers of the pixel array unit 1. n represents the last row number. In other words, the pixel array unit 1 is composed of n rows of pixels in this embodiment. In the present invention, since the correction potential is applied to the second gate electrode (back gate electrode) of the drive transistor Trd having a double gate structure, the correction potential may be referred to as a back gate potential (Vbg).

  The drive transistor Trd exhibits various characteristic variations under the influence of the manufacturing process. This includes in particular variations in the threshold voltage of the channel region. In the drive transistor Trd, the drive current fluctuates according to the variation in the threshold voltage of the channel region, and the uniformity of the screen is impaired. Therefore, in this embodiment, in particular, the correction circuit applies the correction potential Vbg for correcting the variation in the threshold voltage of the drive transistor Trd to the second gate electrode (back gate).

  FIG. 2 is a schematic plan view showing a second embodiment of the display device according to the present invention. In order to facilitate understanding, parts corresponding to those in the first embodiment shown in FIG. The difference from the first embodiment is that the control lines CL are arranged in a row so as to be parallel to the signal lines. That is, in this embodiment, the control line CL commonly connects the second gate electrodes (back gate electrodes) of the drive transistors Trd included in each pixel 2 in units of columns. Terminals are arranged on the outer peripheral edge of the panel 0 corresponding to the columns of the control lines CL. A correction potential (back gate potential Vbg) is applied to these terminals from a correction circuit outside the panel. The control line CL is divided into the three RGB primary colors assigned to each pixel 2. M control lines CL are included for each color. The panel 0 includes another terminal 9 in addition to a terminal for connecting to an external correction circuit. The terminal 9 is for supplying a video signal and a control signal from an external circuit unit to the scanner 4 and the selector 3 in the panel.

  FIG. 3 is a graph showing the current-voltage characteristics of the drive transistor included in the embodiment shown in FIG. 1 or FIG. The drive transistor Trd is an N-channel thin film transistor (TFT). The graph represents the relationship between the gate voltage Vgs and the drain current Ids of the N-channel TFT. The gate voltage Vgs represents the voltage of the gate (G) with reference to the source (S), and is applied to the first gate electrode of the drive transistor having a double gate structure. Therefore, it corresponds to the video signal supplied from the selector 3. On the other hand, the drain current Ids is a drive current that flows through a pair of current ends (source / drain) of the drive transistor Trd, and is supplied to the light emitting element.

  As shown in the graph, the threshold voltage characteristics of the individual drive transistors are not always as intended, but vary on the enhancement side or the depletion side. In the case of an N-channel TFT, the threshold voltage Vth shifts to the positive side when the enhanced TFT characteristic is reached, while the threshold voltage shifts to the negative side in the depletion TFT characteristic. Due to such variations in threshold voltage, even if the gate voltage Vgs is constant, the drain current Ids varies, so that the light emission luminance is not necessarily uniform in each pixel, and the uniformity of the screen is impaired. Therefore, in the present invention, the variation in the threshold voltage is removed by applying the correction potential Vbg to the second gate electrode (back gate electrode) of the drive transistor Trd. Specifically, by applying a relatively high back gate potential to the driving transistor having the enhanced TFT characteristics, the characteristics are shifted in the depletion direction, and the threshold voltage characteristics are brought close to the target aimed characteristics. be able to. Conversely, by applying a relatively low back gate potential (correction potential) to the drive transistor having the depletion TFT characteristic, the characteristic can be shifted in the enhancement direction, and the threshold voltage characteristic can be brought close to the target aimed characteristic. it can. In this way, the uniformity of the screen can be improved by matching the threshold voltage of the driving transistor with the target characteristic over the entire screen.

  Hereinafter, the background, configuration, operation and effect of the present invention will be described in detail with reference to FIGS. FIG. 4 is a schematic plan view illustrating a typical configuration example of the display device. As shown in the figure, the pixel array section 1 includes row-like scanning lines WS, column-like signal lines SL, and matrix-like pixels 2 arranged at the intersections of the scanning lines WS and the signal lines SL. including. The scanner 4 selects the pixels 2 in units of rows via each scanning line WS. The selector 3 supplies a signal to the selected pixel 2 via each signal line SL.

  The pixel 2 includes a sampling transistor Tr1, a drive transistor Trd, and a light emitting element EL. The sampling transistor Tr1 and the drive transistor Trd are N-channel TFTs. One current end of the sampling transistor Tr1 is connected to the signal line SL. The other current end is connected to the gate of the drive transistor Trd. The gate of the sampling transistor Tr1 is connected to the scanning line WS. The drain which is one current end of the drive transistor Trd is connected to the power supply Vccp. The source which is the other current end of the driving transistor Trd is connected to the anode of the light emitting element EL. The cathode of the light emitting element EL is connected to the ground potential. That is, this ground potential is the cathode potential Vcath. As described above, the first gate electrode serving as the control terminal of the drive transistor Trd is connected to the signal line SL via the sampling transistor Tr1.

  FIG. 5 is a schematic diagram for explaining the operation of the pixel 2 shown in FIG. As shown in the figure, the sampling transistor Tr1 is turned on when selected by the scanning line WS, samples the video signal Vsig from the signal line SL, and writes it to the gate G of the drive transistor Trd. The drive transistor Trd outputs a drain current Ids according to the gate voltage Vgs written to the gate G. The light emitting element EL emits light with a luminance corresponding to the drain current (drive current) Ids. At this time, the drive current Ids flows from the power supply Vccp to the ground line (cathode potential Vcath) through the series connection of the drive transistor Trd and the light emitting element EL.

  As shown in the graph of FIG. 5, the current I and the luminance L of the light emitting element EL are in a proportional relationship. That is, as the current I supplied from the drive transistor Trd increases, the luminance L of the light emitting element EL increases. The drive current Ids is controlled by the gate voltage Vgs. The gate voltage Vgs corresponds to the video signal Vsig. Therefore, the pixel 2 controls the luminance L of the light emitting element in accordance with the video signal Vsig (that is, a data voltage representing gradation), and is a voltage program-current drive type.

  The drive transistor Trd incorporated in the voltage program-current drive type pixel 2 operates in a saturation region, and outputs the drive current Ids according to the transistor characteristic equation shown in FIG. As is apparent from the transistor characteristic equation, when the driving transistor Trd operates in the saturation region, the drain current Ids starts flowing when the gate voltage Vgs exceeds the threshold voltage Vth, and the drain current Ids increases as the gate voltage Vgs increases thereafter. Will increase. Note that the coefficient β included in the transistor characteristic formula is a constant determined by the parameters W, L, μ, and Cox. Here, W represents the channel width of the drive transistor Trd, L represents the channel length, μ represents the mobility, and Cox represents the unit capacitance of the gate oxide film.

  As is clear from the above description, the voltage program-current drive type pixel circuit shown in FIG. 5 writes the video signal Vsig supplied from the selector (source driver) to the node G and sets the drive transistor Trd in the saturation region. By operating it, it is used as a current source. On the other hand, the luminance of the light emitting element EL connected to this current source is proportional to the current. In this manner, the drive transistor Trd plays a role of converting the signal Vsig (data voltage) into a light emission current. The video signal Vsig (data voltage) has a level corresponding to the gradation. Since Vsig and Vgs correspond, the luminance of the light emitting element EL can be controlled in gradation.

  As shown in the transistor characteristic formula of FIG. 5, if there is no variation in the threshold voltage Vth and the parameter β, Ids can be accurately obtained according to the gate voltage Vgs, and therefore, there is no variation in the light emission luminance of each pixel. However, actually, due to the influence of the manufacturing process, the threshold voltage Vth and the mobility μ in the parameter β vary, and the uniformity of the screen is disturbed.

  FIG. 6 is a schematic diagram showing a manufacturing process of a thin film transistor (TFT). The element region of the thin film transistor is, for example, a polycrystalline silicon thin film. Polycrystalline silicon is obtained by annealing a thin film of amorphous silicon (hereinafter sometimes referred to as amorphous silicon) by irradiating it with laser light. FIG. 6 is a schematic diagram showing this laser annealing process. The laser light emitted from the excimer laser is reflected by the mirror M1, and then passes through the variable attenuator. Thereafter, the optical path is bent by the mirror M2, and shaped into a line beam LB through a beam shaper, a homogenizer, a field lens, a mirror M3, and a projection lens. The line beam LB passes through the vacuum chamber window and irradiates the glass substrate 100. An amorphous silicon thin film is formed on the glass substrate 100 in advance, and is converted into polycrystalline silicon by irradiating it with a line beam LB.

  As shown in the drawing, the line beam LB has a strip shape having a major axis and a minor axis. By irradiating the line beam LB to the substrate 100 while shifting in the minor axis direction, the amorphous silicon on the entire surface of the substrate 100 can be converted into polycrystalline silicon. In the actual process, irradiation is performed while the position of the line beam LB is fixed and the substrate 100 is slid and shifted.

  Although the intensity of the line beam LB is adjusted to be always constant, the intensity actually varies with time. As a result, the crystal variation of the polycrystalline silicon occurs, and as a result, the characteristics of the thin film transistor vary. This variation in TFT characteristics causes a decrease in uniformity of the display device.

  FIG. 7 is a photograph showing the display state of the pixel array unit 1. FIG. 7 is a photograph of the screen of panel 0 taken. As described above, in the laser annealing, the strip-shaped line beam LB is intermittently applied to the substrate that becomes the panel 0. By repeating the process of irradiating the line beam LB while shifting the substrate in the minor axis direction, the amorphous silicon on the entire surface of the substrate can be polycrystallized. Since the line beam varies in energy every time it is irradiated, a difference in TFT characteristics occurs for each irradiation region of the line beam LB. In the line beam LB, there is some energy distribution along the long axis direction, but since this is continuous, there is no significant influence. Since the TFT characteristic variation along the long axis direction is continuous, the unevenness of the light emission luminance also has a gradation and is not visually noticeable. On the other hand, since the TFT characteristics change discontinuously at the boundary of the line beam LB that overlaps along the minor axis direction, the variation in TFT characteristics also becomes discontinuous. For this reason, the difference in brightness is recognized as a horizontal streak on the screen and becomes noticeable. In the panel photograph in the figure, a horizontal stripe along the long axis direction of the line beam LB appears, which causes the uniformity of the panel 0 to decrease.

  FIG. 8 is a schematic cross-sectional view showing a configuration of a thin film transistor TFT having a polycrystalline silicon thin film as an element region. The upper side represents a TFT having a bottom gate structure, and the lower side represents a TFT having a top gate structure. Both are used as a pixel drive transistor Trd.

  In the bottom gate structure, a gate electrode G is formed on a substrate 100, and a polycrystalline silicon film 102 is formed thereon via a gate insulating film 101. As described above, this polycrystalline silicon thin film 102 has been converted from amorphous silicon by laser annealing. The polycrystalline silicon film 102 is divided into a channel region located immediately above the gate electrode G, and a source region S and a drain region D located on both sides thereof. The polycrystalline silicon film 102 is covered with an interlayer insulating film 103, on which a source electrode S and a drain electrode D are formed.

  In the top-gate driving transistor Trd, a polycrystalline silicon film 102 is formed on a substrate 100 via a base film 104. A gate electrode G is formed thereon via a gate insulating film 101. The gate electrode G is covered with an interlayer insulating film 103, and a source electrode S and a drain electrode D are formed thereon.

In any structure, the channel region of the drive transistor Trd is formed of the polycrystalline silicon film 102 and is affected by fluctuations in the laser annealing process. Specifically, the threshold voltage Vth and mobility μ of the channel region vary for each pixel. More specifically, the threshold voltage Vth and mobility μ of the drive transistor vary depending on the relationship corresponding to the line beam irradiation region. As is clear from the transistor characteristic equation shown in FIG. 5, when Vth and μ vary, the drive current varies, so that a difference occurs in the light emission luminance of the pixels. Since this emission luminance difference appears along the long axis direction of the line beam, it appears as a streak on the screen. The transistor characteristic equation includes channel width W, channel length L, gate oxide unit capacitance Cox, etc. as parameters in addition to Vth and μ, but these are related to the film formation process and the exposure process. Although it causes local unevenness, it cannot cause streaks.
In addition, since the unevenness related to these processes is a continuous change, the characteristic does not change discontinuously like a streak. It is the discontinuous characteristic change that causes the uniformity to deteriorate most, and this is caused by ELPS (Excimer Laser Annealing) of LTPS (Low Temperature Polysilicon) process.

  As is clear from the above description, in order to improve the uniformity of the screen, it is necessary to suppress variations in the threshold voltage Vth and mobility μ of the individual drive transistors. However, when amorphous silicon is converted to polycrystalline silicon using a laser annealing process, variations in TFT characteristics appearing at the boundary of the line beam cannot be suppressed. Therefore, a means for correcting such characteristic variation is necessary. For this purpose, the present invention employs a thin film transistor having a double gate structure for the drive transistor Trd. FIG. 9 is a schematic cross-sectional view showing the drive transistor Trd having the double gate structure. As shown in the figure, a first gate electrode G is formed on the substrate 100. A polycrystalline silicon film (hereinafter sometimes referred to as a polysilicon film) 102 is formed thereon with a gate insulating film 101 interposed therebetween. A second gate electrode (back gate electrode) BG is formed thereon via an interlayer insulating film 103. That is, the interlayer insulating film 103 is a gate insulating film between the channel region of the polysilicon film 102 and the second gate electrode BG. A source electrode S and a drain electrode D are also formed on the interlayer insulating film 103. The first gate electrode G and the second gate electrode BG are opposed to each other with the channel region of the polysilicon film 102 in between.

  The threshold voltage Vth and mobility μ of the channel region vary from line to line under the influence of the laser annealing process. The influence of μ variation on the Vth variation is about 1/10. Therefore, in order to improve the uniformity of the screen, Vth correction is important. The threshold voltage Vth can be corrected by the gate electric field. Therefore, in the present invention, the double gate structure shown in FIG. 9 is adopted, and a correction potential (back gate potential) for correcting variation in threshold voltage is applied to the second gate electrode BG. In the double gate structure of FIG. 9, the sizes of the first gate electrode G and the second gate electrode BG are made to be the same as the channel region. However, the present invention is not limited to this, and the size of the back gate electrode BG can be set within a range in which the threshold voltage Vth of the drive transistor Trd can be adjusted.

  FIG. 10 is a circuit diagram of a transistor having a double gate structure. The left side is an N channel type, and the right side is a P channel type. In any case, the first gate electrode G and the second gate electrode BG are disposed to face the channel portion located between the pair of current ends (source region S and drain region D). As shown in the schematic diagram above the circuit diagram, the polysilicon film PS is divided into a source region S and a drain region D and a channel region (channel portion) therebetween. A first gate electrode (Gate1) is disposed below the channel portion, while a second gate electrode (Gate2) is disposed above the channel portion. The first gate electrode Gate1 controls the conduction state (electric resistance) of the channel portion. On the other hand, the second gate electrode Gate2 adjusts the threshold voltage of the channel portion by an electric field applied to the channel portion.

  FIG. 11 is a circuit diagram and a characteristic graph for explaining the operation of the double gate transistor. As shown in the figure, a predetermined potential is applied to the drain D, the first gate G, and the second gate BG of the double-gate transistor with reference to the source S to determine the state of the channel portion. A gate voltage Vgs is applied to the first gate electrode G. As described above, the gate voltage Vgs corresponds to the video signal, and controls the current Ids flowing between the source S and the drain D. The voltage Vds applied between the source S and the drain D is set to have a sufficient voltage width so that the drive transistor Trd operates in the saturation region. Finally, the back gate voltage Vbgs applied to the second gate electrode BG is a correction potential according to the present invention, and suppresses variations in the threshold voltage Vth in the channel region.

  In the case of an N-channel TFT (NMOS), the NMOS characteristics change from the depletion side to the enhancement side by changing the back gate potential Vbgs from the high level Hi to the low level Lo. Thus, by applying an appropriate correction potential Vbgs to the back gate of the drive transistor, the threshold voltage Vth of the drive transistor can be brought close to a predetermined target value.

  Also in the case of a P-channel transistor (PMOS), when the back gate potential Vbgs is changed from the low level Lo side to the high level Hi side, the PMOS transistor characteristics change from the depletion side to the enhancement side. By appropriately setting Vbgs, the threshold voltage Vth of each PMOS transistor can be set to a target value.

  Most variations in TFT characteristics are Vth variations. Therefore, Vth variation can be corrected by using the Vth shift by the back gate. In an actual TFT, μ variation is about 1/10 of Vth variation. If the Vth variation is 10%, the μ variation is about 1%. Since the human luminance difference visual recognition ability is 1% or more, if the Vth variation is corrected to 1% or less over the entire screen according to the present invention, the image quality uniformity can be improved to a level that is practically no problem. In other words, by appropriately controlling the correction potential applied to the back gate of the drive transistor, the Vth variation of the drive transistor is kept within 1%.

  FIG. 12 is a schematic plan view showing a third embodiment of the display device according to the present invention. Portions corresponding to those in the first embodiment shown in FIG. 1 are given corresponding reference numbers for easy understanding. The difference from the first embodiment is that the driving transistor of each pixel 2 is not an N-channel type but a P-channel type. This P-channel type drive transistor Trd is also a TFT having polysilicon as an element region. This polysilicon is obtained by converting amorphous silicon into polysilicon by laser annealing. The second gate electrodes (back gate electrodes) of the drive transistors Trd are commonly connected by a control line CL. The control line CL is arranged in parallel with the row of the pixels 2. The major axis direction of the line beam used for laser annealing is also set in parallel with the row direction of the pixels 2. A TFT in which amorphous silicon is converted to polysilicon by laser annealing has the same TFT characteristics along the long axis direction of the line beam. Therefore, in this embodiment, the back gates of the drive transistors Trd are commonly connected along the row direction. A correction potential Vbg is applied from an external correction circuit to the control line CL commonly connected to the back gate.

  FIG. 13 is a graph showing the current-voltage characteristics of the P-channel type drive transistor Trd shown in FIG. In order to facilitate understanding, the same notation as the current-voltage characteristic graph of the N-channel transistor shown in FIG. 3 is adopted. As described in FIG. 11, in the case of a P-channel TFT, when the back gate potential is changed from the low level Lo to the high level Hi, the TFT characteristics change from the depletion side to the enhancement side. Therefore, when the pixel drive transistor Trd exhibits depletion characteristics, a relatively high back gate voltage is applied to bring the TFT characteristics closer to the target characteristics. Conversely, when the pixel drive transistor Trd exhibits enhancement characteristics, a relatively low correction potential is applied to the back gate to bring the TFT characteristics closer to the target characteristics.

  Among the TFT characteristic variations caused by the low-temperature polysilicon process using laser annealing, the most conspicuous is the Vth variation. This is because the threshold voltage characteristics of the TFT are aligned in parallel with the long axis direction of the line beam used for laser annealing. Therefore, in the present invention, the back gate correction is performed in accordance with the long axis direction of the line beam. The stripe-like TFT variation along the pixel row or column is mainly due to the laser annealing process, but in addition to this, the uneven TFT caused by the film thickness of the silicon thin film and the concentration of impurities implanted into the silicon thin film There is also characteristic variation. In order to deal with this unevenness, the pixel array section may be divided into a grid and the back gate correction may be performed for each area. Ultimately, if each drive transistor is individually back gate-corrected for each pixel, the uniformity of the screen can be increased in an ideal state. The technique of the present invention can be applied not only to TFTs formed in the pixel array section but also to peripheral circuit TFTs formed on the same panel 0 as the pixel array section 1 as a technique for suppressing variations in TFT characteristics. For example, the back gate correction of the present invention can be adopted for the TFTs constituting the scanner 4 and the selector 3 in order to correct the threshold voltage variation. The back gate correction according to the present invention can be applied to various types of TFTs. It can be applied not only to low-temperature polysilicon TFTs but also to high-temperature polysilicon TFTs and amorphous silicon TFTs. Further, it can be applied to an LSI manufacturing process.

  FIG. 14 is a schematic plan view showing a fourth embodiment of the display device according to the present invention. In order to facilitate understanding, parts corresponding to those in the first embodiment shown in FIG. The display device of this embodiment also basically includes a pixel array unit 1 and a circuit unit. A pixel array unit 1 constituting the screen is arranged on the panel 0. A peripheral circuit unit for driving the pixel array unit 1 is also mounted on the same panel 0. The circuit unit mounted on the panel 0 includes not only the selector 3 and the scanner 4 but also the correction circuit 6. The correction circuit 6 automatically detects a correction potential for each control line CL, and applies the detected correction potential to the corresponding control line CL.

  As is clear from the above description, the fourth embodiment is different from the first embodiment in that the correction circuit 6 is built in the panel 0. The first embodiment shown in FIG. 1 is configured to input a correction potential (back gate potential) from the outside of the panel. For this purpose, terminals are provided along the outer peripheral edge of the panel. The number of terminals (the number of pads) is the same as the number of rows or columns of the pixel array section. For example, when the control line CL is arranged in parallel with the scanning line, it is necessary to provide a pad for each row of pixels. When the pixel array portion has a high definition and a high pixel density, it is necessary to form pads at very fine intervals, and connection with an external correction circuit becomes difficult. Further, there is a problem that it takes time to determine an appropriate back gate potential for each control line CL. In contrast, the present embodiment incorporates the correction circuit 6 in the panel 0, and automatically detects the optimum correction potential for each control line CL and applies the detected correction potential to the corresponding control line CL. ing. With this configuration, it is not necessary to connect the pixel array unit 1 inside the panel 0 and the outside correction circuit.

  FIG. 15 is a circuit diagram showing a specific configuration example of the correction circuit 6 included in the fourth embodiment shown in FIG. As shown in the drawing, the correction circuit 6 is composed of a set of correction units arranged corresponding to each control line CL. This correction unit includes a detection transistor Trn and a resistance element R connected in series between a power supply line (high potential Vh) and a ground line (low potential Vl). The control line CL corresponding to each correction unit is connected to the midpoint (intermediate node) of the detection transistor Trn and the resistance element R. In this embodiment, the potential of this intermediate node is applied to each control line CL as a back gate potential (correction potential).

  The detection transistor Trn has the same size and the same size as the drive transistor Trd connected to the corresponding control line CL. The drive transistor Trd is an N-channel type, and the detection transistor Trn is also an N-channel type correspondingly. The drive transistor Trd and the detection transistor Trn connected to the same control line CL are located on the same line and are irradiated with a line beam at the same timing. Therefore, the drive transistor Trd and the detection transistor Trn connected to the same control line CL have the same characteristics. By utilizing this fact, the characteristics of the drive transistor Trd are detected in units of rows (lines), and a correction potential corresponding to the characteristics is automatically set.

  With continued reference to FIG. 15, the operation of the correction circuit 6 will be described in detail. A predetermined operating voltage Vg is applied from the outside to the gate of the detection transistor Trn included in each correction unit. Accordingly, the detection transistor Trn of each correction unit is turned on, and a current flows through the load resistor R from the high potential Vh side toward the low potential Vl side.

  In such an operation, the intermediate node potential of the corresponding correction unit is relatively low in the line in which the drive transistor Trd shows the depletion TFT characteristic than the target TFT characteristic (average TFT characteristic). Therefore, a relatively low back gate potential is applied to the corresponding control line CL. As a result, the TFT characteristics are shifted in the enhancement direction as shown in FIG. The target TFT characteristic can be obtained by shifting the depletion characteristic in the enhancement direction.

  On the other hand, in the line that shows enhanced TFT characteristics rather than the target TFT characteristics (average TFT characteristics), the intermediate node potential of the corresponding correction unit is relatively high. Therefore, a relatively high potential is applied as a back gate potential (correction potential) to the corresponding control line CL, and the TFT characteristics shift in the depletion direction. When the enhancement characteristic is shifted in the depletion direction, the target TFT characteristic is obtained. By such an operation, the characteristics of each drive transistor are adjusted in units of lines, and the pixel array unit 1 as a whole becomes uniform, so that unevenness as shown in FIG. 7 is improved.

  In order to supply the correction circuit 6 with the operating voltage Vg, the power supply voltage Vh, and the ground voltage Vl, three terminals (pads) are formed on the outer peripheral edge of the panel 0. As apparent from the comparison with the embodiment shown in FIG. 1, the number of external connection pads can be greatly reduced. By adjusting the gate potential Vg, the high potential Vh, and the low potential Vl from the outside, it is possible to adjust the degree of the back gate correction performed by the correction circuit 6 (how it is applied).

  The operation of the correction circuit 6 shown in FIG. 15 will be described in detail with reference to FIG. FIG. 16 is an equivalent circuit diagram of one correction unit. A graph showing the Vgs-Ids characteristic of the detection transistor Trn is also shown. When the detection transistor Trn exhibits depletion characteristics, the drain current Ids is high, so that the intermediate node has a potential higher than Vl. Since the correction potential Vbg appearing at the intermediate node is lowered, the N-channel drive transistor Trd on the same line showing the depletion characteristics as the detection transistor Trn is shifted in the enhancement direction to have the target TFT characteristics. Conversely, when the detection transistor Trd has an enhancement characteristic, the drain current Ids is low, so that the intermediate node has a potential higher than Vh. Since the correction potential Vbg appearing at the intermediate node is high, the N-channel drive transistor Trd on the same line showing the enhancement characteristic shifts in the depletion direction, and the desired TFT characteristic is obtained.

  FIG. 17 is a schematic plan view showing a fifth embodiment of the display device according to the present invention. Portions corresponding to those in the fourth embodiment shown in FIGS. 14 and 15 are given corresponding reference numerals for easy understanding. Unlike the fourth embodiment shown in FIG. 15, in the fifth embodiment, the drive transistor Trd is a P-channel type. Correspondingly, a P-channel detection transistor Trp is used for each correction unit on the correction circuit 6 side.

  FIG. 18 is a schematic diagram for explaining the operation of the correction circuit included in the fifth embodiment shown in FIG. It is the graph which shows the equivalent circuit diagram of one correction | amendment unit, and the Vgs-Ids characteristic of the detection transistor Trp contained in this correction | amendment unit. As shown in the figure, the correction unit includes a detection transistor Trp and a load resistor R connected in series between a high potential Vh and a low potential Vl. A correction potential (back gate potential) Vbg appears at an intermediate node between the two. When the detection transistor Trp is turned on according to the operating potential Vg supplied from the outside, the drain current Ids flows from the high potential Vh toward the low potential Vl.

  When the detection transistor Trp has a depletion characteristic, since the Ids is high, the intermediate node is at a potential higher than Vh. Since the Vbg potential appearing at the intermediate node is high, the drive transistors Trp on the same line, which also show the depletion characteristics, shift in the enhancement direction and become the target TFT characteristics. Conversely, when the detection transistor Trp exhibits enhancement characteristics, the intermediate node is at a potential higher than Vl because Ids is low. Since the back gate potential Vbg appearing at the intermediate node is low, the P-channel drive transistor Trp on the same line, which also exhibits enhancement characteristics, shifts in the depletion direction and becomes the target TFT characteristics.

  FIG. 19 is a schematic plan view showing a sixth embodiment of the display device according to the present invention. Portions corresponding to those in the fourth embodiment shown in FIG. 15 are denoted by corresponding reference numerals. The difference from the fourth embodiment is that the load resistance R of each correction unit is replaced with a load transistor. That is, each correction unit corresponding to each control line CL includes a pair of detection transistors Trn connected in series between the power supply line Vh and the ground line Vl and a load transistor Trp complementary thereto. The control line CL corresponding to each correction unit is connected to the midpoint (intermediate node) of the detection transistor Trn and the load transistor Trp. A gate voltage Vgn is applied to the gate of the detection transistor Trn from the outside, and a gate voltage Vgp is also applied to the gate of the load transistor Trp from the outside.

  In the fourth embodiment shown in FIG. 15, it is necessary to keep the detection transistor Trn in an energized state in order to operate the correction circuit 6. The operating current always flows from the high potential Vh toward the low potential Vl, resulting in an increase in power consumption of the panel. In order to cope with this, in the present embodiment, a pair of complementary transistors are connected in series to form a correction unit to save power consumption. That is, the sixth embodiment shown in FIG. 19 is configured to automatically detect the correction potential by turning on the pair of complementary transistors, and then turn off the pair of complementary transistors and hold the detected correction potential at the intermediate node. . The held correction potential is applied as a back gate potential to the corresponding control line CL. With this configuration, power consumption required for detection and application of the correction potential can be greatly reduced. The correction potential is held at the intermediate node by simultaneously turning off the gate potentials of the N-channel transistor Trn and the P-channel transistor Trp connected in series. As a result, a state in which a through current always flows is eliminated. By periodically turning on the gates of the complementary transistors Trn and Trp, the potential of the intermediate node can be refreshed.

  FIG. 20 is a schematic plan view showing a seventh embodiment of the display device according to the present invention. In order to facilitate understanding, portions corresponding to those of the sixth embodiment shown in FIG. 19 are denoted by corresponding reference numerals. As in the sixth embodiment, in the seventh embodiment, each correction unit is formed of a series connection of a pair of complementary transistors Trn and Trp. The difference is that the sixth embodiment shown in FIG. 19 uses an N-channel type drive transistor, whereas each pixel 2 uses a P-channel type drive transistor Trd in this embodiment. . Correspondingly, on the correction unit side, the P-channel transistor Trp becomes a detection transistor, and the N-channel transistor Trn becomes a load transistor. However, the configuration of each unit of the correction circuit 6 is the same between the sixth embodiment and the seventh embodiment, and the operation is exactly the same.

  With reference to FIG. 21, the operation of the sixth embodiment and the seventh embodiment will be described in detail. FIG. 21 shows an equivalent circuit of one correction unit, the Vgs-Ids characteristic of the P-channel transistor Trp, and the Vgs-Ids characteristic of the N-channel transistor Trn. As shown in the figure, the P-channel transistor Trp and the N-channel transistor Trn are connected in series between the high potential Vh and the low potential Vl, and the correction potential Vbg appears at the intermediate node of both transistors. The transistors Trp and Trn can be switched on and off by controlling the gate potentials Vgp and Vgn.

  In the sixth and seventh embodiments, the transistors Trn and Trp are formed of the same polysilicon layer. That is, the transistors Trn and Trp are formed of polysilicon having a common channel region. In this case, when the N-channel transistor Trn exhibits depletion characteristics, the P-channel transistor has a characteristic of exhibiting enhancement characteristics. Conversely, when the N-channel transistor Trn exhibits enhancement characteristics, the P-channel transistor Trp has a characteristic of exhibiting depletion characteristics. As described above, when the channel portions of the NMOS and PMOS are common, there is an inverse correlation in TFT characteristics between the NMOS and PMOS.

  When the transistor Trn has a depletion characteristic and the transistor Trp has an enhancement characteristic, the potential of the intermediate node becomes Vl when both transistors are turned on. Since the correction potential Vbg is low, if the drive transistor Trd is an N-channel type, it shifts to an enhancement characteristic. Conversely, if the drive transistor Trd is a P-channel type, it shifts to a depletion tendency. Accordingly, the drive transistor Trd approaches the target TFT characteristics in both the N channel type and the P channel type.

  Conversely, when the transistor Trn exhibits enhancement characteristics and the transistor Trp exhibits depletion characteristics, the intermediate node potential between them is Vh. Since the correction potential Vbg appearing at the intermediate node is high, if the drive transistor Trd is an N-channel type, it tends to be a depletion shift. Therefore, when the drive transistor Trd is either NMOS or PMOS, the target TFT characteristics are obtained.

  By changing the gate voltage applied to the transistors Trn and Trp, the on-resistances of the transistors Trn and Trp can be easily changed, so that the correction potential Vbg appearing at the intermediate node between them can be adjusted in the vertical direction. In order to obtain a correction circuit with reduced power consumption, the gate potential applied to the transistors Trn and Trp may be pulsed, and the correction unit may be turned on and off periodically. By doing so, a through current flows only when each correction unit is on. This ON timing can be determined by the potential holding state of the intermediate node.

  When the correction unit is configured by connecting a PMOS and an NMOS in series as in the sixth embodiment and the seventh embodiment, the intermediate potential works in a direction in which back gate correction is easily performed. Compared with a correction unit configured by connecting a load resistor and a TFT in series as in the fourth embodiment and the fifth embodiment, it is easier to detect a difference in characteristic variation in the series connection of PMOS and NMOS. The correction potential appearing at the intermediate node of each correction unit can be appropriately adjusted by potentials Vgn, Vgp, Vh, and Vl supplied from the outside. If Vgp-Vh and Vgn-Vl are set at the operating point where the difference in Ids between the depletion characteristics transistor and the enhancement characteristics transistor is large, the correction potential appearing at the intermediate node can make a large difference depending on the TFT characteristics. It is. The potentials of Vgn, Vgp, Vh, and Vl can be adjusted while confirming the image quality. Since the number of adjustment power supplies is 4, the man-hours can be greatly reduced.

  FIG. 22 is a schematic diagram showing an arrangement relationship between the drive transistor Trd on the pixel array side and the transistors Trn and Trp on the correction circuit side. As described above, since the TFT characteristics are aligned in the major axis direction of the line beam used for laser annealing, the drive transistor Trd of each pixel 2 and the detection transistor Trn on the correction circuit side are aligned on the major axis line accordingly. It is preferable to arrange. Also, the transistor size needs to be matched between the drive transistor Trd and the detection transistor Trn. If the transistor size is different, the number of polycrystalline silicon crystals in the channel is different, which causes a slight shift in TFT characteristics. The transistor structure and its peripheral layout are preferably the same for the drive transistor Trd and the detection transistor Trn. This is because in laser annealing, the heating state varies depending on the layout.

  As described above, according to the present invention, the drive transistor has a double gate structure, and the variation in threshold voltage is corrected by adjusting the back gate voltage. The present invention is also applicable to a display device in which a threshold voltage correction function and a mobility correction function are incorporated in each pixel. According to the present invention, the variation in threshold voltage is roughly corrected in line units, and the uniformity of the screen is further improved by precisely correcting the variation in threshold voltage with the threshold voltage correction function incorporated in each pixel. Can do.

  FIG. 23 is a schematic block diagram illustrating an example of a display device in which a threshold voltage correction function and a mobility correction function are incorporated in each pixel. Unlike the threshold voltage, the mobility is difficult to correct with the back gate potential. Therefore, the mobility can be corrected within each pixel, and the uniformity of the screen can be further enhanced by combining with the present invention.

  As shown in the figure, the display device includes a pixel array unit 1 and a circuit unit for driving the pixel array unit 1. The pixel array unit 1 includes a row-like scanning line WS, a column-like signal line SL, a matrix-like pixel 2 arranged at a portion where both intersect, and a power supply line arranged corresponding to each row of the pixels 2 DS. The circuit unit supplies a control signal to each scanning line WS sequentially to scan the pixels 2 line-sequentially in units of rows, and switches each power supply line DS to a high potential and a low potential according to the line sequential scanning. A drive scanner 5 for supplying a power supply voltage to be replaced, and a horizontal selector 3 for supplying a signal potential as a video signal and a reference potential to the columnar signal lines SL in accordance with the line sequential scanning are provided. Here, the write scanner 4 and the drive scanner 5 constitute a scanner unit, and the horizontal selector 3 constitutes a signal driver.

  Each pixel 2 includes a sampling transistor Tr1, a drive transistor Trd, a storage capacitor Cs, and a light emitting element EL. Each light emitting element EL emits light in one of the three primary colors RGB. A pixel trio is composed of a pixel (RED) including a red light emitting element, a pixel (GREEN) including a green light emitting element, and a pixel (BLUE) including a blue light emitting element. Color display can be performed by arranging the pixel trio in a matrix on the pixel array section 1.

  FIG. 24 is a circuit diagram showing a specific configuration and connection relationship of the pixels 2 included in the display device shown in FIG. As illustrated, the pixel 2 includes a light emitting element EL represented by an organic EL device, a sampling transistor Tr1, a driving transistor Trd, and a storage capacitor Cs. The sampling transistor Tr1 has its gate connected to the corresponding scanning line WS, one of its source and drain connected to the corresponding signal line SL, and the other connected to the gate G of the driving transistor Trd. The drive transistor Trd has a source S connected to the light emitting element EL and a drain connected to the corresponding power supply line DS. The cathode of the light emitting element EL is connected to the ground potential Vcath. This ground wiring is wired in common to all the pixels 2. The storage capacitor (pixel capacitor) Cs is connected between the source S and the gate G of the drive transistor Trd.

  The pixel configuration illustrated in FIG. 24 is an example, and a display device to which the present invention is applied is not limited to this circuit configuration. Basically, each pixel 2 includes a sampling transistor Tr1, a drive transistor Trd, a light emitting element EL, and a storage capacitor Cs. The sampling transistor Tr1 has a control terminal (gate) connected to the scanning line WS, and a pair of current terminals (source and drain) connected between the signal line SL and the control terminal of the drive transistor Trd. The drive transistor Trd has one of a pair of current ends (source and drain) connected to the light emitting element EL and the other connected to the power supply line DS. The storage capacitor Cs is connected between the control end (gate G) of the drive transistor Trd and one of the pair of current ends (source and drain) (source S) of the drive transistor Trd.

  FIG. 25 is a timing chart for explaining the operation of the pixel 2 shown in FIG. The change in the potential of the scanning line WS, the change in the potential of the power supply line DS, and the change in the potential of the signal line SL are shown with a common time axis. In parallel with these potential changes, changes in the gate G and source S of the drive transistor Trd are also shown.

  In this timing chart, the period is divided into (0) to (7) for convenience in accordance with the transition of the operation of the pixel 2. First, in the light emission period (0), the power supply line DS is at the high potential Vccp, and the drive transistor Trd supplies the drive current Ids to the light emitting element EL. The drive current Ids flows from the power supply line DS at the high potential Vccp through the light emitting element EL through the drive transistor Trd and flows into the common ground wiring Vcath.

  Subsequently, in the period (1), the feeder line DS is switched from the high potential Vccp to the low potential Vini. As a result, the power supply line DS is discharged to Vini, and the source potential of the drive transistor Trd transits to a potential close to Vini. When the wiring capacity of the feeder line DS is large, the feeder line DS may be switched from the high potential Vccp to the low potential Vini at a relatively early timing.

  Next, in the period (2), the sampling transistor Tr1 becomes conductive by switching the scanning line WS from the low level to the high level. At this time, the signal line SL is at the reference potential Vofs. Therefore, the gate potential of the drive transistor Trd becomes the reference potential Vofs of the signal line SL through the conducting sampling transistor Tr1. At the same time, the source potential of the drive transistor Trd is immediately fixed to the low potential Vini. Thus, the source potential of the drive transistor Trd is initialized (reset) to the potential Vini that is sufficiently lower than the reference potential Vofs of the video signal line SL. Specifically, the low potential Vini of the power supply line DS is set so that the gate-source voltage Vgs (the difference between the gate potential and the source potential) of the drive transistor Trd is larger than the threshold voltage Vth of the drive transistor Trd.

  As is clear from the above description, the period (1) and the period (2) are preparation processes for the threshold voltage correction operation. That is, in this preparation process, the control terminal, which is the gate G of the driving transistor Trd, is held at the reference potential Vofs, while the gate / source voltage Vgs between the current terminals serving as the source S of the driving transistor Trd is larger than the threshold voltage Vth. Then, the drive transistor Trd is turned on.

  Next, in the Vth cancellation period (3), the power supply line DS changes from the low potential Vini to the high potential Vccp, and the source potential of the drive transistor Trd starts to rise. Eventually, the current is cut off when the gate-source voltage Vgs of the drive transistor Trd reaches the threshold voltage Vth. In this way, a voltage corresponding to the threshold voltage Vth of the drive transistor Trd is written into the storage capacitor (pixel capacitor) Cs. This is the threshold voltage correction operation. At this time, in order to prevent current from flowing exclusively to the storage capacitor Cs and not to the light emitting element EL, the potential of the common ground wiring Vcath is set so that the light emitting element EL is cut off.

  As is apparent from the above description, this Vth cancellation period (3) is the energization process of the threshold voltage correction operation. In this energization process, the drive transistor Trd is energized while maintaining the gate G at the reference potential Vofs, and when the drive transistor Trd is cut off, a voltage corresponding to the threshold voltage appearing between the gate and the source is held in the holding capacitor Cs.

  In the period (4), the scanning line WS shifts to the low potential side, and the sampling transistor Tr1 is turned off once. At this time, although the gate G of the drive transistor Trd is in a floating state, the gate-source voltage Vgs is equal to the threshold voltage Vth of the drive transistor Trd, so that it is in a cut-off state and no drain current Ids flows.

  Subsequently, in period (5), the potential of the signal line SL changes from the reference potential Vofs to the sampling potential (signal potential) Vsig. Thus, preparations for the next sampling operation and mobility correction operation (signal writing and mobility μ cancellation) are completed.

  In the signal writing / mobility μ cancel period (6), the scanning line WS transits to the high potential side, and the sampling transistor Tr1 is turned on. Therefore, the gate potential of the drive transistor Trd becomes the signal potential Vsig. Here, since the light emitting element EL is initially in the cut-off state (high impedance state), the drain-source current Ids of the driving transistor Trd flows into the light emitting element capacitance, and charging is started. Therefore, the source potential of the drive transistor Trd starts to rise, and the gate-source voltage Vgs of the drive transistor Trd eventually becomes Vsig + Vth−ΔV. In this way, the signal potential Vsig is sampled and the correction amount ΔV is adjusted simultaneously. Ids increases as Vsig increases, and the absolute value of ΔV also increases. Therefore, the mobility correction according to the light emission luminance level is performed. When Vsig is constant, the absolute value of ΔV increases as the mobility μ of the drive transistor Trd increases. In other words, since the negative feedback amount ΔV increases as the mobility μ increases, it is possible to remove variations in the mobility μ from pixel to pixel.

  Finally, in the light emission period (7), the scanning line WS shifts to the low potential side, and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. At the same time, the drain current Ids starts to flow through the light emitting element EL. As a result, the anode potential of the light emitting element EL rises according to the drive current Ids. The increase in the anode potential of the light emitting element EL is nothing but the increase in the source potential of the drive transistor Trd. When the source potential of the drive transistor Trd rises, the gate potential of the drive transistor Trd also rises in conjunction with the bootstrap operation of the storage capacitor Cs. The amount of increase in gate potential is equal to the amount of increase in source potential. Therefore, the gate-source voltage Vgs of the driving transistor Trd is kept constant at Vsig + Vth−ΔV during the light emission period (7). In the above description, Vgs is calculated with Vofs = Vcath = 0V.

  The display device according to the present invention has a thin film device configuration as shown in FIG. This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor part (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor part such as a storage capacitor, and a light emitting part such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is laminated thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module shape as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is input to a main body of various electronic devices such as a digital camera, a notebook personal computer, a mobile phone, and a video camera, or The present invention can be applied to displays (display units) of electronic devices in various fields that display information generated in the main unit of the electronic device as an image or video. Examples of electronic devices provided with such a display unit are shown below.

  FIG. 28 shows a television to which the present invention is applied, which includes a video display screen 11 composed of a front panel 12, a filter glass 13, and the like, and is produced by using the display device of the present invention for the video display screen 11. .

  FIG. 29 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a back view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 30 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 that is operated when inputting characters and the like, and the main body cover includes a display unit 22 that displays an image. This display device is used for the display portion 22.

  FIG. 31 shows a mobile terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used.

  FIG. 32 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. It is manufactured by using the device for its monitor 36.

1 is a schematic plan view showing a first embodiment of a display device according to the present invention. It is a typical top view showing a 2nd embodiment similarly. It is a graph which shows the characteristic of an N channel type drive transistor. It is a circuit diagram which shows the typical structural example of a display apparatus. It is a schematic diagram with which it uses for operation | movement description of the display apparatus shown in FIG. It is a schematic diagram which shows a laser annealing process. It is a screen photograph figure of a display apparatus. It is sectional drawing of a drive transistor. It is sectional drawing of the drive transistor which has a double gate structure. It is an equivalent circuit diagram of a double gate transistor. It is the circuit diagram and graph which show the operating characteristic of a double gate transistor. It is a top view which shows 3rd Embodiment of the display apparatus concerning this invention. It is a characteristic formula of a P-channel type driving transistor. It is a top view which shows 4th Embodiment of the display apparatus concerning this invention. It is a circuit diagram which similarly shows 4th Embodiment. It is a schematic diagram with which it uses for operation | movement description of 4th Embodiment. It is a typical top view which shows 5th Embodiment of the display apparatus concerning this invention. It is a schematic diagram with which it uses for operation | movement description of 5th Embodiment. It is a typical top view which shows 6th Embodiment of the display apparatus concerning this invention. It is a typical top view showing a 7th embodiment similarly. It is a graph with which it uses for operation | movement description of 6th Embodiment and 7th Embodiment. It is a schematic diagram which shows the layout of a drive transistor and a detection transistor. It is a block diagram which shows an example of the display apparatus with which this invention is applied. FIG. 24 is a circuit diagram for explaining an operation of the display device shown in FIG. 23. 24 is a timing chart for explaining operations of the display device shown in FIG. It is sectional drawing which shows the device structure of the display apparatus concerning this invention. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 0 ... Panel, 1 ... Pixel array part, 2 ... Pixel, 3 ... Selector (signal circuit), 4 ... Scanner (scanning circuit), Trd ... Drive transistor, Trn ... Detection transistor, Trp ... detection transistor, EL ... light emitting element, 6 ... correction circuit, CL ... control line, WS ... scanning line, SL ... signal line

Claims (9)

It consists of a pixel array part and a circuit part,
The pixel array unit includes row-shaped scanning lines, column-shaped signal lines, and matrix-shaped pixels arranged at portions where each scanning line and each signal line intersect,
The circuit unit includes a scanning circuit that selects pixels in units of rows through each scanning line, and a signal circuit that supplies signals to the selected pixels through each signal line,
The pixel includes a driving transistor that outputs a driving current according to the signal, and a light emitting element that emits light with a luminance according to the driving current,
The driving transistor includes a pair of current ends connected between a power source and the light emitting element, a channel region between the pair of current ends, a first gate electrode to which a signal is written from the signal line, and the channel A second gate electrode facing the first gate electrode with a region in between,
The display device includes a correction circuit that applies a correction potential to the second gate electrode to correct variation in characteristics of the drive transistor. The pixel array unit includes a control line that commonly connects the second gate electrodes of the drive transistors included in each pixel in units of rows or columns,
The display device according to claim 1, wherein the correction circuit applies a correction potential to each control line. The drive transistor has a drive current that fluctuates according to variations in its threshold voltage characteristics,
The display device according to claim 2, wherein the correction circuit applies a correction potential for correcting variation in the threshold voltage characteristic to the second gate electrode. The circuit unit is arranged on the same panel as the pixel array unit including the correction circuit,
The display device according to claim 2, wherein the correction circuit automatically detects a correction potential for each control line, and applies the detected correction potential to a corresponding control line. The correction circuit comprises a set of correction units arranged corresponding to each control line,
The correction unit includes a detection transistor and a resistance element connected in series between a power supply line and a ground line,
The display device according to claim 4, wherein a control line corresponding to each correction unit is connected to a midpoint of the detection transistor and the resistance element. The correction circuit comprises a set of correction units arranged corresponding to each control line,
The correction unit includes a pair of detection transistors and complementary transistors connected in series between a power supply line and a ground line,
The display device according to claim 4, wherein a control line corresponding to each correction unit is connected to a midpoint of the detection transistor and the complementary transistor.   The pair of detection transistors and complementary transistors are turned on to automatically detect a correction potential, and then the pair of detection transistors and complementary transistors are turned off to hold the detected correction potential at the intermediate point and corresponding control lines The display device according to claim 6, which is applied to the display.   The display device according to claim 5, wherein the detection transistor is on the same line as the drive transistor connected to the corresponding control line. A display unit and a main body unit for displaying information on the display unit;
The display unit includes a pixel array unit and a circuit unit,
The pixel array unit includes row-shaped scanning lines, column-shaped signal lines, and matrix-shaped pixels arranged at portions where each scanning line and each signal line intersect,
The circuit unit includes a scanning circuit that selects pixels in units of rows through each scanning line, and a signal circuit that supplies signals to the selected pixels through each signal line,
The pixel includes a driving transistor that outputs a driving current according to the signal, and a light emitting element that emits light with a luminance according to the driving current,
The driving transistor includes a pair of current ends connected between a power source and the light emitting element, a channel region between the pair of current ends, a first gate electrode to which a signal is written from the signal line, and the channel A second gate electrode facing the first gate electrode with a region in between,
The electronic device includes a correction circuit that applies a correction potential for correcting variation in characteristics of the drive transistor to the second gate electrode.