JP2009251039A - Display driving device and layout method for driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output circuit capable of canceling offset of the output circuit even in a recent high-performance display device in a smaller area. <P>SOLUTION: This display driving device is a display driving device including a plurality of driver cells corresponding to the output. The driver cell includes a decoder and an output circuit. The output circuit includes an amplifier circuit, an offset canceling capacity, a switch group for controlling the connecting relationship between the offset canceling capacity and an amplifier, and a control circuit for controlling the switch group. The control circuit is disposed between the amplifier and the switch group. The switch group is disposed between the offset canceling capacity and the control circuit, and the offset canceling capacity is disposed between the decoder and the switch group. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a display drive device and a layout method of a drive circuit used in the drive device.

  With the recent increase in size of liquid crystal display devices, improvements in various performances of liquid crystal drive devices are desired. In particular, high gradation is desired to display vivid colors. In recent years, a liquid crystal display device having a gradation voltage of 10 bits (1024) for each RGB and about 1 billion colors has also appeared. When the number of colors increases, the potential difference between adjacent gradation voltages generally decreases, and a deviation in output voltage, so-called offset, becomes a serious problem. As a technique for canceling the offset voltage, Patent Document 1 and Patent Document 2 can be cited.

  Patent Document 1 discloses an output circuit for offset cancellation having a capacity for charging an error voltage (hereinafter referred to as offset voltage) between an input terminal and a terminal on the feedback side. The offset voltage is held in the capacitor, and in the output state, by changing the connection of one end of the capacitor to the gate on the feedback side, it becomes a voltage follower state where the offset voltage is added, and the output voltage becomes almost the same as the input voltage, reducing the offset voltage it can.

  In Patent Document 2, a capacitor is charged with an output voltage obtained by adding an offset voltage to an input voltage between a feedback-side terminal and GND during sampling. The operational amplifier having the characteristic having the offset voltage is stable in a voltage follower state where the input terminal and the feedback terminal have a potential difference corresponding to the offset voltage as a virtual short circuit. The polarity of the operational amplifier is reversed at the time of output, and the operational amplifier outputs the same output voltage as the input voltage by applying the voltage obtained by adding the offset voltage to the input voltage charged to the capacitor to the input terminal after the reversal. It is stable in a virtual short state with a voltage potential difference, and the offset voltage between the input voltage and the output voltage is substantially reduced.

JP 09-244590 A JP 2005-110065 A

  However, it is very difficult to apply the offset cancel output circuit described in Patent Document 1 to an LCD driver or the like. In particular, when used for LCD drivers in recent years, it often has multiple outputs of 720ch or 960ch, and the capacity for charging the offset voltage is a circuit that outputs the gradation voltage by the number of output pins (scale). A load of the voltage regulator circuit). In a general gradation voltage generation circuit, it is very difficult to converge the offset voltage charge to the high load capacity within one cycle.

  Further, if the output circuit for offset cancellation described in Patent Document 2 is used, the capacity cannot be directly seen at the input terminal of the operational amplifier, so the above-mentioned problem can be solved, but the capacity can be seen directly at the output. It becomes difficult to ensure the phase margin. In the case of an LCD driver, charging (sampling) and output must be performed within one cycle due to usage conditions, and an operational amplifier with no phase margin has a large output ringing (swing) in a short sampling time, which is not intended as a result. The voltage is charged into the capacitor, and the offset cancellation accuracy is deteriorated.

  Further, in view of the above points, a display drive device that can perform high-performance offset cancellation with a smaller area is desired in devising an output circuit having various functions.

  The present invention provides a display drive device and a drive circuit layout method capable of canceling an offset of an output circuit with a small area and high accuracy even in a recent high-performance display device.

  In order to solve the above-described problem, the display driving device of the present invention is a display driving device including a plurality of driver cells corresponding to an output, and the driver cell includes a decoder and an output circuit. An amplifier circuit, an offset canceling capacitor, a switch group for controlling the connection relationship between the offset canceling capacitor and the amplifier, and a control circuit for controlling the switch group, the control circuit being disposed between the amplifier and the switch group The switch group is disposed between the offset cancel capacitor and the control circuit, and the offset cancel capacitor is disposed between the decoder and the switch group.

  In addition, the drive circuit layout method of the present invention includes a step of determining a driver cell block, a step of determining a DA converter block and an output circuit block in the driver cell block, and an output circuit to solve the above-described problems. An amplifier circuit block, a control switch block, a control circuit block, and an offset compensation capacitor block are determined in the block, and the control switch block is disposed between the offset compensation capacitor block and the amplifier circuit block. Arranging the control circuit block between the block and the amplifier circuit block, and arranging elements in the amplifier circuit block, the control switch block, the control circuit block, and the offset compensation capacitance block based on the design circuit diagram And a step of performing.

  The display drive device and the drive circuit layout method according to the present invention can cancel the offset of the output circuit with a small area and high accuracy even in a recent high-performance display device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that, in the following description and the accompanying drawings, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a block diagram of a display device 100 according to the first embodiment of the present invention. A source driving IC 120 and a gate driving IC 130 are mounted on the liquid crystal panel 110. The source driving IC 120 includes at least a gradation voltage generating circuit 140, a digital / analog converter 150, and an output circuit 160. A gradation voltage corresponding to the input data DIN is selected from the gradation voltage generation circuit 140 by the digital / analog converter 120 and output to the output circuit 160. The output of the output circuit 160 outputs a predetermined gradation voltage as an output signal to the liquid crystal panel 110 via the output pad of the source driving IC 120.

  Details of the output circuit 160 according to the first embodiment of the present invention will be described with reference to FIG. The output circuit 160 includes an amplifier circuit 210, first to sixth switches 221 to 226, a control circuit 230, and an offset compensation capacitor 240 that is a capacitance for offset cancellation. The fourth to sixth switches that control the connection relationship between the offset compensation capacitor 240 and the amplifier circuit 210 may be collectively referred to as a switch group 220 in some cases. The amplifier circuit 210 is generally called an operational amplifier, and includes a first input terminal 211, a second input terminal 212, a first output terminal 213, and a switching circuit 214. The switching circuit 214 is a circuit that inverts the polarities of the first input terminal 211 and the second input terminal 212. The amplifier circuit 210 can be realized by using, for example, a differential amplifier circuit described in FIG.

  The first switch 221 is connected between the data input terminal IN and the first output terminal 211, and controls connection / disconnection between the data input terminal IN and the first output terminal 211.

  The second switch 222 is connected between the first input terminal 211 and the first output terminal 213 and controls connection / disconnection between the first input terminal 211 and the first output terminal 213.

  The third switch 223 is connected between the data output terminal OUT and the first output terminal 213, and controls connection / disconnection between the data output terminal OUT and the first output terminal 213.

  The fourth switch 224 is connected between the first output terminal 213 and the second input terminal 212 and controls connection / disconnection between the first output terminal 213 and the second input terminal 212.

  The fifth switch 225 is connected between one end of the offset compensation capacitor 240 and the second input terminal 212, and controls connection / disconnection between the one end of the offset compensation capacitor 240 and the second input terminal 212.

  The sixth switch 226 is connected between one end of the offset compensation capacitor 240 and the first output terminal 213, and controls connection / disconnection between the one end of the offset compensation capacitor 240 and the first output terminal 213. Note that the sixth switch 226 is a switch having a higher on-resistance than the fifth switch 225. For example, it can be composed of large and small MOS transistors having different dimensions (gate length and width), or can be composed of MOS transistors having different impurity concentrations. In general, the fifth switch 225 may be referred to as an analog switch, and the sixth switch 226 may be referred to as a digital switch. The control circuit 230 is composed of, for example, a set of inverters, and is connected to the gates of first to sixth switches (transfer gates) 221 to 226 as necessary. In FIG. 2, the connection to the first to third switches is omitted for the sake of simplicity.

  Next, the offset cancel operation will be described in detail with reference to FIG. One of the high-performance display devices in recent years is a full-spec high-definition or full-HD display panel with 1920 × 1080 (horizontal × vertical) pixels. In current television, 120 Hz is mainstream, and the time for driving 1080 scanning lines by the gate driving IC is 1/120 second.

  If the driving time is one scanning line, the maximum time is about 7.7 μs. Naturally, since a margin for the driving time is required, the time allowed for the source driving IC is generally about 6 to 7 μs. The offset cancel operation of the present invention includes a sampling period which is a time for charging the offset voltage in the offset compensation capacitor 240 and an output period in which an output voltage which takes into account the offset voltage charged in the offset compensation capacitor 240 is output from the data output terminal. It can be realized with high accuracy within 7 μs.

  First, as shown in FIG. 3A, in the sampling period, the first switch 221, the fourth switch 224, and the sixth switch 226 are connected. In addition, the second switch 222, the third switch 223, and the fifth switch are disconnected. Note that the switching circuit 214 is connected so that the first input terminal 211 of the amplifier circuit 210 functions as a non-inverting input terminal and the second input terminal 212 functions as an inverting input terminal. The amplifier circuit 210 functions as a voltage follower by connecting the second input terminal 212 and the first output terminal 213 via the fourth switch 224. A gradation voltage corresponding to the output circuit 160 input to the data input terminal IN is applied to the first input terminal 211, and an offset voltage is applied to the gradation voltage corresponding to the output circuit 160 at the first output terminal 213. The riding voltage is output. The offset compensation capacitor 240 is charged with a voltage obtained by adding an offset voltage to the gradation voltage corresponding to the output circuit 160. Charging is performed via the sixth switch 226. The other end side of the offset compensation capacitor 240 is connected to the ground as an example, but can be realized with a fixed power source.

  Next, as illustrated in FIG. 3B, the first switch 221, the fourth switch 224, and the sixth switch 226 are disconnected in the output period. In addition, the second switch 222, the third switch 223, and the fifth switch are connected. The switching circuit 214 is connected so that the first input terminal 211 of the amplifier circuit 210 functions as an inverting input terminal and the second input terminal 212 functions as a non-inverting input terminal. A voltage obtained by adding an offset voltage to the gradation voltage corresponding to the output circuit 160 is applied to the second input terminal 212. The amplification circuit 210 functions as a voltage follower by connecting the first input terminal 211 and the first output terminal 213 via the second switch 222. By applying a voltage obtained by adding an offset voltage to the gradation voltage corresponding to the output circuit 160 to the second input terminal 212, the output applied to the data input terminal IN is applied to the first output terminal 213. The gradation voltage corresponding to the circuit 160 is output, and the offset voltage generated in the amplifier circuit 210 can be substantially canceled.

  Next, details of the amplifier circuit 210 will be described with reference to FIG. The amplifier circuit 210 includes at least an amplifier stage 410, an output stage 420, and a phase compensation capacitor group 430. The amplification stage 410 includes a differential amplification circuit 415 that outputs signals to the first amplification stage output 411 and the second amplification stage output 412 according to the first input terminal 211 and the second input terminal 212.

  The output stage 420 includes an output transistor 421 connected between the power supply and the first output terminal 213, and an output transistor 422 connected between the first output terminal 213 and the ground. A first amplification stage output 411 is connected to the gate of the output transistor 421. A second amplification stage output 412 is connected to the gate of the output transistor 422.

  The phase compensation capacitor group 430 includes first to fourth compensation capacitors C1 to C4 as phase compensation capacitors. The first compensation capacitor C1 is connected between the first amplification stage output 411 and the first output terminal 213. The second compensation capacitor C2 is connected between the second amplification stage output 412 and the first output terminal 213. The third compensation capacitor C3 has one end connected to the first amplification stage output 411, the other end connected to the first output terminal 213 via the seventh switch 431, and the power source via the ninth switch 433. It is connected to the. The fourth compensation capacitor C4 has one end connected to the second amplification stage output 412 and the other end connected to the first output terminal 213 via the eighth switch 432 and to the ground via the tenth switch 434. It is connected to the. The first compensation capacitor C1 and the second compensation capacitor C2 function as main phase compensation capacitors, and the third compensation capacitor C3 and the fourth compensation capacitor C4 function as sub-phase compensation capacitors.

  The operation of the amplifier circuit 210 will be described in detail with reference to FIG. FIG. 5A shows the state of the sampling period of the amplifier circuit 210. The seventh switch 431 and the eighth switch 432 are in a disconnected state, and the ninth switch 433 and the tenth switch 434 are controlled to be in a connected state. FIG. 5B shows the state of the output period of the amplifier circuit 210. The seventh switch 431 and the eighth switch 432 are connected, and the ninth switch 433 and the tenth switch 434 are controlled so as to be disconnected. Control of the seventh to tenth switches 431 to 434 can use the signal of the control circuit 230 shown in FIG.

The principle of the present invention will be described with reference to FIGS. FIG. 6 is a conceptual diagram showing an outline of a general feedback circuit. When the open loop voltage gain of the operational amplifier is Ao and the feedback factor is β, the closed loop voltage gain Ac is
Ac = vo / vi = -Ao / (1+ Aoβ): Formula 1

Thus, when Aoβ = -1 (Ao = 0dB), the operational amplifier oscillates if the input / output phase is delayed by 180 degrees or more.

  FIG. 7 is a Bode diagram showing the frequency characteristics of the amplifier circuit shown in FIG. When the open loop voltage gain Ao becomes 0 dB, the operational amplifier oscillates if the phase is delayed by 180 degrees or more.

FIG. 8 shows an outline of a feedback circuit embodying FIG. FIG. 8 shows a configuration in which a resistor Rload is added to improve the phase margin with respect to FIG. When the feedback amount β is expressed by an approximate expression, the following expression is obtained.

1 / β = (Rs + Rload) / Rload: Formula 2

That is, the feedback amount β increases as the output resistance increases. When this is applied to Equation 1, the voltage gain Ao decreases as the feedback amount increases. Therefore, the point at which Ao = 0 dB is moved to the low frequency region as it is, and the frequency of the operational amplifier substantially having only one pole. Since it becomes close to the characteristics and the pole on the high frequency side does not affect, the phase margin can be easily secured and stable operation can be realized.

  FIG. 9 shows frequency characteristics of a schematic diagram of the feedback circuit shown in FIG. When applied to the actual output circuit 160, the resistance corresponding to Rload in the schematic diagram of FIG. 8 is the on-resistance of the sixth switch 226, and the state during charging (sampling period) is the state of the sixth switch 226. The on-resistance is higher than that of the fifth switch 225. The high on-resistance of the sixth switch 226 means that the output circuit 160 has a sufficient phase margin.

  Note that if the on-resistance of the sixth switch 226 is increased to ensure a phase margin, the first and second compensation capacitors C1 and C2 can be reduced. Since the offset compensation capacitor 240 that is a load of the sampling period is also small, a high slew rate can be realized in combination with the reduction of the first and second compensation capacitors C1 and C2, and the phase margin is secured in the sampling period. Can be stabilized in a short time.

  In addition, when the output circuit 160 in the first embodiment, in particular, the capacitance values of the first and second compensation capacitors C1 and C2 are made extremely low, the sampling period can be shortened to the maximum. There is a possibility that the phase margin is not sufficiently secured. By connecting the third and fourth compensation capacitors C3 and C4 shown in FIG. 4 and FIG. 5 during the output period, it becomes possible to secure the capacitance value of the phase compensation capacitor. A high slew rate and a phase margin can be ensured.

  FIG. 10 is a graph showing an offset amount when the output circuit 160 of the present invention and a general output circuit are applied to a 10-bit output source driving IC. Graph A shows the maximum and minimum offset amounts when a general rail-to-rail output circuit is applied. Graph B shows the maximum and minimum values of the offset amount when the output circuit 160 of the present invention is applied.

  In graph A, an offset amount of ± 15 to 30 mV occurs at any gradation. However, in the graph B of the present invention, it can be suppressed within ± 5 mV. In the graph A, the offset amount is extremely high near the gradation 0 or 1024, but in the graph B, it is possible to set the offset amount so that there is no significant difference in any gradation.

  The effect of the present invention is not limited to the liquid crystal driving IC, but can be applied to any voltage driving type driving IC. In particular, since an organic EL panel or the like does not use a backlight and is a self-luminous type, the characteristic that the offset amount is flat in all gradations makes it possible to display an image more clearly.

  In addition, the output circuit 160 with high offset cancellation accuracy contributes to size reduction of the amplification stage 410. In general, in order to reduce the amount of offset, the transistor size must be increased, but by applying the output circuit 160 of the present invention, it is possible to cancel out some offset. .

  FIG. 11 is an output circuit showing Embodiment 2 of the present invention. Components having the same functions as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The output circuit 360 according to the second embodiment includes buffer circuits 525 and 526 in a feedback path from the output stage 420 according to the first embodiment to the compensation capacitor group 430. The outputs of the output stage 420 are input to the buffer circuits 525 and 526. Further, the compensation capacitor group 430 of the first embodiment is provided with a compensation capacitor group 330 in the second embodiment. The compensation capacitor group 330 includes a compensation capacitor C12 connected between the output of the buffer circuit 525 and the first amplification stage output 411, and a compensation capacitor connected between the output of the buffer circuit 525 and the first amplification stage output 412. A capacitor C21, a compensation capacitor C11 connected between the output of the buffer circuit 526 and the first amplification stage output 411, and a compensation capacitor C22 connected between the output of the buffer circuit 526 and the first amplification stage output 412 And third and fourth compensation capacitors C3 and C4.

  The output transistor 421 composed of a P-type MOS transistor in the output stage 420 has a source electrode connected to the power supply terminal, the power supply voltage VDD is supplied to the source electrode, and a drain electrode connected to the first output terminal 213 of the amplifier circuit 310. The output transistor 422 connected by the N-type MOS transistor has a source electrode connected to the first output terminal 213 of the amplifier circuit 310 and a drain electrode connected to the ground terminal. The output transistors 421 and 422 have push-pull circuits whose operating voltage ranges are different from each other with respect to the voltage level of the signal input to each gate electrode (specifically, each operating voltage range partially overlaps to perform class AB operation). The output transistor 421 is activated when the output voltage is increased, and the output transistor 422 is activated when the output voltage is decreased.

  Next, the operation of the amplifier circuit 310 will be described. Since the output transistor 421 and the output transistor 422 operate as a push-pull circuit (specifically, a push-pull circuit that performs class AB operation) as described above, the output stage 420 of the amplifier circuit 310 drives the display panel 110 (display panel). A wide effective operating range suitable for applying a data voltage to the capacitive load 242 corresponding to 110 individual pixels (cells) can be obtained.

  The buffer circuit 525 of the amplifier circuit 310 is a level shift circuit having a source follower configuration of the N-type MOS transistor 527, and the output voltage Vout of the amplifier circuit 310 is higher than the power supply voltage VDD to the ground voltage. It operates when the threshold voltage Vtn is within a high value range. The output voltage of the buffer circuit 525 becomes a voltage lower than the output voltage Vout of the amplifier circuit 310 by the threshold voltage Vtn, and the output voltage of the buffer circuit 525 that changes according to the output voltage Vout is output to the output transistor via the compensation capacitor C12. It is fed back to the gate electrode of 421 and fed back to the gate electrode of the output transistor 422 via the compensation capacitor C21.

  The buffer circuit 526 is a level shift circuit having a source follower configuration of the P-type MOS transistor 528, and the output voltage Vout of the amplifier circuit 310 is lower than the threshold voltage Vtp of the P-type MOS transistor 528 than the power supply voltage VDD to the ground. Operates when within voltage range. The output voltage of the buffer circuit 526 is higher than the output voltage Vout of the amplifier circuit 310 by the threshold voltage Vtp, and the output voltage of the buffer circuit 526 that changes according to the output voltage Vout is output to the output transistor via the compensation capacitor C11. It is fed back to the gate electrode of 421 and fed back to the gate electrode of the output transistor 422 via the compensation capacitor C22.

  As described above, in the amplifier circuit 310 according to the second embodiment, when the phase compensation is performed using the mirror effect, the buffer circuit is inserted in the feedback path of the amplifier circuit as compared with the first embodiment, so that the phase is compensated. The phase compensation capacity (compensation capacity C11, C12, C21C22) for ensuring a margin can be reduced. Since the phase compensation capacitance (the total capacitance of the compensation capacitors C11, C12, and C21C22) can be reduced, the voltage of the gate electrodes of the output transistors 421 and 422 due to the coupling of the compensation capacitors C11, C12, and C21C22 during the large amplitude operation. Since the fluctuation can be reduced, it is possible to prevent a through current from flowing due to the operation of the output transistors 421 and 422 during a period when they are not originally operated. Further, since the phase compensation capacitance can be reduced, the load of the input amplification stage 410 is reduced, the followability of the buffer circuits 421 and 422 to the change of the output voltage Vout is improved, and the slew rate of the amplification circuit 310 is improved. be able to. Furthermore, it is possible to reduce the size of the chip on which the amplifier circuit 310 is mounted.

  In the second embodiment, the buffer circuit 421 and the buffer circuit 422 have different operating voltage ranges, the maximum operating voltage in the buffer circuit 421 matches the power supply voltage VDD, and the minimum operating voltage in the buffer circuit 422 becomes the ground voltage. Therefore, at least one of the buffer circuit 421 and the buffer circuit 422 operates over the entire range of the output voltage Vout of the amplifier circuit 310 (power supply voltage VDD to ground voltage). Compared with the case where only one is provided, the output voltage dependency of the phase margin can also be improved. Since the first to sixth switches 221 to 226 operate in the same manner as in the first embodiment, the effects of the first embodiment can also be obtained.

  FIG. 12 is a top view showing a part of the display driving apparatus according to the third embodiment of the present invention. The display driving device 500 is a rectangle in which an integrated circuit is formed on a semiconductor substrate (semiconductor chip) and is generally composed of a short side and a long side. In the display driving device 500, a plurality of strip-like driver cells 570 are arranged in the long side direction. The driver cell 570 generally includes a latch circuit that receives a signal corresponding to display data, a digital / analog converter that converts a digital signal into an analog signal, a level shifter that converts a signal level, an output circuit that outputs an output signal with high driving capability, and the like. Is formed. In the present invention, a digital / analog converter and an output circuit will be particularly described.

  The driver cell 570 has a strip shape and includes a DA converter block 550 in which a digital-analog converter is formed in a rectangular area, and an output circuit block 560 in which an output circuit is formed. The long side direction of the driver cell 570 is the short side direction of the display driving device 500. In the long side direction of the driver cell 570, the output circuit block 560 is disposed closer to the chip edge 590 than the DA converter block 550. The output circuit block 560 includes an amplifier circuit block 510, a control switch block 520, a control circuit block 530, and an offset compensation capacitor block 540. The amplifier circuit block 510 is a block in which the amplifier circuit 210 including the amplifier stage 410 and the output stage 420 is formed. The control switch block 520 is a block in which the fourth to sixth switches 224 to 226 are formed, and is a block in which the switch group 220 that controls the connection relationship between the offset compensation capacitor 240 and the amplifier circuit 210 is formed. The control circuit block 530 is a block in which the control circuit 230 is formed. The offset compensation capacitor block 540 is a block in which the offset compensation capacitor 240 is formed.

  The amplifier circuit block 510, the control switch block 520, the control circuit block 530, and the offset compensation capacitor block 540 are arranged in a line in the long side direction of the driver cell 570. A control switch block 520 is disposed between the offset compensation capacitor block 540 and the amplifier circuit block 510, and a control circuit block 530 is disposed between the control switch block 520 and the amplifier circuit block 510. The amplifier circuit block 510 is disposed closest to the chip edge 590 in the output circuit block 560.

  By arranging the amplifier circuit block 510, the control switch block 520, the control circuit block 530, and the offset compensation capacitor block 540 as described above, the following effects can be obtained. First, the width of the driver cell 570 can be reduced by arranging the blocks in a line. Further, since the offset compensation capacitor 240 can be arranged at a position close to the voltage at which the offset voltage between the output of the DA converter block 550 and the output of the amplifier circuit block 510 is desired to be output, the accuracy can be increased. Further, by disposing the control circuit block 530 between the control switch 520 and the amplifier circuit block 510, it becomes possible to efficiently supply signals to both the control switch 520 and the amplifier circuit block 510.

  Next, a layout method of the driving device of this embodiment will be described. In general, various specifications are determined when designing a drive device. For example, the format of the input interface and the number of output pins. A rough chip size is determined by the specifications and the number of wafers taken per wafer. When the chip size and specifications are determined, the block size per driver cell can also be determined. Next, positioning is also performed for each block (amplifier circuit block, control switch block, control circuit block, and offset compensation capacitor block) in the driver cell. Based on a separately designed DA converter and design drawing of the output circuit, element placement, that is, so-called layout design, is performed on each previously determined block.

  In the above layout method, even if a circuit is modified or changed on the design drawing, the position of the block is determined in advance. It is possible to keep the predicted value within the expected range, and it is possible to realize in a short time from a small correction or change of the circuit to the convergence of the design. In other words, it is possible to prevent an unexpected design trouble from occurring.

  FIG. 13 is a top view showing a part of a display driving apparatus according to Embodiment 4 of the present invention. The display driving device 600 is formed by forming an integrated circuit on a semiconductor substrate (semiconductor chip), and is generally a rectangle composed of a short side and a long side. In the display driving device 600, a plurality of strip-like driver cells 670 are arranged in the long side direction. The driver cell 670 generally includes a latch circuit that receives a signal corresponding to display data, a digital / analog converter that converts a digital signal into an analog signal, a level shifter that converts a signal level, an output circuit that outputs an output signal with high driving capability, and the like. Is formed. In the present invention, a digital / analog converter and an output circuit will be particularly described.

  The driver cell 670 has a strip shape and includes a DA converter block 650 in which a digital-analog converter is formed in a rectangular area and an output circuit block 660 in which an output circuit is formed. The long side direction of the driver cell 670 is the short side direction of the display driving device 600. In the long side direction of the driver cell 670, the output circuit block 660 is arranged closer to the chip edge 690 than the DA converter block 650.

  The output circuit block 660 includes an amplifier circuit block 610, a control switch block 620, a control circuit block 630, and an offset compensation capacitor block 640. The amplifier circuit block 610 is a block in which the amplifier circuit 210 including the amplifier stage 410 and the output stage 420 is formed. The control switch block 620 is a block in which the fourth to sixth switches 224 to 226 are formed, and is a block in which the switch group 220 that controls the connection relationship between the offset compensation capacitor 240 and the amplifier circuit 210 is formed. The control circuit block 630 is a block in which the control circuit 230 is formed. The offset compensation capacitor block 640 is a block in which the offset compensation capacitor 240 is formed.

  The amplifier circuit block 610, the control switch block 620, the control circuit block 630, and the offset compensation capacitor block 640 are arranged in a line in the long side direction of the driver cell 670. A control switch block 620 is disposed between the offset compensation capacitor block 640 and the amplifier circuit block 610, and a control circuit block 630 is disposed between the control switch block 620 and the amplifier circuit block 610. Note that the amplifier circuit block 610 is disposed closest to the chip edge 690 in the output circuit block 660. The output of the amplifier circuit block 610 is connected to the output pad 680. In this embodiment, the order of the amplifier circuit block 610, the control switch block 620, the control circuit block 630, and the offset compensation capacitor block 640 may be changed as long as they are arranged in a line. However, it is desirable that the positions of the amplifier circuit block 610, the control switch block 620, the control circuit block 630, or the offset compensation capacitor block 640 in each driver cell 670 coincide with each other in the long side direction of the display driving device 600.

  When the amplifier circuit block 610 of each driver cell 670 is collectively set as an amplifier circuit block group, and the control switch block 620 of each driver cell 670 is collectively set as a control switch block group, the amplifier circuit block group and the control switch block group are Individual power supply lines 601 and ground lines 602 each extending in the long side direction of the display driving device 600 are provided.

  The operation of a part of the display driving device 600 will be described with reference to FIG. FIG. 14 is a diagram showing a part of the output circuit 160. The output circuit 760 includes an amplifier circuit 210, a fifth switch 225, and an offset compensation capacitor 240. The amplifier circuit 210 is supplied with a first power supply. The second input terminal 212 of the amplifier circuit 210 and one end of the fifth switch 225 are connected. The other end of the fifth switch 225 is connected to one end of the offset compensation capacitor 240. The other end of the offset compensation capacitor 240 is connected to the ground. The fifth switch 225 is a switch composed of a MOS transistor, and is supplied with a first power source supplied to the amplifier circuit 210 as a substrate potential. In the present display driving device 600, it is assumed that the gradation voltage range is 0 to 18 V as an example.

  In the output circuit 760 described above, the offset compensation capacitor 240 is charged with a voltage obtained by adding the offset voltage to the output voltage during the sampling period. For example, when the offset compensation capacitor 240 is charged at the output circuit of many driver cells at 17.8 V close to the upper limit of the gradation voltage range, if a high voltage is simultaneously output from many output circuits, it is temporarily Therefore, the voltage of the power supply will drop. When the voltage is lower than the voltage charged in the offset compensation capacitor 240, the diode formed on the substrate operates and the charge charged in the offset compensation capacitor 240 is released. As a result, scheduled offset cancellation cannot be performed, and the accuracy of the offset cancellation operation is deteriorated.

  The display driving device showing the fourth embodiment will be described in detail with reference to FIG. In this figure, the output circuit 360 shown in FIG. 11 is arranged in the driver cell 670. In the display driving device 600, an output pad 680, a power supply pad 681, a ground pad 682, a control switch power supply pad 683, and an offset canceling ground pad 684 are arranged along the chip edge 690. The positions of the power supply pad 681, the ground pad 682, the control switch power supply pad 683, and the offset canceling ground pad 684 are not necessarily along the chip edge 690.

  The amplifier circuit 310 formed in the amplifier circuit block 610 is connected to the power supply pad 681 and the ground pad 682 via wirings 601A and 602A and supplied with power. The switch group 220 formed in the control switch block is connected to the control switch power supply pad 683 and the offset cancel ground pad 684 via the wirings 601B and 602B and supplied with power. The power supply pad 681, the ground pad 682, the control switch power supply pad 683, and the offset canceling ground pad 684 are supplied with power independently from the outside. The control circuit block 630 is connected to the power supply pad 681 and the ground pad 682 via the wirings 601A and 602A and is supplied with power, but may be separately supplied with power.

  In this embodiment, the amplifier circuit block 610, the control switch block 620, the control circuit block 630, and the offset compensation capacitor block 640 are arranged in a line in the long side direction of the driver cell 670, so that at least the amplifier circuit block 610 is arranged. In addition, it is possible to easily form individual power supply wiring 601 and ground wiring 602 in the control switch block 620. By forming individual power supply wirings 601A and B and ground wirings 602A and B in the amplifier circuit block 610 and the control switch block 620, the accuracy of offset cancellation is reduced even when the output voltage of each output circuit is concentrated. It is possible to perform an offset cancel operation without any problem. Of course, not only the amplifier circuit block 610 and the control switch block 620, but also the power supply and ground of the control circuit block 630 can be provided individually, which adversely affects the fluctuation of the power supply caused by the operation of the amplifier circuit block 610. Can be prevented. Note that the amplifier circuit block 610, the control switch block 620, the control circuit block 630, and the offset compensation capacitor block 640 do not have to be rectangular areas, and can be used in the present embodiment as long as power can be supplied independently to each other. It is possible to obtain the effect.

It is a display apparatus in Example 1 of this invention. FIG. 2 is a circuit diagram illustrating a specific example of an output circuit in FIG. 1. FIG. 3 is a circuit diagram showing an operation of the output circuit in FIG. 2. FIG. 3 is a circuit diagram illustrating a specific example of an amplifier circuit in FIG. 2. FIG. 5 is a circuit diagram showing an operation of the amplifier circuit in FIG. 4. It is the schematic of a general feedback circuit. FIG. 7 is a Bode diagram showing frequency characteristics of the feedback circuit shown in FIG. 6. It is the schematic which actualized the feedback circuit shown in FIG. It is a figure which shows the frequency characteristic of the feedback circuit shown in FIG. It is a graph which shows the amount of offsets which compared the past and the present invention. It is a circuit diagram which shows the output circuit in Example 2 of this invention. It is a layout figure which shows the drive device in Example 3 of this invention. FIG. 9 is a layout diagram illustrating a driving device according to a fourth embodiment of the present invention. It is principle explanatory drawing in Example 4 of this invention. It is a layout figure which shows the other drive device in Example 4 of this invention.

Explanation of symbols

100 Display Device 110 Display Panel 120 Source Drive IC
130 Gate drive IC
140 gradation voltage generation circuit 150 DA converter 160 output circuit 210 amplifying circuit 220 switch group 230 control circuit 240 offset compensation capacity

Claims (4)

A display driving device including a plurality of driver cells corresponding to an output,
The driver cell includes a decoder and an output circuit,
The output circuit is
An amplifier circuit, an offset cancel capacitor, a switch group for controlling a connection relationship between the offset cancel capacitor and the amplifier circuit, and a control circuit for controlling the switch group,
The control circuit is disposed between the amplifier circuit and the switch group,
The switch group is disposed between the offset canceling capacitor and the control circuit,
The display driving device, wherein the offset canceling capacitor is disposed between the decoder and the switch group. The switch group includes:
A first switch for controlling connection between one end of the offset canceling capacitor and the output of the amplifier circuit;
2. A second switch for controlling connection between one end of the offset canceling capacitor and the input of the amplifier circuit, wherein the first switch has higher on-resistance than the second switch. Item 4. The display driving device according to Item 1.   The display driving device according to claim 2, wherein the first switch has a smaller dimension than the second switch. Determining a driver cell block;
Determining a DA converter block and an output circuit block in the driver cell block;
An amplifier circuit block, a control switch block, a control circuit block, and an offset compensation capacitor block are determined in the output circuit block, and the control switch block is disposed between the offset compensation capacitor block and the amplifier circuit block, Disposing the control circuit block between the control switch block and the amplifier circuit block;
Arranging elements in the amplifier circuit block, the control switch block, the control circuit block, and the offset compensation capacitance block based on a design circuit diagram;
A layout method of a drive circuit comprising:

Images