JP2009245979A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can establish enough mechanical strength by using an insulation film, and to provide a manufacturing method for the device. <P>SOLUTION: A semiconductor device 11 is provided with a substrate 12. A plurality of layers formed of an insulation film 15 are stacked on the surface of the substrate 12. A conductive wiring layer 16 is pinched in between respective insulation films 15. A carbon-based material 18 is embedded in the insulation film 15, which is apart from the wiring layer 16. The carbon-based material 18 has a large mechanical strength. As a result, enough mechanical strength can be established in the insulation film 15. Similarly, sufficient mechanical strength can be established in the semiconductor device 11. Even if the surface of the insulation film 15 is planarized, the breakage of the insulation film 15 is avoided. In addition, when the semiconductor device 11 is to be mounted, for example, damages to the semiconductor device 11 can be avoided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as an LSI (Large Scale Integrated Circuit) chip.

For example, an LSI chip includes a silicon substrate. Circuit elements such as transistors are formed on the surface of the silicon substrate. A plurality of layers of insulating films are formed on the surface of the silicon substrate. A conductive wiring layer is sandwiched between the insulating films. In order to improve the operating speed of the LSI chip, it is desired that the dielectric constant of the insulating film be kept low. In order to suppress the dielectric constant, the insulating film is formed of a porous material. In this way, many holes are formed in the insulating film.
JP 2007-27223 A JP 2005-243695 A JP 2000-100894 A Akita Seiji et al., “Nanomechanics of Carbon Nanotubes”, Surface Science, Japan, 2000, Vol. 21, No. 9, p. 546-552 A. KRISHNAN et al., “Young's modules of single-walled nanotubes”, PHYSICAL REVIEW B, The American Physical Society, November 15, 1998, Volume 58, Number 20, p.14013-14019

  In manufacturing an LSI chip, an insulating film is laminated on the surface of the silicon substrate. After the formation of the insulating film, the surface of the insulating film is subjected to chemical mechanical polishing (CMP) treatment. In the chemical mechanical polishing process, the polishing pad applies a load to the insulating film. As described above, since holes are formed in the insulating film, the mechanical strength of the insulating film is low. As a result, when the load acting from the polishing pad is large, the insulating film is crushed. The insulating film will be damaged.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing the mechanical strength of an insulating film and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device includes a substrate, a plurality of insulating films stacked on the surface of the substrate, a conductive wiring layer sandwiched between the insulating films, and an insulating layer separated from the wiring layer. And a carbon-based material embedded in the film. In such a semiconductor device, the insulating film is prevented from contacting the wiring layer.

  A method of manufacturing a semiconductor device includes a step of forming a circuit element on a surface of a substrate, a step of laminating a first insulating film on the surface of the substrate, covering the circuit element with a first insulating film, and a surface of the first insulating film. Forming a recess in the first insulating film; forming a carbon-based material in the recess; and laminating a second insulating film on a surface of the first insulating film; and in the first insulating film and the second insulating film And a step of embedding a carbon-based material.

  As described above, the semiconductor device and the manufacturing method thereof can increase the mechanical strength of the insulating film.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 schematically shows a cross-sectional structure of a semiconductor device, that is, an LSI (Large Scale Integrated Circuit) chip 11 according to the first embodiment of the present invention. Such an LSI chip 11 is mounted on a wiring board (not shown) based on, for example, flip chip or face up. The LSI chip 11 includes a substrate 12. The substrate 12 is made of, for example, silicon. A circuit element such as a transistor 13 is formed on the surface of the substrate 12.

  A multilayer wiring board 14 that covers the transistor 13 is formed on the surface of the substrate 12. The multilayer wiring board 14 includes, for example, four layers of interlayer insulating films 15 stacked on the surface of the substrate 12. The interlayer insulating film 15 is formed of a low dielectric constant insulating material such as a spin-on-glass (SOG) material. Such an interlayer insulating film 15 is formed of a porous material. As a result, innumerable holes (not shown) are formed in the interlayer insulating film 15. The interlayer insulating film 15 spreads in a uniform film thickness parallel to the surface of the substrate 12.

  A conductive wiring layer 16 is formed on the surface of the interlayer insulating film 15. Thus, the wiring layer 16 is sandwiched between the interlayer insulating films 15. In the interlayer insulating film 15, conductive interlayer wirings, that is, vias 17 that penetrate the interlayer insulating film 15 in a direction orthogonal to the surface of the substrate 12 are formed. The via 17 connects the wiring layers 16 to each other. The wiring layer 16 and the via 17 are made of a conductor such as Cu.

  A carbon-based material 18 is embedded in the interlayer insulating film 15 at a position away from the wiring layer 16 and the via 17. Electrical connection between the carbon-based material 18 and the wiring layer 16 and via 17 is avoided. For the carbon material 18, for example, a long material such as a carbon nanotube (CNT) is used. The carbonaceous material 18 extends in a vertical direction perpendicular to the surface of the substrate 12. The carbonaceous material 18 is formed in a cylindrical shape, for example. The diameter of the carbonaceous material 18 is set to about 10 nm, for example. Here, for example, three carbon-based materials 18 are bundled to form a plurality of aggregates. The aggregate of the carbon-based materials 18 is separated from the wiring layer 16 and the via 17 by a predetermined interval. Such an interval is set according to the parasitic capacitance. If the parasitic capacitance is suppressed as much as possible, the delay of the electric signal transmitted through the wiring layer 16 and the via 17 is suppressed.

  Next, a method for manufacturing the LSI chip 11 according to the first embodiment of the present invention will be described. First, as shown in FIG. 2, the transistor 13 is formed on the surface of the substrate, that is, the wafer 21. Thereafter, the first insulating film 22 is laminated on the surface of the wafer 21 with a uniform film thickness. For lamination, a spin-on-glass material is applied by, for example, a spin coating method. After application, the spin-on-glass material is cured by heating. Thus, the first insulating film 22 covers the transistor 13 on the surface of the wafer 21. The first insulating film 22 is formed from a porous material.

  As shown in FIG. 3, a resist film 23 is formed in a predetermined pattern on the surface of the first insulating film 22. A predetermined gap 23 a is formed in the resist film 23. The surface of the first insulating film 22 is exposed in the gap 23a. The first insulating film 22 is etched based on the resist film 23. As a result, as shown in FIG. 4, a recess 24 is formed on the surface of the first insulating film 22. The recess 24 is formed with a bottomed hole. Thereafter, the resist film 23 is removed from the surface of the first insulating film 22.

  Thereafter, a plurality of catalyst metals 25 are disposed on the bottom surface of the recess 24. As the catalyst metal 25, for example, a transition metal alone such as Fe, Ni, and Co, a mixture of these transition metals, or a mixture of a transition metal and a metal such as Ti, Ta, or Ru may be used. A chemical vapor deposition (CVD) method is performed for the placement of the catalyst metal 25. As a result, as shown in FIG. 5, carbon nanotubes, that is, the carbon-based material 18 grow from the catalyst metal 25 in the recess 24. The carbon-based material 18 extends in a vertical direction orthogonal to the surface of the wafer 21. The carbonaceous material 18 is bundled in the recess 24.

  As shown in FIG. 6, a second insulating film 26 is laminated on the surface of the first insulating film 22. For lamination, a spin-on-glass material is applied by, for example, a spin coating method. After application, the spin-on-glass material is cured by heating. The second insulating film 26 is formed from a porous material. Thus, the inside of the recess 24 is filled with the second insulating film 26. An aggregate of the carbon-based material 18 is embedded in the first insulating film 22 and the second insulating film 26. Thereafter, a planarization process is performed on the surface of the second insulating film 26. A chemical mechanical polishing (CMP) method is performed for the planarization process. A flat surface is formed on the surface of the second insulating film 26. For example, chemical vapor deposition (CVD) may be performed when the first insulating film 22 and the second insulating film 26 are stacked.

  As shown in FIG. 7, a resist film 27 is formed on the surface of the second insulating film 26 with a predetermined pattern. A gap 27a is formed in the resist film 27 at a predetermined position. The surface of the second insulating film 26 is exposed in the gap 27a. Based on the resist film 27, the second insulating film 26 is etched. As a result, as shown in FIG. 8, a through hole 28 is formed in the first and second insulating films 22 and 26. The through hole 28 penetrates the first and second insulating films 22 and 26. An aggregate of the carbonaceous material 18 is disposed between the through holes 28. Thereafter, the resist film 27 is removed from the surface of the second insulating film 26.

  As shown in FIG. 9, the surface of the second insulating film 26 is plated. A plating film 29 is formed on the surface of the second insulating film 26. The plating film 29 is formed from a conductor such as Cu. The plated film 29 is filled in the through hole 28. Thereafter, the plating film 29 is subjected to a flattening process. A chemical mechanical polishing method is performed in the planarization process. Thus, the plating film 29 is removed on the surface of the second insulating film 26. As a result, a first interlayer insulating film 15 is formed on the surface of the wafer 21 as shown in FIG. Vias 17 are formed in the interlayer insulating film 15.

  As shown in FIG. 11, a wiring layer 16 is formed on the surface of the interlayer insulating film 15. In the formation, a resist film (not shown) having a predetermined pattern is formed on the surface of the interlayer insulating film 15. A plating film (not shown) is formed on the surface of the interlayer insulating film 15. After the plating film is formed, the resist film is removed. Thus, the wiring layer 16 is formed outside the resist film. Thereafter, an assembly of the interlayer insulating film 15, the wiring layer 16, the via 17, and the carbon-based material 18 in the second to fourth layers is formed by the same formation method. Thereafter, each LSI chip 11 is cut out from the wafer 21.

  In the LSI chip 11 as described above, when the interlayer insulating film 15 is formed, the first and second insulating films 22 and 26 are subjected to a planarization process based on a chemical mechanical polishing method. In the planarization process, for example, a predetermined load acts on the first insulating film 22 and the second insulating film 26 from the polishing pad. The first insulating film 22 and the second insulating film 26 are embedded with an aggregate of the carbon-based material 18. The carbonaceous material 18 extends in a vertical direction perpendicular to the surface of the substrate 12. The carbonaceous material 18 has a high mechanical strength. As a result, the mechanical strength of the first insulating film 22 and the second insulating film 26 is increased in the vertical direction perpendicular to the surface of the substrate 12. Although the first insulating film 22 and the second insulating film 26 are made of a porous material, damage to the first insulating film 22 and the second insulating film 26 is avoided. Thus, sufficient mechanical strength is established in the multilayer wiring board 14, that is, the LSI chip 11 as a whole. In addition, destruction of the LSI chip 11 can be avoided, for example, when mounted on a wiring board.

  The inventor has verified the mechanical characteristics of the LSI chip 11. Upon verification, a sample 31 was manufactured as shown in FIG. In the sample 31, a single-layer interlayer insulating film 33 was formed on the surface of the silicon substrate 32. A carbon nanotube, that is, a carbon-based material 34 is embedded in the interlayer insulating film 33. Here, for example, five carbon-based materials 34 are bundled. At this time, the mechanical properties of the interlayer insulating film 33 were measured based on the nanoindentation method. In measurement, the indenter of the nanoindenter was pressed against the surface of the arrangement region of the carbon-based material 34 and the surface of the non-arrangement region of the carbon-based material 34.

  As a result, an unloading curve shown in FIG. 13 was obtained in the arrangement region of the carbon-based material 34. Similarly, the unloading curve shown in FIG. 14 was obtained in the non-arranged region of the carbonaceous material 34. The slope of the unloading curve in the arrangement region, that is, the Young's modulus, was 12.39 [GPa]. The slope of the unloading curve in the non-arranged region, that is, the Young's modulus, was 10.59 [GPa]. As a result, the Young's modulus increased by, for example, 15% in the arrangement region compared to the non-arrangement region of the carbonaceous material 34. Therefore, it was confirmed that when the carbon-based material 34 is embedded in the interlayer insulating film 33, the Young's modulus, that is, the mechanical strength of the entire interlayer insulating film 33 is improved.

  FIG. 15 schematically shows the structure of an LSI chip 11a according to the second embodiment of the present invention. In the LSI chip 11a, the carbon-based material 18 extends over a plurality of interlayer insulating films 15. Here, the carbon-based material 18 is disposed across, for example, the first and second interlayer insulating films 15. Similarly, the carbonaceous material 18 is disposed across, for example, the third and fourth interlayer insulating films 15. In the interlayer insulating film 15, the wiring layer 16 and the via 17 are arranged away from the aggregate of the carbon-based materials 18. In addition, the same reference numerals are assigned to configurations and structures equivalent to those of the LSI chip 11 described above.

  In manufacturing the LSI chip 11a, as shown in FIG. 16, the first insulating film 41 is laminated on the surface of the wafer 21 in the same manner as the first insulating film 22 described above. A through hole 43 is formed on the surface of the first insulating film 41 based on an etching process. The through hole 43 penetrates the first insulating film 41. Subsequently, as shown in FIG. 17, a plating film 44 is formed on the surface of the first insulating film 41. The plated film 44 is filled in the through hole 43. Thereafter, the plating film 44 is subjected to a flattening process based on a chemical mechanical polishing method. As a result, a first interlayer insulating film 15 is formed on the surface of the wafer 21 as shown in FIG. Thereafter, a wiring layer 16 is formed on the surface of the interlayer insulating film 15 with a predetermined pattern.

  As shown in FIG. 19, a recess 45 is formed on the surface of the interlayer insulating film 15 outside the wiring layer 16. In forming the recess 45, an etching process is performed outside the resist film. A plurality of catalyst metals 25 are arranged on the bottom surface of the recess 45 formed in this way. A chemical vapor deposition method is performed for the placement of the catalyst metal 25. As a result, as shown in FIG. 20, the aforementioned carbon-based material 18 grows from the catalyst metal 25 in the recess 45. The carbonaceous material 18 extends in a vertical direction perpendicular to the surface of the wafer 21. Here, the carbon-based material 18 protrudes from the surface of the interlayer insulating film 15.

  As shown in FIG. 21, a second insulating film 46 is stacked on the surface of the first insulating film 41 in the same manner as the second insulating film 26 described above. Thus, the aggregate of the carbon-based material 18 is embedded in the first insulating film 41 and the second insulating film 46. Thereafter, the surface of the second insulating film 46 is subjected to a planarization process based on a chemical mechanical polishing method. Thereafter, as shown in FIG. 22, a through-hole 47 is formed in the second insulating film 46 based on the etching process. An aggregate of the carbon-based materials 18 is disposed between the through holes 47. Vias 17 are formed in the through holes 47 based on plating. The surface of the second insulating film 46 is subjected to a planarization process based on a chemical mechanical polishing method. Thereafter, the wiring layer 16 is formed on the surface of the second insulating film 46. Thus, the second interlayer insulating film 15 is formed. Thereafter, the third and fourth interlayer insulating films 15 are formed by the same formation method.

  In the LSI chip 11a as described above, when the interlayer insulating film 15 is formed, the first insulating film 41 and the second insulating film 46 are subjected to a planarization process based on a chemical mechanical polishing method. In the planarization process, a predetermined load acts on the first insulating film 41 and the second insulating film 46. In the first insulating film 41 and the second insulating film 46, an aggregate of the carbon-based material 18 is embedded. The carbonaceous material 18 extends in a vertical direction perpendicular to the surface of the substrate 12. The carbonaceous material 18 has a high mechanical strength. As a result, the mechanical strength of the first insulating film 41 and the second insulating film 46 is improved in the vertical direction orthogonal to the surface of the substrate 12. Although the first insulating film 41 and the second insulating film 46 are formed of a porous material, damage to the first insulating film 41 and the second insulating film 46 is avoided. Thus, sufficient mechanical strength is established in the multilayer wiring board 14, that is, the entire LSI chip 11a. In addition, for example, destruction of the LSI chip 11a is avoided during mounting on a wiring board.

  FIG. 23 schematically shows the structure of an LSI chip 11b according to the third embodiment of the present invention. In the LSI chip 11b, the carbon-based material 18 extends over all the interlayer insulating films 15. In the interlayer insulating film 15, the aggregate of the carbon-based materials 18 is arranged away from the wiring layer 16 and the via 17. Like reference numerals are attached to the structure or components equivalent to those of the aforementioned LSI chip 11a. In such an LSI chip 11b, sufficient mechanical strength is established in the multilayer wiring board 14, that is, the entire LSI chip 11b, in the same manner as the LSI chip 11 described above. In addition, for example, destruction of the LSI chip 11b is avoided during mounting on a wiring board.

  In manufacturing the LSI chip 11b, four layers of the first insulating film, that is, the interlayer insulating film 15, are formed on the surface of the wafer 21, as shown in FIG. A recess 51 is formed in the interlayer insulating film 15 based on, for example, an etching process. The recess 51 is formed from the fourth interlayer insulating film 15 to the first interlayer insulating film 15. The recess 51 is formed outside the wiring layer 16 and the via 17. The catalyst metal 25 is disposed on the bottom surface of the recess 51. As shown in FIG. 25, the carbonaceous material 18 grows in the recess 51 based on the catalyst metal 25. Thereafter, as shown in FIG. 26, the recess 51 is filled with a second insulating film, that is, an insulating film 52. Thereafter, a planarization process is performed on the surface of the insulating film 52 based on a chemical mechanical polishing method. Thus, the aggregate of the carbon-based materials 18 is embedded in the interlayer insulating film 15.

  In the LSI chips 11, 11 a, and 11 b as described above, the individual carbon material 18 is one selected from the group including carbon nanotubes, graphite sheets, peapods, carbon nanohorns, fullerenes, and carbon nanofibers. It may be formed from two or more. In using the graphite sheet, for example, a plurality of graphite sheets may be superposed in parallel to the surface of the substrate 12. The peapod, carbon nanohorn, and carbon nanofiber may be formed as a long material in the same manner as the carbon nanotube.

(Appendix 1) a substrate,
A plurality of insulating films stacked on the surface of the substrate;
A conductive wiring layer sandwiched between insulating films;
And a carbon-based material embedded in the insulating film while being separated from the wiring layer.

  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the carbonaceous material is bundled to form one or more aggregates.

  (Additional remark 3) The semiconductor device of Additional remark 1 or 2 WHEREIN: The said carbonaceous material is extended in the perpendicular direction orthogonal to the surface of the said board | substrate, The semiconductor device characterized by the above-mentioned.

  (Supplementary Note 4) In the semiconductor device according to Supplementary Note 2 or 3, the carbon material of each of the aggregates is selected from the group including carbon nanotubes, graphite sheets, peapods, carbon nanohorns, fullerenes, and carbon nanofibers. One or two or more semiconductor devices.

  (Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, further comprising an interlayer wiring penetrating the insulating film in a direction perpendicular to the surface of the substrate while being separated from the carbonaceous material. Semiconductor device.

  (Additional remark 6) The semiconductor device in any one of Additional remarks 1-5 WHEREIN: The said insulating film is formed from a porous material, The semiconductor device characterized by the above-mentioned.

(Appendix 7) A step of forming a circuit element on the surface of the substrate;
Laminating a first insulating film on the surface of the substrate and covering the circuit element with the first insulating film;
Forming a recess in the first insulating film from the surface of the first insulating film;
Forming a carbon-based material in the recess;
And a step of laminating a second insulating film on the surface of the first insulating film, and embedding a carbon-based material in the first insulating film and the second insulating film.

  (Additional remark 8) The manufacturing method of the semiconductor device of Additional remark 7 WHEREIN: The planarization process is performed to the surface of a said 2nd insulating film, The manufacturing method of the semiconductor device characterized by the above-mentioned.

  (Supplementary Note 9) In the method for manufacturing a semiconductor device according to Supplementary Note 7 or 8, in the formation of the carbonaceous material, a plurality of carbonaceous materials are grown in the vertical direction perpendicular to the surface of the substrate in the recess. A method of manufacturing a semiconductor device.

  (Additional remark 10) The manufacturing method of the semiconductor device of Additional remark 9 WHEREIN: The said carbonaceous material is bundled within the said hollow.

  (Appendix 11) In the method for manufacturing a semiconductor device according to any one of Appendixes 7 to 10, the carbon-based material is selected from the group including carbon nanotubes, graphite sheets, peapods, carbon nanohorns, fullerenes, and carbon nanofibers. One or two or more semiconductor device manufacturing methods.

  (Appendix 12) In the method of manufacturing a semiconductor device according to any one of Appendixes 7 to 11, a step of forming an interlayer wiring that penetrates the first insulating film between the recesses after the formation of the carbon-based material. A method for manufacturing a semiconductor device, further comprising:

  (Supplementary note 13) In the method of manufacturing a semiconductor device according to any one of supplementary notes 7 to 12, at least one of the first insulating film and the second insulating film is formed of a porous material. Production method.

  (Supplementary Note 14) In the method of manufacturing a semiconductor device according to any one of Supplementary Notes 7 to 13, any one of a spin coating method and a chemical vapor deposition method is performed in stacking the first insulating film and the second insulating film. A method for manufacturing a semiconductor device.

1 is a vertical sectional view schematically showing a structure of a semiconductor device, that is, an LSI chip according to a first embodiment of the present invention. It is a vertical sectional view schematically showing a process of laminating a first insulating film on the surface of a substrate. It is a vertical sectional view schematically showing a step of performing an etching process on the surface of the first insulating film. It is a vertical sectional view schematically showing a step of forming a depression on the surface of the first insulating film. It is a vertical sectional view which shows roughly the process of growing a carbonaceous material in a hollow. It is a vertical sectional view schematically showing a step of laminating a second insulating film on the surface of the first insulating film. It is a vertical sectional view schematically showing a step of performing an etching process on the surface of the second insulating film. It is a vertical sectional view schematically showing a step of forming a through hole in the first insulating film and the second insulating film. It is a vertical sectional view schematically showing a step of forming a plating film on the surface of the second insulating film. It is a vertical sectional view schematically showing a step of forming an interlayer wiring that penetrates a first insulating film between carbon-based materials. It is a vertical sectional view schematically showing a step of forming a wiring layer on the surface of the second insulating film. It is a vertical sectional view schematically showing the structure of a sample prepared for verification. It is a graph which shows the unloading curve measured in the arrangement | positioning area | region of a carbonaceous material. It is a graph which shows the unloading curve measured in the non-arrangement field of a carbon system material. It is a vertical sectional view schematically showing the structure of a semiconductor device according to a second embodiment of the present invention. It is a vertical sectional view schematically showing a step of forming a through hole in the first insulating film formed on the surface of the substrate. It is a vertical sectional view schematically showing a step of forming a plating film on the surface of the first insulating film. It is a vertical sectional view schematically showing a step of forming an interlayer wiring that penetrates the first insulating film. It is a vertical sectional view which shows roughly the process of arrange | positioning a catalyst metal in the hollow formed in the surface of a 1st insulating film. It is a vertical sectional view which shows roughly the process of growing a carbonaceous material in a hollow. It is a vertical sectional view schematically showing a step of laminating a second insulating film on the surface of the first insulating film. It is a vertical sectional view schematically showing a step of forming an interlayer wiring penetrating the second insulating film. It is a vertical sectional view schematically showing the structure of a semiconductor device according to a third embodiment of the present invention. It is a vertical sectional view schematically showing a step of forming a recess in a four-layer insulating film laminated on the surface of a substrate. It is a vertical sectional view which shows roughly the process of growing a carbonaceous material in a hollow. It is a vertical sectional view schematically showing a step of laminating a second insulating film on the surface of the first insulating film.

Explanation of symbols

  11 Semiconductor device (LSI chip), 12 substrate, 13 circuit element (transistor), 15 insulating film / first insulating film (interlayer insulating film), 16 wiring layer, 17 interlayer wiring, 18 carbon-based material, 21 substrate, 22 1 insulating film, 24 depressions, 26 second insulating film, 52 second insulating film (insulating film).

Claims (10)

A substrate,
A plurality of insulating films stacked on the surface of the substrate;
A conductive wiring layer sandwiched between insulating films;
And a carbon-based material embedded in the insulating film while being separated from the wiring layer.   2. The semiconductor device according to claim 1, wherein the carbonaceous material is bundled to form one or more aggregates.   3. The semiconductor device according to claim 1, wherein the carbon-based material extends in a vertical direction orthogonal to the surface of the substrate.   4. The semiconductor device according to claim 2, wherein the carbonaceous material of each of the aggregates is one or two selected from the group including carbon nanotubes, graphite sheets, peapods, carbon nanohorns, fullerenes, and carbon nanofibers. One or more semiconductor devices.   5. The semiconductor device according to claim 1, further comprising an interlayer wiring penetrating the insulating film in a direction perpendicular to the surface of the substrate while being separated from the carbon-based material. 6. .   6. The semiconductor device according to claim 1, wherein the insulating film is made of a porous material. Forming circuit elements on the surface of the substrate;
Laminating a first insulating film on the surface of the substrate and covering the circuit element with the first insulating film;
Forming a recess in the first insulating film from the surface of the first insulating film;
Forming a carbon-based material in the recess;
And a step of laminating a second insulating film on the surface of the first insulating film and embedding a carbon-based material in the first insulating film and the second insulating film.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the surface of the second insulating film is planarized.   9. The method of manufacturing a semiconductor device according to claim 7, wherein a plurality of carbon-based materials are grown in the vertical direction perpendicular to the surface of the substrate in the recess when forming the carbon-based material. A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 9, wherein the carbonaceous material is bundled in the recess.

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