JP2009236547A - Electronic clock - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that power consumption by a micro computer is increased since a voltage detecting circuit has a large number of voltage detecting values and the micro computer is operated each time of detection. <P>SOLUTION: Since a comparing rank setting circuit 702 does not output a comparison enabling signal HEN if a switching signal SL 3 is output, a halt release setting signal SET is not output from a comparator (2) 704, and a release signal HR is thereby not output from a release circuit 77. Namely, even if an overcharging detecting voltage V3 is detected, the micro computer 2 that is not necessary to operate can be controlled to remain in a stopped state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for operating an entire electronic timepiece in a low power consumption state by minimizing the operation of the microcomputer in an electronic timepiece composed of a microcomputer.

  In recent electronic timepieces, multifunctionalization has progressed, and a large number of devices using a microcomputer as a control circuit have appeared. As the microcomputer used in the timepiece, a low-power microcomputer is used in consideration of the low power consumption of the electronic timepiece using a small battery (see, for example, Patent Document 1).

  Low power microcomputers have been devised in various ways to achieve low power consumption. One of them is a HALT function for stopping the operation of the microcomputer and a HALT release function for releasing it. Since the power consumption during operation is very large, the microcomputer is controlled to maintain the HALT state as much as possible when the operation is unnecessary.

  For example, there is a battery voltage detection operation described in Patent Document 1. The battery voltage detection circuit performs battery voltage detection at regular intervals based on a time signal output from a circuit different from the microcomputer. At this time, the microcomputer is in the HALT state because no operation is required for the battery voltage detection circuit.

Further, the battery voltage detection circuit has a function of comparing the past battery voltage detection result with the current result, and if the comparison shows that the past and current states are different, that is, the battery voltage is changed. If it occurs, a HALT release signal is generated from the battery voltage detection circuit to the microcomputer, and the microcomputer performs various control operations accompanying changes in the battery voltage. As described above, in the conventional electronic timepiece, as a result of detection and comparison in the battery voltage detection circuit, the microcomputer is operated only when the past and current voltage states are different. The power consumption of the watch can be reduced.
JP 2005-147727 A (paragraphs 0083 to 0085, FIG. 2, FIG. 4, FIG. 9)

  However, the conventional electronic timepiece has the following problems. Any system can be assumed around the microcomputer, and each requires voltage information such as operating voltage. For example, in an analog electronic timepiece that stores electric power from a solar battery in a power storage unit and displays the time by a hand, a motor for driving the hand is a motor pulse having an appropriate driving force according to the voltage of the power storage unit. Therefore, it is necessary to detect the voltage of the power storage unit with a plurality of detected voltage values, and based on the information, the microcomputer calculates an appropriate motor pulse and outputs an appropriate control signal to the motor drive circuit. is there.

  Since the circuit system of an electronic timepiece using a microcomputer is used by changing a program according to a clock of various specifications, the system is designed to cover all specifications. In particular, the characteristics of motors and power storage units differ depending on the model, so the voltage detection circuit has a very large number of voltages in order to be able to share the circuit system according to multiple specifications of various electronic watches. A detection value must be prepared.

  As in the system described in Patent Document 1 described above, the voltage detection circuit compares the past battery voltage detection result with the current result, and if a change occurs in the battery voltage, a HALT release signal is sent to the microcomputer. Generated, the microcomputer prompts the operation to execute various control operations accompanying the change in the battery voltage, and executes a predetermined calculation operation. As described above, the voltage detection circuit has a large number of voltage detection values. Therefore, the microcomputer will operate each time it is detected.

  However, depending on the electronic timepiece having different specifications, not all voltage detection values are necessarily required. Therefore, there is a problem that power cannot be sufficiently saved if the microcomputer is frequently released by HALT.

  The present invention solves such problems and provides a technique capable of operating the entire electronic timepiece in a low power consumption state.

  In order to solve the above problems, the electronic timepiece of the invention has the following configuration.

  A microcomputer, at least one detection unit for executing a predetermined operation and outputting a processing request signal for executing a calculation process in the microcomputer based on the execution result, and output from the detection unit A processing request signal setting unit for setting whether or not the processing request signal is valid as the processing request signal for causing the microcomputer to execute the arithmetic processing.

  In addition, it has time measuring means for outputting an operation command signal for causing the detection section to intermittently execute the operation, and the time measuring means is set to an intermittent time via the microcomputer.

  Further, the microcomputer has a HALT function for stopping the operation, and the processing request signal is a release signal for canceling the stop state when the HALT function is in an operating state, or an interrupt request. It is a signal.

  In addition, the detection unit includes power supply voltage detection means for detecting the voltage of the power supply unit of the electronic timepiece.

  By implementing the present invention, the microcomputer is halt-released only when necessary, so that wasteful current consumption can be reduced.

In order to help understanding of the present invention, a comparative example will be described first. FIG. 1 shows a circuit configuration of an electronic timepiece using a low-power microcomputer, and this basic configuration is the same in both the comparative example and the present invention. In FIG. 1, reference numeral 1 denotes a crystal oscillator, which outputs an oscillation signal CK. A microcomputer 2 has an address bus (A_BUS), a data bus (D_BUS), and a halt release terminal HR_M for use in accessing peripheral circuits. Reference numeral 3 denotes a frequency dividing circuit that outputs a frequency-divided signal group SG. Reference numeral 4 denotes a solar cell, which generates a generated voltage HD by external light. Reference numeral 5 denotes a charge control circuit, which receives the generated voltage HD and supplies a charging current ID to the power storage unit 6 described later. Reference numeral 6 denotes a power storage unit including a rechargeable secondary battery. Reference numeral 7 denotes a voltage detection circuit group, which inputs the storage voltage VBT of the power storage unit 2 to the terminal VK, outputs the charge prohibition signal OD, and generates a halt release signal HR serving as a processing request signal from the terminal HR_S. Reference numeral 8 denotes an LCD control circuit, which outputs display data D_DATA according to instructions from the address bus (A_BUS) and data bus (D_BUS) of the microcomputer 2. An LCD display unit 9 displays desired information based on the display data D_DATA.

  Next, a voltage detection circuit group of a comparative example will be described with reference to FIG. FIG. 4 is a detailed configuration diagram of the voltage detection circuit group 7. In the figure, reference numeral 71 denotes a comparator. An input voltage VIN is input to a “+” terminal, a reference potential VREF is input to a “−” terminal, and a voltage comparison result CMP is output. A constant voltage circuit 72 outputs a reference potential VREF. Reference numeral 73 denotes a switching control circuit which inputs an address bus (A_BUS) and a data bus (D_BUS) of the microcomputer 2 and a 1 Hz signal in the divided signal group SG, and outputs switching signals SL1, SL2 and SL3. A result storage circuit 74 outputs an end signal END, a charge inhibition signal OD, and result data SD based on the switching signals SL1, SL2, and SL3 and the voltage comparison result CMP. Reference numeral 75 denotes a previous result storage circuit which inputs the result data SD of the result storage circuit 74 and outputs the previous result data KD. Reference numeral 76 denotes a comparator which inputs the result data SD and the previous result data KD and outputs the data comparison result PSET. Reference numeral 77 denotes a release circuit which inputs the data comparison result PSET, the address bus (A_BUS) and the data bus (D_BUS) of the microcomputer 2, and outputs a halt release signal HR.

  In FIG. 4, R0, R1, R2, and R3 are resistors, and TR1, TR2, and TR3 are N channel transistors (hereinafter, the N channel transistors are described as N channels). One end of the resistor R 0 is connected to the VDD that is the ground, and the other end is connected to one end of the resistor R 1 and the “+” terminal of the comparator 71. The other end of the resistor R1 is connected to one end of the resistor R2 and the drain of the N-channel TR1. The other end of the resistor R2 is connected to one end of the resistor 3 and the drain of the N-channel TR2. The other end of the resistor 3 is connected to the drain of the N-channel TR3. The sources of N-chan TR1, N-chan TR2, and N-chan TR3 are common and the storage voltage VBT is connected. Further, the switching signal SL1 of the switching control circuit 73 is input to the gate of the N-channel TR1. The switching signal SL2 of the switching control circuit 73 is input to the gate of the N-channel TR2. The switching signal SL3 of the switching control circuit 73 is input to the gate of the N-channel TR3.

  Next, before describing the operation of the comparative example, the relationship between the voltage change of the power storage unit 6 and the operation of the microcomputer 2 will be briefly described with reference to FIG. FIG. 5 is an explanatory diagram for explaining the relationship between the voltage transition of the power storage unit 6 and the operation of the microcomputer 2, and the curve shows the voltage transition state of the power storage unit 6. In FIG. 5, the charging area indicates a state where the power storage unit 6 is charged and the voltage is increased based on the power generation of the solar battery 4. The overcharge region indicates a state in which charging is forcibly stopped and the voltage does not increase any more because the voltage of the power storage unit 6 is in an overcharged state. The non-charging region indicates a state where the voltage of the power storage unit 6 is dropping because there is no power generation of the solar cell 4. The vertical axis indicates the voltage of the power storage unit 6, the voltage V3 is an overcharge detection voltage, V2 is a capacity shortage warning voltage, and V1 is an operation stop voltage of the electronic timepiece. The horizontal axis is the time axis, T1 is when it is detected that the voltage is higher than the overcharge detection voltage V3, T2 is when it is detected that the voltage is lower than the overcharge detection voltage V3, and T3 is the capacity This is when it is detected that the voltage is lower than the shortage warning voltage V2, and T4 is when it is detected that the voltage is lower than the operation stop voltage V1. The lower part of the figure shows the voltage detection timing of the storage voltage VBT of the power storage unit 6 and how the halt release HR_S of the microcomputer 2 is generated at the timing from T1 to T4. is there.

  FIG. 6 shows the display state of the LCD display unit 9, in which 91 is a normal display state, 92 is a charging warning display state, and 93 is a state where the display is turned off due to a voltage drop.

Next, the operation of the electronic timepiece of the comparative example will be described with reference to FIG. 1, FIG. 4, FIG. 5, and FIG. The microcomputer 2 first sends an address bus (A_B) by a transmission signal CK from the crystal oscillator 1.
US) and a data bus (D_BUS) are used to output a normal clock display command to the LCD control circuit 8. Thereafter, the LCD control circuit 8 receives the control signal from the microcomputer 2 and generates the display data D_DATA using the divided signal group SG, thereby causing the LCD display unit 9 to display the normal display state 91. . Similarly, the voltage detection circuit group 7 first receives an operation start command of the switching control circuit 73 of the voltage detection circuit group 7 from the microcomputer 2 by using the address bus (A_BUS) and the data bus (D_BUS). Without receiving the control signal from 2, the operation is continued with the 1 Hz signal of the divided signal group SG as the reference detection timing.

  First, an operation in a state where the charging region shown in FIG. 5 does not reach T1 will be described. The storage voltage VBT of the power storage unit 6 at the time of detection is equal to or higher than the capacity shortage warning voltage V2 and lower than the overcharge detection voltage V3. Since the solar cell 4 is irradiated with light, the power generation voltage HD is generated from the solar cell 4, and thus the charging control circuit 2 generates the charging current ID. The switching control circuit 73 sets the switching signal SL1 to the “H” level by the 1 Hz signal that is the reference detection timing. When the N-channel TR1 is “ON”, the resistors R0 and R1 become series resistors between the VDD and the storage voltage VBT, and a current flows. Therefore, a potential of VIN = VBT × R0 / (R0 + R1) is generated. The resistance value is set so that VIN = VREF when VBT = V1. However, since VBT is larger than V1, the comparator 71 outputs “L” at this time.

  Next, the switching control circuit 73 returns the switching signal SL1 to the “L” level and sets the switching signal SL2 to the “H” level. When the N-channel TR2 is “ON”, the resistors R0, R1, and R2 become series resistors between the VDD and the storage voltage VBT, and a current flows. Therefore, a potential of VIN = VBT × R0 / (R0 + R1 + R2) is generated. When VBT = V2, the resistance value is set so that VIN = VREF. However, since VBT is larger than V2, the comparator 71 outputs “L” even at this time.

  Further, the switching control circuit 73 returns the switching signal SL2 to the “L” level and sets the switching signal SL3 to the “H” level. When the N-channel TR3 is turned “ON”, the resistors R0, R1, R2, and R3 become series resistors and current flows between the VDD and the storage voltage VBT. Therefore, a potential of VIN = VBT × R0 / (R0 + R1 + R2 + R3) is generated. However, since the storage voltage VBT is smaller than V3, the comparator 71 outputs “H” at this time. From the result, the result storage circuit 74 stores the switching signals SL1, SL2, and SL3 and the voltage comparison result CMP = “L” level, and the result storage circuit 74 outputs the end signal END, thereby switching control circuit 73. Stops working.

  Subsequently, the comparator 76 compares the result data SD and the previous result data KD. Since the storage voltage VBT of the power storage unit 6 is not less than the capacity shortage warning voltage V2 and less than the overcharge detection voltage V3, the result data SD and the previous result data KD are compared. The result data KD are the same, and the data comparison result PSET is not output. Therefore, the release circuit 77 does not output the halt release signal HR. The microcomputer 2 continues the HALT state.

  Next, the operation at the timing of T1 will be described. The storage voltage VBT of the power storage unit 6 has already exceeded the overcharge detection voltage V3 due to charging. Similarly to the above, the switching control circuit 73 sequentially switches the switching signals SL1, SL2, and SL3, but the comparators 71 are all at the “L” level. Therefore, the result storage circuit 74 stores the switching signals SL1, SL2, and SL3 and the voltage comparison result CMP = “L” level, outputs the end signal END, and outputs the charge inhibition signal OD. Therefore, the charging control circuit 5 stops charging the power storage unit 6 by stopping the charging current ID.

The comparator 76 compares the result data SD and the previous result data KD. At this time, the previous result data KD is the switching signal and the output of the comparator (SL1, SL2, SL3, COMP) = (L, L, H, H), and the switching signal of the result data SD and the output of the comparator are (SL1, SL2 , SL3, COMP) = (L, L, H, L), the comparator 76 outputs the data comparison result PSET, and the release circuit 72 outputs the halt release signal HR. Therefore, the microcomputer 2 is halt released. The microcomputer 2 confirms the signal input to the halt release terminal HR_M, confirms that it is a release instruction, and then resets the release circuit 77 using the address bus (A_BUS) and data bus (D_BUS). Therefore, the release circuit 77 stops the halt release signal HR. The switching signal of the result data SD and the output of the comparator at the timing between T1 and T2 are (SL1, SL2, SL3, COMP) = (L, L, H, L), and there is no change, so the description is omitted.

  Next, at the timing of T2, the generation voltage HD is not generated from the solar cell 4 because there is no light irradiation. Therefore, it is in the non-charging region, and the voltage of the power storage unit 6 is reduced by the operation power-off of the system including the oscillator 1 and the like. The storage voltage VBT of the power storage unit 6 is less than the overcharge detection voltage V3 and more than the capacity shortage warning voltage V2. At the timing T2, the previous result data KD of the previous result circuit 75 indicates that the switching signal and the output of the comparator are (SL1, SL2, SL3, COMP) = (L, L, H, L). The storage circuit 74 stores (SL1, SL2, SL3, COMP) = (L, L, H, H) as the switching signal of the result data SD and the output of the comparator. The release circuit 72 is reset using the address bus (A_BUS) and the data bus (D_BUS).

  At the timing between T2 and T3, the switching signal of the result data SD and the output of the comparator are (SL1, SL2, SL3, COMP) = (L, L, H, H), and there is no change, so the description is omitted.

  Further, the non-charged state is continued, the storage voltage VBT of the power storage unit 6 decreases, and when the T3 timing is reached, the storage voltage VBT of the power storage unit 6 becomes less than the capacity shortage warning voltage V2 and the operation stop voltage V1 or more. Therefore, at the timing T3, the previous result data KD of the previous result circuit 75 is that the switching signal and the output of the comparator are (SL1, SL2, SL3, COMP) = (L, L, H, H). Since the result storage circuit 74 stores the switching signal of the result data SD and the output of the comparator (SL1, SL2, SL3, COMP) = (L, H, L, H), the microcomputer 2 is halt-released. As a result, the release circuit 72 is reset using the address bus (A_BUS) and the data bus (D_BUS), and a battery voltage warning display command is output to the LCD control circuit 8. Therefore, the LCD control circuit 8 switches the LCD display unit 9 from the normal display state 91 shown in FIG.

  At the timing between T3 and T4, the switching signal of the result data SD and the output of the comparator are (SL1, SL2, SL3, COMP) = (L, H, L, H), and there is no change, so the description is omitted.

Next, the storage voltage VBT of the power storage unit 6 further decreases, and when the timing T4 is reached, the storage voltage VBT of the power storage unit 6 becomes less than the operation stop voltage V1. Therefore, at the timing T4, the previous result data KD of the previous result circuit 75 is that the switching signal and the output of the comparator are (SL1, SL2, SL3, COMP) = (L, H, L, H). Since the result storage circuit 74 stores the switching signal of the result data SD and the output of the comparator (SL1, SL2, SL3, COMP) = (H, L, L, H), the microcomputer 2 is halt-released. The address bus (A_BUS), the data bus (D_BUS)
) Is used to reset the release circuit 77 and output a display stop command to the LCD control circuit 8 for power saving. Therefore, the LCD control circuit 8 switches the LCD display unit 9 from the charging warning display state 92 in FIG.

  The above is the operation of the electronic timepiece equipped with the low power microcomputer in the comparative example. According to the comparative example, since the microcomputer 2 is halt-released at all voltage change points detected by the voltage detection circuit group 7, at the timings T1 and T2 at which the display state of the LCD display unit 9 does not need to be changed. However, the microcomputer 2 is halt-released unnecessarily, so that sufficient power saving cannot be achieved.

Next, an electronic timepiece according to an embodiment of the present invention will be described with reference to the drawings. Similar to the comparative example, in the present embodiment, the battery voltage detection technique of the electronic timepiece will be described as an example. FIG. 1 shows a circuit configuration of an electronic timepiece using a low-power microcomputer. Since this basic configuration is the same as that of the comparative example, description thereof is omitted.
FIG. 2 shows the voltage detection circuit group 7 in the present embodiment. First, only the configuration different from the comparative example will be described. A time interval control circuit 701 is connected to the divided signal group SG and the address bus (A_BUS) and data bus (D_BUS) of the microcomputer 2 and outputs a time interval signal TM. The time interval control circuit 701 is configured such that the output interval of the time interval signal TM is set via the microcomputer 2. Reference numeral 702 denotes a comparison rank setting circuit which inputs an instruction of the address bus (A_BUS) and data bus (D_BUS) of the microcomputer 2 and switching signals SL1 to SL3 and outputs a comparison permission signal HEN. Reference numeral 703 denotes a previous state storage circuit that inputs the switching signals SL1 to SL3 and the voltage comparison result COMP and outputs the previous voltage comparison result ZCOMP. Reference numeral 704 denotes a comparator (2) which receives the voltage comparison result COMP, the previous voltage comparison result ZCOMP, and the comparison enable signal HEN, and outputs a halt release set signal SET. A release circuit 77 receives the data comparison result signal SET, the address bus A_BUS and the data bus D_BUS of the microcomputer 2, and outputs a halt release signal HR. The voltage detection circuit group 7 corresponds to the detection unit of the present invention, and the comparison rank setting circuit 702 corresponds to the processing request signal setting unit of the present invention.

  Next, the operation of this embodiment will be described. The microcomputer 2 outputs a comparison permission signal HEN when SL1 and SL2 are generated to the comparison rank setting circuit 702 via the address bus (A_BUS) and data bus (D_BUS), and when SL3 is generated. Setting is made so that the comparison enable signal HEN is not output. Thereafter, the microcomputer 2 is set to output a time interval signal TM of 1 Hz to the time interval control circuit 701 via the address bus (A_BUS) and the data bus (D_BUS). As a result, the time interval signal TM is output at 1 Hz intervals, so that the switching control circuit 73 operates at 1 Hz intervals. After completing the setting, the microcomputer 2 shifts to the halt state.

  Next, the operation of this embodiment according to the change in the storage voltage VBT of the storage unit 6 will be described with reference to FIG. In FIG. 3, until T1, the stored voltage VBT is not less than the capacity shortage warning voltage V2, but the overcharge detection voltage V3 has not yet been detected. When the time interval signal TM comes, the switching control circuit 73 first outputs the switching signal SL1. Then, the comparator 71 compares the operation stop voltage V1 with the storage voltage VBT. At this time, since the storage voltage VBT exceeds the operation stop voltage V1, the voltage comparison result CMP of the comparator 71 outputs “L” level. At that time, since there was no change from the previous voltage value, the previous voltage comparison result ZCMP output from the previous state storage circuit 703 also outputs “L” level. The comparison rank setting circuit 702 outputs a comparison permission signal HEN when the switching signal SL1 is output. Therefore, the comparator 704 compares the voltage comparison result CMP with the previous voltage comparison result ZCMP, but since the result is the same, the halt release set signal SET is not output.

  Next, the switching signal SL2 is switched. Similarly, since the storage voltage VBT exceeds the capacity shortage warning voltage V2, the voltage comparison result CMP of the comparator 71 outputs “L” level. Also at this time, since there was no change from the previous voltage value, the previous voltage comparison result ZCMP output from the previous state storage circuit 703 also outputs the “L” level. When the switching signal SL2 is output, the comparison rank setting circuit 702 outputs a comparison permission signal HEN. Therefore, the comparator 704 compares the voltage comparison result CMP with the previous voltage comparison result ZCMP, but since the result is the same, the halt release set signal SET is not output.

  Further, the switching control circuit 73 outputs a switching signal SL3. At this time, since the storage voltage VBT does not exceed the overcharge detection voltage V3, the voltage comparison result CMP of the comparator 71 outputs “H” level. Further, since there is no change between the previous voltage value and the previous voltage comparison result ZCMP output from the previous state storage circuit 703, the “H” level is also output. When the switching signal SL3 is output to the comparison rank setting circuit 702, the comparison enable signal HEN is not output, so that the comparator (2) 704 does not execute the comparison operation of the voltage comparison result CMP and the previous voltage comparison result ZCMP. Therefore, the halt release set signal SET is not output.

  Next, when time T1 is reached, the storage voltage VBT of the storage unit 6 has already exceeded the overcharge detection voltage V3. When the switching signals SL1 and SL2 are output, the result is the same as described above, and there is no change in operation, so the description is omitted.

  When the switching signal SL3 is output, the voltage comparison result CMP of the comparator 71 outputs “L” level. Since the previous state comparison circuit 703 outputs “H” level from the previous voltage comparison result ZCMP, the data is different. Therefore, the comparator (2) 704 outputs the halt release set signal SET. However, since the comparison rank setting circuit 702 does not output the comparison permission signal HEN when the switching signal SL3 is output, the halt release set signal SET is not output from the comparator (2) 704. 77 does not output the release signal HR.

  That is, even if the overcharge detection voltage V3 is detected, the microcomputer 2 that does not need to operate can be controlled to be stopped.

  Since the voltage comparison result CMP of the comparator 71 outputs “L” level, the result storage circuit 74 outputs the charge prohibition signal OD, stops the operation of the charge control circuit 5, and supplies power to the power storage unit 6. Charging operation is stopped.

  Similarly, the same is true at the time T2, and at time T2, the voltage of the power storage unit 2 is already less than the overcharge voltage V3 and there is a change in the detection voltage, but the comparison rank setting circuit 702 is designated for comparison permission for SL3. Therefore, the comparison enable signal HEN is not output. Therefore, the halt release set signal SET is not output.

  Furthermore, when the voltage of the power storage unit 2 decreases and reaches the time T3, it already reaches between the capacity shortage warning voltage V2 and the operation stop voltage V1. At this time, when the switching signal SL2 is generated, an operation different from the conventional operation occurs.

When switched to the switching signal SL2, the voltage comparison result CMP of the comparator 71 outputs an “H” level. Further, the previous state storage circuit 703 outputs “L” level from the previous voltage comparison result ZCMP. Further, the comparison rank setting circuit 702 outputs the comparison permission signal HEN when the switching signal SL2 is output, so that the comparator 704 outputs the voltage comparison result CMP.
And the previous voltage comparison result ZCMP are compared, and the result is different, so the halt release set signal SET is output.

  Thereby, the microcomputer 2 resets the release circuit 72 using the address bus (A_BUS) and the data bus (D_BUS) and outputs a battery voltage warning display command to the LCD control circuit 8 by being halt released. Therefore, the LCD control circuit 8 switches the LCD display unit 9 from the normal display state 91 shown in FIG.

  Further, at time T4, the operation is the same as that at T3. When the voltage of the power storage unit 6 decreases and reaches the time T4, the voltage is already less than the operation stop voltage V1, and when the switching signal SL1 is generated, the voltage comparison result CMP of the comparator 71 outputs the “H” level. Further, the “L” level is output from the previous voltage comparison result ZCMP of the previous state storage circuit 703. Since the comparison rank setting circuit 702 outputs the comparison permission signal HEN when the switching signal SL1 is output, the comparator 704 compares the voltage comparison result CMP with the previous voltage comparison result ZCMP, and the result is different. The halt release set signal SET is output.

  When halted, the microcomputer 2 resets the release circuit 77 using the address bus (A_BUS) and data bus (D_BUS) and outputs a display stop command to the LCD control circuit 8 for power saving. Therefore, the LCD control circuit 8 switches the LCD display unit 9 from the charging warning display state 92 in FIG.

  In the present embodiment, the voltage detection circuit of the power storage unit 6 has been described as the detection unit, but the present invention is not limited to this, and may be configured according to the potential of a regulator or the like, You may construct | assemble in the said invention with respect to the detection data value with which it becomes a generated current detection circuit or the A / D converter with a sensor.

  In the present invention, the comparison rank setting circuit is a mask ROM or a non-volatile memory that does not involve a microcomputer, although data setting is performed by an address bus (A_BUS) and a data bus (D_BUS) by a microcomputer. It may be configured.

  In the present invention, the entire system may be composed of a plurality of chips or a single chip.

  As apparent from the above description, in a circuit with a plurality of potential relationships, etc., the microcomputer is not released unnecessarily by halt release only under the necessary conditions, so that power consumption is extremely low. A low electronic watch can be provided.

It is a circuit block diagram of the comparative example and the electronic timepiece which is one embodiment of the present invention. It is a block diagram of the voltage detection circuit group of the electronic timepiece which is one Embodiment of this invention. It is explanatory drawing explaining the relationship between the voltage transition of the electrical storage part of the electronic timepiece which is one Embodiment of this invention, and operation | movement of a microcomputer. It is a block diagram of the voltage detection circuit group of a comparative example. It is explanatory drawing explaining the relationship between the voltage transition of the electrical storage part of a comparative example, and the operation | movement of a microcomputer. It is explanatory drawing which shows the display state of a LCD display part.

Explanation of symbols

2 Microcomputer 7 Voltage detection circuit group 701 Time interval control means 702 Comparison rank setting circuit 703 Previous state storage circuit 77 Release circuit

Claims (4)

A microcomputer, at least one detection unit for executing a predetermined operation and outputting a processing request signal for executing a calculation process in the microcomputer based on the execution result, and output from the detection unit A processing request signal setting unit for setting whether or not to enable the processing request signal for executing the arithmetic processing in the microcomputer among the processing request signals. clock. 2. A time measuring means for outputting an operation command signal for causing the detection section to intermittently execute an operation, wherein the time measuring means is set to an intermittent time via the microcomputer. The electronic watch described. The microcomputer has a HALT function for stopping the operation, and the processing request signal is a release signal or an interrupt request signal for releasing the stop state when the microcomputer is in the operating state. The electronic timepiece according to claim 1, wherein the electronic timepiece is provided. The electronic timepiece according to any one of claims 1 to 3, wherein the detection unit includes power supply voltage detection means for detecting a voltage of a power supply unit of the electronic timepiece.

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