JP2009235459A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a gold bump plating step is carried out to form an electrode having 15-20 μm height in a semiconductor product such as LCD driver and a gold bump surface shape of the LCD driver requires flatness to improve the contact property in the installation and on the other hand, the position of the installation is carried out by image recognition and the bump surface appearance requires low-glossiness to make the reflection low by diffusing the light in every direction, then there is an antinomy that the surface roughness is necessary to be kept in micro but the bump cross-section shape is necessary to be flat in macro. <P>SOLUTION: The final part of a second step of plating (high current density plating step after initial low current density plating) in a two stage plating is carried out under low current density. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plating technique in a method for manufacturing a semiconductor device (or a semiconductor integrated circuit device), and particularly to a technique effective when applied to a gold plating technique.

  Japanese Patent Laid-Open No. 2002-256486 (Patent Document 1) or US Patent Publication No. 2002-0127829 (Patent Document 2) discloses a uniform temperature distribution in a wafer in a general plating process on a semiconductor wafer. In order to achieve this, it is disclosed that temperature control including heating and cooling is performed.

  Japanese Patent Application Laid-Open No. 2005-136225 (Patent Document 3) or US Patent Publication No. 2005-0023149 (Patent Document 4) describes a process for plating copper or the like for forming embedded wiring on a semiconductor wafer. It is disclosed that temperature control including heating and cooling is performed in order to keep the temperature of the temperature constant.

  Japanese Laid-Open Patent Publication No. 7-142425 (Patent Document 5) discloses that in a general plating process on a semiconductor wafer, temperature adjustment including heating is performed in order to make the temperature distribution in the wafer uniform. Has been.

  In Japanese Patent Laid-Open No. 11-200058 (Patent Document 6), in a plating process of copper or the like for forming an embedded wiring on a semiconductor wafer, a wafer is formed in order to form a temperature gradient according to the distance from the wafer. It is disclosed that the temperature is adjusted to a constant temperature including heating from the back surface.

  Japanese Patent Application Laid-Open No. 11-92948 (Patent Document 7) or US Pat. No. 6,544,585 (Patent Document 8) describes a bubble on a wafer in a plating process of copper or the like for forming an embedded wiring on a semiconductor wafer. In order to remove this, it is disclosed that the plating solution is boiled by heating from the back surface of the wafer.

JP 2002-256486 A US Patent Publication No. 2002-0127829 JP 2005-136225 A US Patent Publication No. 2005-0023149 JP-A-7-142425 Japanese Patent Laid-Open No. 11-200058 Japanese Patent Laid-Open No. 11-92948 US Pat. No. 6,544,585

  Semiconductor products such as LCD (Liquid Crystal Display) drivers have a gold BUMP plating process for forming electrodes having a height of about 15 to 20 μm. The gold BUMP surface shape of the LCD driver is required to be flat to improve the contact property during mounting. On the other hand, since the positioning at the time of mounting is performed by image recognition, the BUMP surface appearance is required to be matte with little light reflection. In order to make the BUMP surface matte, it is important to maintain a certain degree of surface roughness microscopically in order to diffuse light in all directions. At first glance, there is a conflicting problem.

  A low current density is desirable for flattening and matting of the BUMP surface, but on the other hand, there is a demerit that the plating processing time is increased. This is because, when the current density is low, the gold particle lump becomes large, and therefore it becomes dull, the base step is not traced, and the center is convex. On the other hand, when the current density is increased, the gold grain lump becomes small, so that it becomes glossy and the base step is traced, so that the center is concave. Therefore, in general, two-step plating is performed in which plating is performed at a low current density for a few minutes at the initial stage of plating and at a high current density thereafter.

  However, due to recent high-density mounting, further flattening is required while maintaining a dull state. In order to answer this seemingly contradictory request, the inventors of the present application have made the following examination.

  That is, the plating solution temperature (plating solution temperature) is set to a solution temperature that can achieve a desired BUMP surface flatness and matte finish within an appropriate plating solution temperature range (about 50 ° C. to 65 ° C.). It is common to implement. Increasing the plating solution temperature within this appropriate plating solution temperature range (almost the same effect as reducing the current density) results in an increase in the size of the gold particles, resulting in matte, no trace of the underlying step, and convex center. Become a mold. On the other hand, when the plating solution temperature is lowered (substantially the same effect as increasing the current density), the gold grain lump becomes small and glossy, and the base step is traced, so that the center becomes concave. Thus, the parameters that determine the microscopic and macroscopic characteristics of the gold-plated surface have two elements, the current density and the plating solution temperature, and the novel combination can solve the seemingly contradictory problems described above. This has been clarified by the present inventors.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to the present invention, the end of the second stage of the two-stage plating (the high current density plating step after the initial low current density plating) is made to have a low current density.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the gold bump plating step is a three-step step including an initial low current density plating, an intermediate high current density plating step, and a final low current density plating, so that macroscopic flatness is not sacrificed. The glossy surface in the intermediate high current density plating step can be rendered matte again.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component;
(D2) On the first plating layer, an average plating particle agglomeration is smaller than the first plating layer and has a second thickness larger than the first thickness, and gold is a main component. Depositing a second plated layer;
(D3) On the second plating layer, the average plating particle agglomeration is larger than the second plating layer and has a third thickness smaller than the second thickness, and gold is a main component. Depositing a third plating layer.

  2. In the method of manufacturing a semiconductor device according to the item 1, the temperature of the plating solution is substantially constant in the step (d).

  3. In the method of manufacturing a semiconductor device according to the item 1 or 2, the second thickness is at least three times as large as the first thickness and the third thickness.

  4). In the method of manufacturing a semiconductor device according to item 1 or 2, the second thickness is four times or more the first thickness and the third thickness.

  5). In the method of manufacturing a semiconductor device according to the item 1 or 2, the second thickness is five times or more the first thickness and the third thickness.

  6). 6. In the method for manufacturing a semiconductor device according to any one of items 1 to 5, the plating current density in the lower step (d2) is larger than the plating current density in the lower steps (d1) and (d3).

  7. 6. In the method for manufacturing a semiconductor device according to any one of 1 to 5, the plating current density in the lower step (d2) is two times or more larger than the plating current density in the lower steps (d1) and (d3). .

  8). 6. In the method for manufacturing a semiconductor device according to any one of 1 to 5, the plating current density in the lower step (d2) is three times or more larger than the plating current density in the lower steps (d1) and (d3). .

  9. 9. In the method of manufacturing a semiconductor device according to any one of 1 to 8, the temperature of the wafer in the substep (d2) is lower than the temperature of the wafer in the substeps (d1) and (d3).

  10. 9. In the method of manufacturing a semiconductor device according to any one of 1 to 8, the temperature of the wafer in the substep (d2) is 2 degrees Celsius than the temperature of the wafer in the substeps (d1) and (d3). That's low.

  11. 11. In the method of manufacturing a semiconductor device as described above in any one of 1 to 10, the temperature of the wafer in the lower step (d2) is reduced by cooling the second main surface of the wafer. And the temperature of the wafer in (d3).

  12 11. In the method of manufacturing a semiconductor device according to any one of 1 to 10, the temperature of the wafer in the substeps (d1) and (d3) is set by heating the second main surface of the wafer. The temperature is higher than that of the wafer in the step (d2).

13. A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component by electroplating with a first plating current density;
(D2) having a second thickness greater than the first thickness by electroplating with a second plating current density higher than the first plating current density on the first plating layer; Depositing a second plating layer comprising gold as a major component;
(D3) On the second plating layer, by electroplating with a third plating current density lower than the second plating current density, the third thickness is smaller than the second thickness; Depositing a third plating layer comprising gold as a major component;

  14 In the method of manufacturing a semiconductor device according to the item 13, the temperature of the plating solution is substantially constant in the step (d).

  15. 15. In the method of manufacturing a semiconductor device according to item 13 or 14, the upper surface of the third plating layer is not a glossy surface.

  16. 16. In the method for manufacturing a semiconductor device according to any one of items 13 to 15, the second thickness is three times or more the first thickness and the third thickness.

  17. 16. In the method for manufacturing a semiconductor device according to any one of items 13 to 15, the second thickness is four times or more the first thickness and the third thickness.

  18. 16. In the method for manufacturing a semiconductor device according to any one of items 13 to 15, the second thickness is not less than five times the first thickness and the third thickness.

  19. 19. In the method for manufacturing a semiconductor device according to any one of items 13 to 18, the plating current density in the lower step (d2) is twice or more larger than the plating current density in the lower steps (d1) and (d3). .

  20. 20. In the method for manufacturing a semiconductor device as described above in any one of 13 to 19, the plating current density in the lower step (d2) is three times or more larger than the plating current density in the lower steps (d1) and (d3). .

  21. 21. In the method of manufacturing a semiconductor device as described above in any one of 13 to 20, the temperature of the wafer in the substep (d2) is lower than the temperature of the wafer in the substeps (d1) and (d3).

  22. 21. In the method of manufacturing a semiconductor device as described above in any one of 13 to 20, the temperature of the wafer in the lower step (d2) is 2 degrees Celsius than the temperature of the wafer in the lower steps (d1) and (d3). That's low.

  23. 23. In the method of manufacturing a semiconductor device as described above in any one of 13 to 22, the temperature of the wafer in the lower step (d2) is reduced by cooling the second main surface of the wafer. And the temperature of the wafer in (d3).

  24. 23. In the method of manufacturing a semiconductor device as described above in any one of 13 to 22, the temperature of the wafer in the substeps (d1) and (d3) is adjusted by heating the second main surface of the wafer. The temperature is higher than that of the wafer in the step (d2).

25. A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component at a first wafer temperature;
(D2) On the first plating layer, gold is a major component at a second wafer temperature having a second thickness greater than the first thickness and lower than the first wafer temperature. Depositing a second plating layer;
(D3) On the second plating layer, gold is a major component at a third wafer temperature having a third thickness smaller than the second thickness and higher than the second wafer temperature. Depositing a third plating layer.

  26. In the method for manufacturing a semiconductor device according to the item 25, the plating current density is substantially constant in the step (d).

  27. 27. In the method of manufacturing a semiconductor device according to 25 or 26, the upper surface of the third plating layer is not a glossy surface.

  28. 28. In the method for manufacturing a semiconductor device as described above in any one of 25 to 27, in the step (d), the temperature of the plating solution is substantially constant.

  29. 29. In the method of manufacturing a semiconductor device as described above in any one of 25 to 28, the second thickness is three times or more the first thickness and the third thickness.

  30. 29. In the method of manufacturing a semiconductor device according to any one of items 25 to 28, the second thickness is four times or more the first thickness and the third thickness.

  31. 29. In the method of manufacturing a semiconductor device according to any one of items 25 to 28, the second thickness is five times or more the first thickness and the third thickness.

  32. 32. In the method for manufacturing a semiconductor device according to any one of 25 and 27 to 31, the plating current density in the lower step (d2) is larger than the plating current density in the lower steps (d1) and (d3).

  33. 32. In the method of manufacturing a semiconductor device according to any one of 25 and 27 to 31, the plating current density in the lower step (d2) is two times or more than the plating current density in the lower steps (d1) and (d3). ,large.

  34. 32. In the method of manufacturing a semiconductor device according to any one of 25 and 27 to 31, the plating current density in the lower step (d2) is three times or more than the plating current density in the lower steps (d1) and (d3). ,large.

  35. 35. In the method of manufacturing a semiconductor device as described above in any one of 25 to 34, the temperature of the wafer in the substep (d2) is lower than the temperature of the wafer in the substeps (d1) and (d3).

  36. 35. In the method of manufacturing a semiconductor device as described above in any one of 25 to 34, the temperature of the wafer in the substep (d2) is 2 degrees Celsius than the temperature of the wafer in the substeps (d1) and (d3). That's low.

  37. 37. In the method of manufacturing a semiconductor device as described above in any one of 25 to 36, the temperature of the wafer in the sub-process (d2) is controlled by cooling the second main surface of the wafer. And the temperature of the wafer in (d3).

  38. 37. In the method of manufacturing a semiconductor device as described above in any one of 25 to 36, the temperature of the wafer in the substeps (d1) and (d3) is adjusted by heating the second main surface of the wafer. The temperature is higher than that of the wafer in the step (d2).

39. A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component at a first wafer temperature;
(D2) On the first plating layer, gold is a major component at a second wafer temperature having a second thickness greater than the first thickness and lower than the first wafer temperature. Depositing a second plating layer.

  40. In the method for manufacturing a semiconductor device according to Item 39, the plating current density is substantially constant in the step (d).

  41. 41. In the method of manufacturing a semiconductor device according to 39 or 40, the temperature of the wafer in the sub-process (d1) is set such that the temperature of the wafer in the sub-process (d2) is increased by heating the second main surface of the wafer. It is higher than the temperature.

  42. 42. In the method for manufacturing a semiconductor device as described above in any one of 39 to 41, in the step (d), the temperature of the plating solution is substantially constant.

  43. 43. In the method of manufacturing a semiconductor device according to any one of Items 39 to 42, the second thickness is not less than three times the first thickness and the third thickness.

  44. 43. In the method for manufacturing a semiconductor device according to any one of Items 39 to 42, the second thickness is four times or more the first thickness and the third thickness.

  45. 43. In the method of manufacturing a semiconductor device according to any one of Items 39 to 42, the second thickness is not less than five times the first thickness and the third thickness.

  46. 46. In the method for manufacturing a semiconductor device according to any one of 39 and 41 to 45, the plating current density in the lower step (d2) is larger than the plating current density in the lower step (d1).

  47. 46. In the method for manufacturing a semiconductor device according to any one of 39 and 41 to 45, the plating current density in the lower step (d2) is twice or more larger than the plating current density in the lower step (d1).

  48. 46. In the method for manufacturing a semiconductor device according to any one of 39 and 41 to 45, the plating current density in the lower step (d2) is three times or more larger than the plating current density in the lower step (d1).

  49. 49. In the method for manufacturing a semiconductor device according to any one of 39 to 48, the temperature of the wafer in the lower step (d2) is lower than the temperature of the wafer in the lower step (d1).

  50. 49. In the method for manufacturing a semiconductor device according to any one of Items 39 to 48, the temperature of the wafer in the lower step (d2) is two degrees Celsius or lower than the temperature of the wafer in the lower step (d1).

  51. 51. In the method of manufacturing a semiconductor device according to any one of 39, 40, and 42 to 50, the temperature of the wafer in the sub-step (d2) is obtained by cooling the second main surface of the wafer. It is made lower than the temperature of the wafer in the lower step (d1).

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary. However, unless otherwise specified, these are not independent from each other. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “gold bump electrodes” and the like include not only pure gold but also gold alloys containing gold as a main component. Similarly, the term “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and other additives. Needless to say. Similarly, the term “silicon oxide film” refers not only to relatively pure undoped silicon oxide, but also to FSG (Fluorosilicate Glass), TEOS-based silicon oxide, and SiOC ( Silicon Oxicarbide) or Carbon-doped Silicon oxide (OSG) (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass) and other thermal oxide films, CVD oxide films, SOG (Spin ON Glass) , Nano-clustering silica (NSC), etc., coated silicon oxide, silica-based low-k insulating film (porous insulating film) in which pores are introduced in similar members, and these are the main Needless to say, it includes a composite film with another silicon-based insulating film as an essential component.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer or an SOI wafer, and a semiconductor layer or the like. Needless to say, composite wafers are also included. The term “wafer temperature” refers to the temperature at the center of the back surface of the wafer, unless a location is specified or it is obvious and not.

  6). The term “plating solution temperature” refers to the amount of plating solution flowing into the plating cup, except when a specific location is specified (eg, “plating solution temperature in the plating solution tank”) or unless otherwise apparent. Represents temperature.

  7. The term “thickness of the plating layer” for a bump electrode or the like refers to the thickness of the central portion of the bump electrode or the like unless a location is specified or it is obvious and not.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

1. Description of device mounting state by gold bump plating process of manufacturing method of semiconductor device of this embodiment (mainly FIGS. 3 and 4)
FIG. 3 is a top view of a chip showing an example of a semiconductor device (semiconductor integrated circuit device) according to a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a structure in which a semiconductor device (semiconductor integrated circuit device) according to a method for manufacturing a semiconductor device according to an embodiment of the present invention is mounted on a liquid crystal display device. Based on these, the mounting state of the device by the gold bump plating process of the manufacturing method of the semiconductor device of this embodiment will be described.

  As described above, FIG. 3 is a chip top view showing an example of a semiconductor device (semiconductor integrated circuit device) according to the method for manufacturing a semiconductor device of one embodiment of the present invention. This is an example of a chip for a liquid crystal display device, that is, an LCD (Liquid Crystal Display) driver. On the chip 51, a circuit region 52 and a large number of bump electrodes 15 around it are arranged.

  FIG. 4 is a cross-sectional view showing a structure in which a semiconductor device (semiconductor integrated circuit device) according to a method for manufacturing a semiconductor device of an embodiment of the present invention is mounted on a liquid crystal display device. As shown in FIG. 4, conductor external electrodes such as a plurality of ITO (Indium Tin Oxide) electrodes 53 are provided on the liquid crystal substrate 55 of the liquid crystal display device, and a plurality of gold bumps on the LCD driver chip 51 are provided. The electrode 15 is electrically connected via an anisotropic conductive film 54, that is, an ACF (Anisotropic Conductive Film). At this time, if the gold bump electrode 15 has a variation in thickness, there is a high possibility of causing a problem such as an increase in connection resistance between some of the electrodes.

2. Detailed description of one example of the entire process, plating cup (plating cup structure X), and plating process of the semiconductor device manufacturing method of the present embodiment (mainly FIGS. 1, 2 and 5 to 12)
FIG. 1 is a sequence diagram of a plating process (current variable three-step process: plating process A) in a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the basic structure of a plating cup used in the plating process in the method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a device structure before bump formation processing in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a device structure in a UBM (Under Bump Metal) forming step in the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 7 is a schematic cross-sectional view showing a device structure in which the photoresist coating process is completed in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 8 is a schematic cross-sectional view showing a device structure in which the photoresist developing process is completed in the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional view showing a device structure in which a plating step is completed in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing a device structure in which the resist removal step in the semiconductor device manufacturing method according to one embodiment of the present invention is completed. FIG. 11 is a schematic cross-sectional view showing a device structure in which the UBM etch process is completed in the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 12 is a perspective view showing a coating portion of a resist coating apparatus used in the method for manufacturing a semiconductor device according to an embodiment of the present invention. Based on these, details of an example of the entire process, plating cup, and plating process of the semiconductor device manufacturing method of the present embodiment will be described.

  First, the basic structure of the plating cup 3 will be described with reference to FIG. Hereinafter, a case of a 200φ silicon single crystal wafer will be described in detail as an example. As shown in FIG. 2, the wafer holder 24 of the plating tank 2 in the plating cup 3 is provided with a ring-shaped cathode electrode 32 on which the wafer 1 faces down (the device surface 1a of the wafer 1). Is set downward). A plating solution supply pipe 45 is connected to the lower end of the plating cup 3. The plating solution 2 passes through the anode electrode 34, hits the first main surface 1 a of the wafer 1, changes its direction, and is returned from the plating solution discharge pipe 46 to the tank. The second main surface 1 b (back surface) of the wafer 1 is pressed against the cathode electrode 32 by a wafer presser 42 by a pressing spring 43 and a wafer holder driving cylinder 44.

  Next, a bump forming process in the method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 5, a first main surface 1a (first main surface 1a is a device surface) of a wafer 1 on which a large number of devices and wirings (formed of silicon oxide films and various metal layers) are formed. A final passivation film 61 such as silicon nitride (which may be an inorganic film as well as an inorganic film) is formed on the second main surface 1b, that is, the main surface opposite to the back surface 1b of the wafer). A pad opening 63 is provided in a portion corresponding to the aluminum pad 62 formed. Next, as shown in FIG. 6, a UBM (Under Bump Metal) film, for example, a titanium film 64 (lower layer) having a thickness of about 175 micrometers, for example, a palladium film 65 (upper layer) having a thickness of about 175 micrometers is formed by sputtering. (These UBM materials are merely examples, and other similar materials are not excluded. For example, a palladium film may be a gold film, but the use of a palladium film increases reliability. In addition, there is a merit that the material price is slightly lower than gold.) As shown in FIG. 7, a positive resist film 12 having a thickness of, for example, about 19 to 25 microns (for example, 20 microns) is formed thereon using the above coating system and method. The resist solution used here includes, for example, a positive resist for diazo / naphthoquinone / novolak thick film manufactured by Tokyo Ohka Kogyo Co., LTD., Product name “PMER P-LA900PM”, and the like. A film resist may be used instead of the coating resist. As shown in FIG. 8, an opening 66 is formed by exposing and developing the resist.

Next, as shown in FIG. 9, a gold layer that becomes a bump electrode 15 having a thickness of, for example, about 15 micrometers is embedded in the opening 66 by electroplating (at this time, the temperature of the supplied plating solution is, for example, 53 degrees Celsius). Is kept at a constant temperature). This step is divided into three sub-steps as shown in FIG. First, in the first step, a relatively low current density (for example, 0) is obtained until the step of the UBM film is overcome, that is, between 0 and 2 micrometers (the first thickness Ta is about 2 micrometers). Electroplating at about ^{2 A} / dm ² ). In this way, the particle size of the plating layer becomes relatively large, and an effect of filling the step can be expected, so that a relatively flat first plating layer 15a can be obtained.

In the second step, that is, between 2 and 14 micrometers (the second thickness Tb is about 12 micrometers), it is necessary to perform plating as fast and flat as possible. Electroplating is performed at a high current density (for example, about 0.75 A / dm ² ) to obtain the second plating layer 15 b. In this way, the agglomerate diameter of the plating layer becomes relatively small, and a flat plating layer (the center is not convex) is formed on the flat base as it is.

In the third step, that is, between 14 and 15 micrometers (the third thickness Tc is about 1 micrometer), it is necessary to obtain a surface roughness that is not substantially a glossy surface. Again, electroplating is performed at a relatively low current density (for example, about 0.2 A / dm ² ) to obtain a third plating layer 15 c whose upper surface is matte. In this way, the agglomerate diameter of the plating layer becomes relatively large, and as a result, it becomes dull (the upper surface of the plating layer is not glossy).

  Here, the second thickness is preferably three times or more as compared with the first thickness and the third thickness in consideration of processing time or shape characteristics. Moreover, when flatness is severe, 4 times or more is desirable. Furthermore, 5 times or more is more preferable. This is because when the thickness of the bump electrode is about 15 μm, the base step is usually about 2 μm or less, and the uppermost layer only needs to be larger than the maximum grain size, and therefore usually 0 This is because it is enough if it is 5 micrometers or more. This also applies to other plating processes described below.

  The relationship of the current density in each of the above steps is as follows. That is, in the first step, it is necessary to eliminate the ground level difference, and in the third step, it is necessary to make the surface substantially matte. On the other hand, in the second step, it is necessary to ensure a plating state that is as fast as possible and that maintains the flatness of the base. Therefore, in order to realize such plating characteristics, the plating current density in the second step is preferably at least twice the plating current density in the first step and the third step. Furthermore, in order to shorten the processing time and the like, 3 times or more is more preferable. This is the same when the current density is made variable in the other plating processes described below. However, in that case, it is necessary to consider that the required characteristics can be obtained with a smaller difference due to the synergistic effect of the current density and the wafer temperature.

  Here, as the plating solution, a gold sulfite-based plating solution (the main component is an aqueous solution of sodium gold sulfite, ethylenediamine, inorganic acid salt, and other trace additives), which is a non-cyanide plating solution with little environmental problems, is used. ing. Needless to say, it is also possible to use a cyan plating solution if sufficient consideration is given to the environment.

  Next, as shown in FIG. 10, the resist film 12 is removed. Finally, as shown in FIG. 11, unnecessary UBM films are selectively removed by wet etching using the gold bumps 15 as a mask. This completes the bump electrode.

  FIG. 12 is a perspective view showing a coating portion of a resist coating apparatus used in the method for manufacturing a semiconductor device according to an embodiment of the present invention. The resist solution dropped from the nozzle 67 is stretched onto the resist film 12 having a predetermined thickness as the spin chuck 41 rotates at high speed on the wafer 1.

3. Description of plating apparatus used for gold plating process in manufacturing method of semiconductor device of this embodiment (mainly FIGS. 13 to 15)
FIG. 13 is a top view of a single wafer plating apparatus used for a plating process in the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 14 is a schematic cross-sectional view for explaining a plating solution circulation mechanism of a single wafer plating apparatus used in a plating process in a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 15 is an enlarged cross-sectional view showing a contact state between the cathode electrode of the single wafer plating apparatus used in the gold bump plating process and the conductive layer on the device surface of the wafer in the manufacturing method of the semiconductor device according to the embodiment of the present invention FIG. 15 is a diagram (corresponding to a portion C in FIG. 14). Based on these, the plating apparatus used for the gold plating process in the method for manufacturing the semiconductor device of the present embodiment will be described.

  First, the overall structure of the single wafer plating apparatus will be described with reference to FIG. As shown in FIG. 13, the single wafer plating device 74 is operated by an operation panel 75. First, a wafer transfer container containing a plurality of processed wafers 1 is accommodated in the loader / unloader unit 76. The wafer 1 accommodated is adjusted in position or the like by a wafer position or an alignment unit 77, and is first transferred to a cleaning unit 79 by a transfer unit 78 (wafer transfer mechanism). After cleaning, the transfer unit 78 again performs plating. -It is set in the vacant plating cup 3 in the cup array part 73. Thereafter, several tens of minutes of plating processes are performed. Here, the plating solution tank 68 supplies the plating solution 2 (FIG. 14) to all the plating cups 3 (14 in this case).

  Next, the state of circulation of the plating solution 2 between the plating cup 3 (same as FIG. 2: plating cup structure X) and the plating solution tank 68 will be described with reference to FIG. As shown in FIG. 14, the plating solution 2 in the plating solution tank 68 is, for example, about 53 degrees Celsius (if necessary, between 50 degrees Celsius and 65 degrees Celsius) by a heater 69, a thermometer 70, and a heater output control device 71. The temperature is controlled to an appropriate constant temperature). The plating solution 2 is sent to each plating cup 3 through the plating solution supply pipe 45 by the pump 72 and returned to the tank 68 from the plating solution discharge pipe 46.

  Next, details of how to set the wafer 1 on the plating cup 3 described with reference to FIG. 2 will be described. FIG. 15 shows the state of contact between the cathode electrode 32 of the single wafer plating apparatus 74 used in the gold bump plating process and the conductive layer on the device surface 1a of the wafer 1 in the method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. Details of the method of loading the wafer 1 onto the wafer holder 24 will be described with reference to FIG. As shown in FIG. 15, when the cathode ring electrode 32 is brought into contact with the palladium layer 65 at the terminal end of the wafer 1 and the back surface 1b of the wafer 1 is pushed downward by the wafer presser 42 from above, the lip seal 33 is formed. The structure is deformed, and the resist is crushed and sealed so that the plating solution does not leak.

4). Details of another example of the plating process of the manufacturing method of the semiconductor device of this embodiment and description of the plating cup used therefor (mainly FIGS. 9 and 16 to 18)
FIG. 16 is a sequence diagram of a plating process (wafer temperature variable 3-step process: plating process B) in the method of manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 17 is a cross-sectional view (when not heated) showing another plating cup structure (plating cup structure Y) used in the plating process in the method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view (during heating) showing another plating cup structure (plating cup structure Y) used in the plating process in the method of manufacturing a semiconductor device according to one embodiment of the present invention. Details of another example of the plating process of the semiconductor device manufacturing method of the present embodiment and a plating cup used therefor will be described with reference to FIGS. 9 and 16 to 18.

  First, the structure of the plating cup used below will be described. Except as described below, it is the same as FIG. As shown in FIGS. 17 and 18, the wafer holder 42 is provided with a heat block 4. A wafer heater 5 is embedded in the heat block 4, and the wafer heater control unit 8 controls the temperature of the heat block 4 to be a certain temperature (here, for example, Celsius) higher than the temperature of the plating solution. 56 degrees). The heat block 4 is pressed against the back surface 1b of the wafer 1 by the heat block pressing spring 7 and the heat block driving cylinder 6 controlled by the wafer heater control unit 8 (wafer heating ON state) or separated. The temperature of the back surface 1b of the wafer 1 rises and falls depending on whether or not (wafer heating OFF state).

  Next, details of the plating process corresponding to FIG. 9 will be described. This corresponds to a modification of the part of FIG. 9 of the overall process described in FIGS.

As shown in FIG. 9, a gold layer that becomes a bump electrode 15 having a thickness of, for example, about 15 micrometers is embedded in the opening 66 by electroplating with a constant current density (for example, about 0.75 A / dm ² ). The temperature of the supplied plating solution is maintained at a constant temperature of, for example, about 53 degrees Celsius). This step is executed by being divided into three sub-steps as shown in FIG. First, in the first step, the heat block as shown in FIG. 18 is used until the level difference of the UBM film is overcome, that is, between 0 and 2 micrometers (the first thickness Ta is about 2 micrometers). Electroplating is performed with 4 in close contact with the back surface 1 b of the wafer 1. By doing so, the particle size becomes relatively large, and the effect of filling the step can be expected, and the relatively flat first plating layer 15a can be obtained. This is because the temperature of the front surface 1a of the wafer 1 rises as a result of the rise of the temperature of the back surface 1b of the wafer 1, and thus the temperature of the substantial plating solution on the surface 1a of the wafer 1 rises.

  In the second step, that is, between 2 and 14 micrometers (second thickness Tb is about 12 micrometers), it is necessary to perform plating as fast and flat as possible. In this manner, electroplating is performed in a state where the heat block 4 is separated from the back surface 1b of the wafer 1 to obtain a second plating layer 15b.

  In the third step, that is, between 14 and 15 micrometers (the third thickness Tc is about 1 micrometer), it is necessary to obtain a surface roughness that is substantially non-glossy. Again, as shown in FIG. 18, electroplating is performed in a state where the heat block 4 is in close contact with the back surface 1b of the wafer 1 to obtain a third plated layer 15c whose upper surface is matte. Here, as the plating solution, a gold sulfite-based plating solution, which is a non-cyanide plating solution with little environmental problems, is used. ing. Needless to say, it is also possible to use a cyan plating solution if sufficient consideration is given to the environment.

  The relationship between the wafer temperatures in the above steps is as follows. That is, in the first step, it is necessary to eliminate the ground level difference, and in the third step, it is necessary to make the surface substantially matte. On the other hand, in the second step, it is necessary to ensure a plating state that is as fast as possible and that maintains the flatness of the base. Therefore, in order to realize such plating characteristics, the wafer temperature in the second step is desirably lower by 2 degrees Celsius than the wafer temperature in the first step and the third step. This also applies to the case where the wafer temperature is made variable in other plating processes described below. However, in that case, it is necessary to consider that the required characteristics can be obtained with a smaller difference due to the synergistic effect of the current density and the wafer temperature.

  The advantage of this plating process B (wafer temperature variable 3-step process) is that it has a relatively high current density throughout the process compared to the plating process A (current variable 3-step process) described in section 2. Since the plating process can be performed, the processing time can be shortened.

  If the matte surface of the bump electrode is not particularly required, the last step of the plating process B can be omitted (wafer temperature variable two-step process: plating process C). . However, in this case, in order to ensure the same bump thickness, it is necessary to lengthen the second step accordingly.

5. Other plating apparatus used in the gold plating process in the manufacturing method of the semiconductor device of the present embodiment and the details of the plating process using the same (mainly FIG. 19)
FIG. 19 is a cross-sectional view showing still another plating cup structure (plating cup structure Z) used in the plating process (plating process B or C) in the semiconductor device manufacturing method according to the embodiment of the present invention. During cooling). Based on this, another plating apparatus used in the gold plating process in the semiconductor device manufacturing method of the present embodiment will be described.

  First, the structure of the plating cup used below will be described. Except as described below, this embodiment is the same as FIGS. As shown in FIG. 19, the wafer holder 42 is provided with a cooling block 56. A cooling water pipe 60 is embedded in the cooling block 56, and the wafer cooling control unit 59 causes the temperature of the cooling block 56 to be a constant temperature (for example, 53 degrees Celsius) lower than the temperature of the plating solution. Is controlled. Whether the cooling block 56 is pressed against the back surface 1b of the wafer 1 by the cooling block pressing spring 58 and the cooling block drive cylinder 57 controlled by the wafer cooling control unit 59 (wafer heating ON state) or away (wafer heating). In the OFF state, the temperature of the back surface 1b of the wafer 1 increases and decreases.

  Next, details of the plating process corresponding to FIG. 9 will be described. This corresponds to a modification of the part of FIG. 9 of the overall process described in FIGS.

As shown in FIG. 9, a gold layer that becomes a bump electrode 15 having a thickness of, for example, about 15 micrometers is embedded in the opening 66 by electroplating with a constant current density (for example, about 0.75 A / dm ² ). The temperature of the supplied plating solution is maintained at a constant temperature of, for example, about 56 degrees Celsius). This step is executed by being divided into three sub-steps as shown in FIG. First, in the first step, the cooling block 56 is placed on the back surface of the wafer 1 until the step of the UBM film is overcome, that is, between 0 and 2 micrometers (the first thickness Ta is about 2 micrometers). Electroplating is performed in a state separated from 1b. By doing so, the particle size becomes relatively large, and the effect of filling the step can be expected, and the relatively flat first plating layer 15a can be obtained. This is because the temperature of the plating solution is originally set high.

  In the second step, that is, between 2 and 14 micrometers (second thickness Tb is about 12 micrometers), it is necessary to perform plating as fast and flat as possible. Thus, electroplating is performed in a state where the cooling block 56 is in close contact with the back surface 1b of the wafer 1 to obtain the second plating layer 15b. This is because the temperature of the back surface 1b of the wafer 1 is lowered, and the temperature of the front surface 1a of the wafer 1 is also lowered. As a result, the temperature of the plating solution on the front surface 1a portion of the wafer 1 is substantially lowered.

  In the third step, that is, between 14 and 15 micrometers (the third thickness Tc is about 1 micrometer), it is necessary to obtain a surface roughness that is not substantially a glossy surface. Again, electroplating is performed in a state where the cooling block 56 is separated from the back surface 1b of the wafer 1 to obtain a third plating layer 15c whose upper surface is matte. Here, as the plating solution, a gold sulfite-based plating solution (the main component is an aqueous solution of sodium gold sulfite, ethylenediamine, inorganic acid salt, and other trace additives), which is a non-cyanide plating solution with little environmental problems, is used. ing. Needless to say, it is also possible to use a cyan plating solution if sufficient consideration is given to the environment.

  The advantage of this plating process B (wafer temperature variable 3-step process) is that it has a relatively high current density throughout the process compared to the plating process A (current variable 3-step process) described in section 2. Since the plating process can be performed, the processing time can be shortened.

  If the matte surface of the bump electrode is not particularly required, the last step of the plating process B can be omitted (wafer temperature variable two-step process: plating process C). . However, in this case, in order to ensure the same bump thickness, it is necessary to lengthen the second step accordingly.

6). Description of Variations of Gold Plating Process in Manufacturing Method of Semiconductor Device of this Embodiment It goes without saying that the plating cup structures Y and Z described above can be used for any of the plating processes A, B, and C. Further, the plating process sequence of FIG. 1 or FIG. 16 has been specifically described only for the most typical (the limit where the plating current density is constant and the limit where the wafer temperature is constant) for convenience of description. This is not to exclude common forms. In practice, it is more common to set the optimum conditions corresponding to various requirements in mass production by appropriately changing the plating current density and the wafer temperature as necessary.

7). Summary The invention made by the present inventors has been specifically described with reference to an example of a plating process when forming gold bumps based on the embodiment. However, the present invention is not limited thereto and does not depart from the gist of the invention. It goes without saying that various changes can be made in the range.

  For example, it goes without saying that the present invention can be similarly applied to the formation of solder bumps other than gold, silver bumps, and the like. Needless to say, the present invention is not limited to bump formation and can be widely applied when handling materials.

  In the present embodiment, the process of providing an opening in the resist film and plating the opening has been described. However, as in the copper damascene process (or silver damascene process), the resist film is not used and the wafer is used. Needless to say, the present invention can also be applied to a process of plating a metal film on almost the entire surface.

  Furthermore, in the above-described embodiment, the wafer face down type plating apparatus that does not reverse the cup that is widely used at present is specifically described as an example, but the present invention is not limited thereto. Needless to say, the present invention can also be applied to a cup inversion type (wafer face up type) plating apparatus.

  In the above embodiment, the case where a 200φ wafer is mainly used has been specifically described as an example. However, the present invention is not limited thereto, and it is needless to say that the present invention can be similarly applied to a 300φ wafer or 450φ. .

It is a sequence diagram of the plating process (current variable 3 step process) in the manufacturing method of the semiconductor device of one embodiment of the present invention. It is sectional drawing which shows the structure of the basic plating cup used for the plating process in the manufacturing method of the semiconductor device of one embodiment of this invention. It is a chip top view showing an example of a semiconductor device (semiconductor integrated circuit device) by a manufacturing method of a semiconductor device of one embodiment of the invention of this application. It is sectional drawing which shows the structure where the semiconductor device (semiconductor integrated circuit device) by the manufacturing method of the semiconductor device of one embodiment of this invention was mounted in the liquid crystal display device. It is a schematic cross section which shows the device structure before the bump formation process in the manufacturing method of the semiconductor device of one embodiment of this invention. 1 is a schematic cross-sectional view showing a device structure of a UBM (Under Bump Metal) forming step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. It is a schematic cross section which shows the device structure in which the photoresist application | coating process in the manufacturing method of the semiconductor device of one embodiment of this invention was completed. It is a schematic cross section which shows the device structure in which the photoresist image development process in the manufacturing method of the semiconductor device of one embodiment of this invention was completed. It is a schematic cross section which shows the device structure which the plating process in the manufacturing method of the semiconductor device of one embodiment of this invention completed. It is a schematic cross section which shows the device structure which the resist removal process in the manufacturing method of the semiconductor device of one embodiment of this invention completed. It is a schematic cross section showing the device structure in which the UBM etch process in the manufacturing method of the semiconductor device of one embodiment of the present invention is completed. It is a perspective view which shows the application part of the resist coating device used for the manufacturing method of the semiconductor device of one embodiment of this invention. It is a top view of the single wafer plating apparatus used for the plating process in the manufacturing method of the semiconductor device of one embodiment of this invention. It is a schematic cross section explaining the plating solution circulation mechanism of the single wafer plating apparatus used for the plating process in the manufacturing method of the semiconductor device of one embodiment of the present invention. The expanded sectional view which shows the mode of the contact of the cathode electrode of the single wafer plating apparatus used for the gold bump plating process in the manufacturing method of the semiconductor device of one embodiment of this invention, and the conductive layer of the device surface of a wafer (figure) 14 corresponding to part C). It is a sequence diagram of the plating process (wafer temperature variable 3 step process) in the manufacturing method of the semiconductor device of one embodiment of this invention. It is sectional drawing (at the time of non-heating) which shows the structure of the other plating cup used for the plating process in the manufacturing method of the semiconductor device of one embodiment of this invention. It is sectional drawing (at the time of a heating) which shows the structure of the other plating cup used for the plating process in the manufacturing method of the semiconductor device of one embodiment of this invention. It is sectional drawing (at the time of cooling) which shows the structure of the further another plating cup used for the plating process in the manufacturing method of the semiconductor device of one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 1a 1st main surface (device surface) (device surface)
2 Plating solution (plating tank)
3 plating cup 12 resist film 15 gold bump electrode 15a first plating layer 15b second plating layer 15c third plating layer 66 (resist film) opening 68 plating solution tank 74 single wafer plating device Ta first Thickness Tb Second thickness Tc Third thickness

Claims (20)

A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component;
(D2) On the first plating layer, an average plating particle agglomeration is smaller than the first plating layer and has a second thickness larger than the first thickness, and gold is a main component. Depositing a second plated layer;
(D3) On the second plating layer, the average plating particle agglomeration is larger than the second plating layer and has a third thickness smaller than the second thickness, and gold is a main component. Depositing a third plating layer.     In the method of manufacturing a semiconductor device according to the item 1, the temperature of the plating solution is substantially constant in the step (d).     In the method of manufacturing a semiconductor device according to the item 1, the second thickness is not less than three times the first thickness and the third thickness.     In the method for manufacturing a semiconductor device according to the item 1, the second thickness is not less than four times the first thickness and the third thickness.     In the method of manufacturing a semiconductor device according to the item 1, the second thickness is not less than five times the first thickness and the third thickness.     In the method of manufacturing a semiconductor device according to the item 1, the plating current density in the lower step (d2) is larger than the plating current density in the lower steps (d1) and (d3).     In the method of manufacturing a semiconductor device according to the item 1, the plating current density in the lower step (d2) is twice or more larger than the plating current density in the lower steps (d1) and (d3).     In the method for manufacturing a semiconductor device according to the item 1, the plating current density in the lower step (d2) is three times or more larger than the plating current density in the lower steps (d1) and (d3).     In the method of manufacturing a semiconductor device according to the item 1, the temperature of the wafer in the lower step (d2) is lower than the temperature of the wafer in the lower steps (d1) and (d3).     In the method of manufacturing a semiconductor device according to the item 1, the temperature of the wafer in the lower step (d2) is lower by 2 degrees Celsius or more than the temperature of the wafer in the lower steps (d1) and (d3).     In the method of manufacturing a semiconductor device according to the item 1, the temperature of the wafer in the sub-process (d2) is adjusted so that the second main surface of the wafer is cooled, so that the temperature in the sub-process (d1) and (d3) is reduced. The temperature is lower than the wafer temperature.     In the method of manufacturing a semiconductor device according to the item 1, the temperature of the wafer in the substeps (d1) and (d3) is set so that the second main surface of the wafer is heated, whereby the temperature in the substep (d2) is set. The temperature is higher than the wafer temperature. A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component by electroplating with a first plating current density;
(D2) having a second thickness greater than the first thickness by electroplating with a second plating current density higher than the first plating current density on the first plating layer; Depositing a second plating layer comprising gold as a major component;
(D3) On the second plating layer, by electroplating with a third plating current density lower than the second plating current density, the third thickness is smaller than the second thickness; Depositing a third plating layer comprising gold as a major component;     In the method of manufacturing a semiconductor device according to the item 13, the temperature of the plating solution is substantially constant in the step (d). A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component at a first wafer temperature;
(D2) On the first plating layer, gold is a major component at a second wafer temperature having a second thickness greater than the first thickness and lower than the first wafer temperature. Depositing a second plating layer;
(D3) On the second plating layer, gold is a major component at a third wafer temperature having a third thickness smaller than the second thickness and higher than the second wafer temperature. Depositing a third plating layer.     In the method for manufacturing a semiconductor device according to the item 15, the plating current density is substantially constant in the step (d).     16. In the method of manufacturing a semiconductor device according to the item 15, the upper surface of the third plating layer is not a glossy surface. A semiconductor device manufacturing method including the following steps:
(A) forming a resist film having a plurality of openings on the first main surface of the wafer;
(B) introducing the wafer having the resist film into a single wafer plating apparatus having a plating cup and a plating solution tank for supplying a plating solution to the plating cup;
(C) loading the wafer having the resist film into the plating cup in the single wafer plating apparatus so that the first main surface faces the plating tank of the plating cup;
(D) After the step (c), while the plating solution is circulated between the plating tank and the plating solution tank, gold bumps are formed by electroplating on the plurality of openings on the first main surface. Forming an electrode;
Here, the step (d) includes the following sub-steps:
(D1) depositing a first plating layer having a first thickness and containing gold as a main component at a first wafer temperature;
(D2) On the first plating layer, gold is a major component at a second wafer temperature having a second thickness greater than the first thickness and lower than the first wafer temperature. Depositing a second plating layer.     In the method of manufacturing a semiconductor device according to the item 18, the plating current density is substantially constant in the step (d).     In the method of manufacturing a semiconductor device according to the item 18, the temperature of the wafer in the lower step (d1) is higher than the temperature of the wafer in the lower step (d2) by heating the second main surface of the wafer. Is also high.

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