JP2009232296A - Amplification circuit and adjustment method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplification circuit or an adjustment method thereof for easily canceling deviation of timing mutually between an input signal applied to an amplifier and a power supply voltage. <P>SOLUTION: An amplification circuit includes: a function for applying a power supply voltage modulated on the basis of an input signal to an amplifier 22 to the relevant amplifier 22; a function for estimating an inverse distortion characteristic based on an input/output characteristic of the amplifier 22 to perform distortion compensation; and a function for adjusting mutual timing of the input signal applied to the amplifier 22 and of the power supply voltage. The amplification circuit is configured to increase an output of the amplifier 22, through the timing adjustment, from a timing non-adjusted output at a time when an adjustment signal having a peaked waveform is input to the amplifier 22 while not performing distortion compensation due to a distortion compensation part 30, so that a peak value appears, and to perform the timing adjustment so that a value, in the vicinity of the relevant peak value, corresponding to a width of the input/output characteristic (gain width or the like) in the output lower than the peak value becomes a predetermined value or less (becomes "0" ideally). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an amplifier circuit and an adjustment method thereof.

  When power is amplified using a high power amplifier (HPA), a desired output may not be obtained due to distortion of input / output characteristics. Therefore, as a distortion compensation method for compensating for such distortion, an inverse distortion characteristic opposite to the amplifier distortion characteristic is generated by digital signal processing for the input signal (gate signal) of the amplifier, and There has been proposed a technique for obtaining a desired amplifier output by performing DPD (Digital Pre-Distortion) processing added to an input (see, for example, Non-Patent Document 1).

  If you want to increase the power efficiency of the amplifier at the same time, the power supply voltage (drain signal) of the amplifier is modulated using the input signal of the amplifier, and the power consumption of the amplifier is dynamically changed according to the size of the input signal (power supply (Referred to as non-patent documents 2 and 3). In such a power supply modulation method, when the voltage of the input signal is small, the power consumption of the amplifier is suppressed, and the power efficiency is improved. In this way, a highly efficient amplification technique can be provided.

  When the power supply voltage of the amplifier is controlled together with the DPD processing as described above, the signal timing of the input signal to the amplifier and the modulated power supply voltage completely match each other (that is, the delay with respect to one of the other is Is not desirable.) For this purpose, for example, the timing of the power supply voltage can be matched by adjusting the timing of the power supply voltage so that the distortion component of the output of the amplifier is minimized (see, for example, Patent Document 1). .

Donald F. Kimball, et. Al., “High-Efficiency Envelope-Tracking W-CDMA Base-Station Amplifier Using GaN HFETs”, IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 11, November 2006. Donald F. Kimball, et al., "High-Efficiency Envelope-Tracking W-CDMA Base-Station Amplifier Using GaN HFETs", IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 11, November 2006. Feipeng Wang, et. Al., “Design of Wide-Band Envelope-Tracking Power Amplifiers for OFDM Applications”, IEEE Transactions on Microwave Theory and Techniques, Vol. 53, No. 4, April 2005. Japanese Patent No. 3898656

  However, the distortion of the amplifier under the application of the DPD is caused by the DPD compensation amount and the memory effect of the amplifier in addition to the shift of the drain voltage timing, and therefore the timing is not always the same if the distortion is minimized. Absent. If the timing is slightly shifted, the output of the amplifier cannot be maximized. In particular, the timing is completely unknown at the initial stage of starting to use the amplifier, and there is a problem of how to adjust the timing under such circumstances.

  In view of such a conventional problem, an object of the present invention is to provide an amplifier circuit or a method for adjusting the same that easily eliminates a timing shift between an input signal applied to an amplifier and a power supply voltage (drain voltage). .

An amplifier circuit according to the present invention acquires an input / output characteristic of an amplifier, a power supply modulation unit that applies the power supply voltage modulated based on an input signal to the amplifier to the amplifier, and an input / output characteristic of the amplifier. An estimator that estimates a reverse distortion characteristic that cancels the distortion characteristic obtained from the above, a distortion compensation part that performs distortion compensation by adding the reverse distortion characteristic to an input signal to the amplifier, and an input signal applied to the amplifier And a timing adjustment unit for adjusting the relative timing of the power supply voltage,
The estimation unit and the timing adjustment unit adjust the timing from an unadjusted output when a signal having a spire waveform is input to the amplifier in a state where distortion compensation by the distortion compensation unit is not performed. The output is increased to cause a peak value to appear, and the timing is adjusted so that the value corresponding to the width of the input / output characteristic in the vicinity of the peak value and lower than the peak value is equal to or less than a predetermined value. To do.

  In the amplifier circuit as described above, for example, a peak value appears from a state where the mutual timing shift between the input signal to the amplifier and the power supply voltage modulated based on the input signal is unknown, and the peak value By adjusting so that the value corresponding to the width of the input / output characteristics (for example, the gain characteristics and the phase characteristics) is within the predetermined range, the timing adjustment can be easily performed.

Further, in the amplifier circuit, it is preferable that the timing adjustment unit coarsely adjusts the timing when a peak value appears, and finely adjusts the timing when adjusting the timing to be equal to or less than the predetermined value.
In this case, it is possible to cause the peak value to appear quickly by coarse adjustment regardless of the timing deviation before adjustment, and to finally adjust the timing accurately by fine adjustment.

In the amplifier circuit, an adjustment signal generator that generates the signal having the spire waveform as a timing adjustment signal may be provided.
In this case, the amplification circuit can automatically adjust the timing by generating the signal from the adjustment signal generator.

In the amplifier circuit, it is preferable that the adjustment signal generation unit periodically generates a signal having a spire waveform.
In this case, the timing adjustment becomes easier due to the periodicity. As a signal having a spire waveform, it is preferable to generate a waveform having a high peak-to-average power ratio (PAPR) and few peaks in one cycle (1 is the best).

  On the other hand, the present invention as a method obtains a function of applying a power supply voltage modulated based on an input signal to an amplifier to the amplifier and an input / output characteristic of the amplifier, and obtains a distortion obtained from the input / output characteristic. Estimating the inverse distortion characteristics that cancel the characteristics and adding this to the input signal to the amplifier to adjust the distortion, and adjusting the relative timing of the input signal and power supply voltage applied to the amplifier And (1) a timing from an unadjusted output when a signal having a spire waveform is input to the amplifier in a state where distortion compensation by the distortion compensator is not performed. To increase the output of the amplifier to cause a peak value to appear. (2) Further, the input / output characteristics of the output near the peak value and lower than the peak value are The corresponding values to adjust the timing to be the predetermined value or less, we are characterized in.

  In the adjustment method of the amplifier circuit as described above, for example, a peak value is caused to appear from a state in which the mutual timing shift between the input signal to the amplifier and the power supply voltage modulated based on the input signal is unknown, and By adjusting the value corresponding to the width of the input / output characteristics (for example, gain characteristics and phase characteristics) in the vicinity of the peak value and lower than the peak value, the timing can be easily adjusted. .

  According to the amplifier circuit or the adjustment method of the present invention, it is possible to easily eliminate the mutual timing shift between the input signal applied to the amplifier and the power supply voltage (drain voltage). In particular, even in the initial state where the timing deviation is unknown, it is convenient in that the timing deviation can be easily eliminated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of a wireless communication system having a wireless base station 1a as a wireless communication device and terminal devices 1b, 1c, and 1d as wireless communication devices.
Each of the wireless communication devices 1a, 1b, 1c, and 1d includes a receiver 11 for receiving a wireless signal, a transmitter 12 for transmitting a wireless signal, and a processing unit 13 that processes transmission / reception signals. .

The receiver 11 receives a linear modulation signal and has a low noise amplification circuit 11a for receiving and amplifying the linear modulation signal.
The transmitter 12 transmits a linear modulation signal and includes a power amplification circuit 12a that amplifies the linear modulation signal.
Since the basic configurations of the low noise amplifier circuit 11a and the power amplifier circuit 12a are the same, the power amplifier circuit 12a will be described below as an example of the “amplifier circuit” of the present invention.

FIG. 2 is a circuit diagram showing a hardware configuration of the amplifier circuit 12a. The amplifier circuit 12a includes a digital signal processor (DSP) 21, an RF power amplifier (hereinafter simply referred to as an amplifier) 22, an envelope amplifier 23, and the like.
The amplifier 22 is for amplifying a linear modulation signal, but has an operation region having nonlinear characteristics, and a DPD (distortion compensation unit) 30 shown in FIG. 3 described later is required. In the amplifier 22, power efficiency and distortion characteristics may change due to changes in input signals and variations in amplifier characteristics.

The digital signal processing unit 21 can output a signal (baseband signal) serving as an input to the amplifier 22 and obtain an output (baseband signal) of the amplifier 22.
A DA converter (DAC) 24, a low-pass filter (LPF) 25, an up-converter 26, a band-pass filter 27, and a driver 28 are provided between the digital signal processing unit 21 and the signal input terminal of the amplifier 22. ing. A DA converter (DAC) 24, a low-pass filter 29d, and an envelope amplifier 23 are provided between the digital signal processing unit 21 and the power supply voltage input terminal of the amplifier 22.

  The digital signal that is the basis of the input signal (analog) of the envelope amplifier 23 is given as a signal based on the input signal (digital) to the amplifier 22 in the digital signal processing unit 21. Therefore, the circuit portion that applies the power supply voltage to the amplifier 22 through the DA converter 24, the low-pass filter 29d, and the envelope amplifier 23 from the digital signal processing unit 21 applies the power supply voltage that is modulated based on the input signal to the amplifier 22. A power supply modulation unit 20 applied to the amplifier 22 is configured. On the other hand, a directional coupler 29e, a down converter 29a, a low-pass filter 29b, and an AD converter (ADC) 29c are provided between the output terminal of the amplifier 22 and the digital signal processing unit 21.

  FIG. 3 is a block diagram illustrating functions related to the amplifier 22 among the internal functions of the digital signal processing unit 21. In the figure, a digital signal processing unit 21 includes a DPD (Digital Pre-Distorter) 30 (distortion compensation unit) that performs distortion compensation of a signal applied to an amplifier 22, a controller 31 to which an input / output signal of the DPD 30 is input, and a pair of A timing adjustment unit 32 including timing adjustment circuits 33 and 34 and an estimation unit 35 are provided. Further, as an input to the DPD 30, an adjustment signal generator 36 for inputting an adjustment signal in addition to the original input signal x is provided. The adjustment signal is a digital signal that is the basis of a predetermined RF signal.

  The timing adjustment circuit 33 is provided on the way from the DPD 30 to the signal input terminal of the amplifier 22, while the timing adjustment circuit 34 is provided on the way from the controller 31 to the power supply voltage input terminal (drain) of the amplifier 22. ing. Each of the timing adjustment circuits 33 and 34 can adjust the output timing by adjusting the phase between the input and output in response to an instruction from the estimation unit 35. The adjustment signal generator 36 can output an adjustment signal in response to an instruction from the estimation unit 35.

The DPD 30 performs a distortion compensation process according to the distortion characteristics of the amplifier 22 on the signal (baseband signal before distortion compensation) x to obtain a signal (baseband signal after distortion compensation) u. The estimation unit 35 can acquire the input / output characteristic of the amplifier 22 based on the output u of the DPD 30 and the output y of the amplifier 22, estimates the distortion characteristic therefrom, and reverse distortion characteristic cancels this distortion characteristic. Is estimated. That is, the estimation unit 35 estimates a reverse distortion characteristic (A ⁻¹ ) that cancels the distortion characteristic (A) obtained from the input / output characteristics of the amplifier 22. The DPD 30 performs distortion compensation by adding the inverse distortion characteristic (A ⁻¹ ) to the input signal x. By supplying the output signal u of the DPD 30 subjected to distortion compensation in advance to the amplifier 22, an output y without distortion (or little) can be obtained from the amplifier 22.

  On the other hand, as described above, the power supply modulation unit 20 changes the power supply voltage Vd applied to the amplifier 22 in accordance with the envelope (envelope) of the input signal x to the DPD 30 or the output signal u from the DPD 30. That is, if the signal x or u (envelope) is small, the power supply voltage Vd becomes small, and if the signal x or u (envelope) is large, the power supply voltage Vd becomes large, whereby the amplifier 22 based on the signal x or u. The power supply voltage Vd modulated by the input signal to is determined. Thereby, the power efficiency of the amplifier 22 can be improved.

As described above, the power supply modulation characteristic and the distortion compensation characteristic of the amplifier 22 can be controlled. Accordingly, it is possible to obtain optimum amplifier characteristics that achieve “maximum efficiency and minimum distortion” by performing adaptive control of both the power supply modulation characteristic and the distortion compensation characteristic of the amplifier 22.
Also, it is possible to control such that one of efficiency and distortion is sacrificed and the performance of the other is improved.

  Next, timing adjustment of the amplifier circuit 12a will be described. This timing adjustment is basically performed at the beginning of the use of the amplifier circuit 12a. When performing the timing adjustment, the digital signal processing unit 21 stops the distortion compensation function of the DPD 30 so that the input signal to the DPD 30 becomes the output signal u as it is. Initially, a digital signal corresponding to a predetermined RF signal as an adjustment signal is input from the adjustment signal generator 36 instead of the normal input signal x.

  FIGS. 5A, 5B and 6C are graphs showing signal timings of three patterns, and the upper part of each graph is an RF signal (DA-converted signal) used as the input signal u. The same applies to the following.), And the lower part shows the signal given as the power supply voltage Vd to the amplifier 2 based on the RF signal shown in the upper part. The characteristic of the RF signal as the adjustment signal is that the PAPR (Peak-to-Average Power Ratio) is high and the number of peaks in one period T is small (1 is the best). In other words, such an RF signal is a spire waveform having a low signal level in most time regions, a constant period T, and a high peak value.

  If it is in the state shown to (a) of FIG. 5, two signals will have shifted | deviated the timing of a spire waveform and a peak largely. (B) shows a state in which the deviation is smaller than the state of (a), but the timing is not completely matched. Furthermore, in the state of (c) in FIG. 6, the timings of the two signals are completely coincident.

  FIG. 7 is a graph showing a partially enlarged state of FIG. In this case, assuming that the times corresponding to the signal level u1 are ta and tb, the values of the power supply voltage Vd at these times are A and B in the figure, which are different from each other. Therefore, at times ta and tb, the signal level is the same (u1), but the gains are different from each other.

Input signal u for the amplifier 22, the real part at time t in 1 period T, the imaginary part, respectively a _t, When b _t, can be expressed as u = a _t + jb _t. Similarly, the output y of the amplifier 22 can be expressed as y = A _t + jB _t , where A _t and B _t are the real part and the imaginary part at time t in one cycle T, respectively. Therefore, the gain g _t at time t,
_{│ (A t + jB t)} / (a t + jb t) │∠φ t
It becomes. However, it is ^{_{φ t = tan -1 {(A}} t + jB t) / (a t + jb t)}.

  FIG. 8 is a graph of input / output characteristics (AM-AM characteristics) where the horizontal axis represents the output y of the amplifier 22 and the vertical axis represents the gain of the amplifier 22. (A), (b), and (c) are the input / output characteristics observed with respect to the RF signals of (a), (b), and (c) in FIGS. That is, when the timing is greatly shifted as shown in FIG. 5A, the input / output characteristics draw a shape as shown in FIG. 8A during one period T, and the output y is small. In the region, noise gets on and the gain width varies and widens. Further, the peak value of the output y and the peak power region in the vicinity thereof do not appear.

The peak power region is a portion extending from the state of FIG. 8A by adjusting the timing (adjustment in the timing matching direction), and is shown in FIGS. 8B and 8C. An output region with a narrow gain width that can be near the peak value y _P when there is no or little timing deviation. The peak power region expands horizontally (increases) as the above-mentioned PAPR is high, and becomes narrower as the number of RF signal peaks in one cycle is smaller.

On the other hand, in the case of (b) in FIG. 5, the deviation is smaller than in (a). For this reason, as shown in FIG. 8B, the peak value appears, but the gain width cannot be fully narrowed and is slightly swollen in a loop shape. In this case, for example, A and B in FIG. 7 correspond to A and B in FIG.
In the case of FIG. 5C, the timings of the signal u and the power supply voltage Vd coincide with each other. At this time, as shown in FIG. 8C, a thin linear peak power region appears, which is an ideal state.

  That is, in FIG. 8, when there is a timing shift, the state (a) is reached, when the shift becomes small, the state (b) is reached, and when the timing matches, the state (c) is reached. Further, when the timing starts to deviate from the state of (c), the state becomes (b), and when the timing further deviates, the state of (a) is obtained. Accordingly, it is first necessary to adjust the timing (coarse adjustment) from the state (a) to the state (b) and then further adjust the timing (fine adjustment) to the state (c).

  Such timing adjustment will be described with reference to the flowchart of FIG. The processing of this flowchart is performed by the digital signal processing unit 21 (mainly the estimation unit 35 and the timing adjustment unit 32). In the figure, the estimation unit 35 first turns off the predistortion by the DPD 30 (step S1). In addition, the estimation unit 35 sets the timing adjustment time by the timing adjustment unit 32 to 0, that is, a timing unadjusted state.

Next, the estimation unit 35 stores the maximum value of the output y as y _max (step S3), and causes the timing adjustment unit 32 to perform timing adjustment of one unit adjustment amount (step S4). This timing adjustment may be performed by either one of the timing adjustment circuits 33 and 34 or by both. Here, the timing adjustment circuit 33 is fixed in a non-adjusted state, and the adjustment is performed only by the timing adjustment circuit 34.
The adjustment is performed in one direction (arbitrary) in either the direction in which the voltage Vd is delayed or the direction in which the signal V is advanced. Then, the estimation unit 35 determines whether or not the current output y is larger than the stored y _max , that is, whether or not the output y has increased due to the timing adjustment (step S5).

Here, when the output y increases due to timing adjustment (when the adjustment direction is correct), the estimation unit 35 updates y _max (step S6), and then causes the timing adjustment unit 32 to perform timing adjustment again (step S6). Step S4). Thus, steps S4, S5 and S6 are repeated. In addition, when y is equal to or less than y _max in step S5 (“NO”), that is, when the output y does not increase due to the timing adjustment (when the adjustment direction is reversed), the estimation unit 35 performs the “ It is determined whether or not “NO” has changed from “YES” to “NO” (step S7). If the adjustment direction is reverse, this determination is “NO”, and the estimation unit 35 instructs the timing adjustment unit 32 to adjust the timing again after giving an instruction to reverse the adjustment direction by the timing adjustment unit 32 (step S8). (Step S4). Thereafter, steps S4, S5 and S6 are repeated.

In this way, when coarse timing adjustment is performed and the determination in step S7 is changed from “YES” in the previous (immediately preceding) to “NO”, that is, when the output y no longer increases, input / output It is understood that the characteristic is in the state shown in FIG. Therefore, the estimation unit 35 detects the width of the gain within the peak power range with the previous y _max as the peak value y _P (step S9).

Specifically, referring to FIG. 9 which is a partially enlarged view of the input / output characteristics shown in FIG. 8B, for example, it is smaller than the peak value y _{P of the} output y and within the range of the peak power region. output y _H (<y _P) is the two different times of the times t1, t2 leaving, these times respectively obtained gain | G _t1 │, seek | G _t2 │, the difference (│g _t2 │- | G _t1 │) to a gain width. Note that t1 and t2 can be set to t1 = t _P −Δt and t2 = t _P + Δt with respect to the time t _P when the peak value y _P of the output y occurs.

  Next, the estimation unit 35 causes the timing adjustment unit 32 to adjust the timing by one unit adjustment amount (step S10), re-detects the gain width, and determines whether the gain width has increased (step S11). ). Here, since the direction of timing adjustment is reverse when it is increasing, the adjustment direction is reversed (step S12) and the timing adjustment is performed (step S10). If the gain width has not increased (decreased or unchanged) in step S11, it is determined whether or not the gain width is within a predetermined value (step S13). Here, if it is not within the predetermined value, steps S10, S11, and S13 are repeated. As a result, when the gain width is within a predetermined value (ideally substantially 0), the input / output characteristics are in the state shown in FIG.

  As described above, according to the amplifier circuit of the present embodiment, distortion due to the DPD 30 is unknown in a state in which the timing difference between the input signal to the amplifier 22 and the power supply voltage modulated based on the input signal is unknown. The output of the amplifier 22 is increased by adjusting the timing from the unadjusted output when the signal for adjusting the spire waveform is input to the amplifier 22 without compensation, and the peak value appears. The timing of the input signal and the power supply voltage is adjusted by adjusting the value corresponding to the width of the input / output characteristic (gain characteristic) at the output lower than the peak value in the vicinity (within the peak power region) to be a predetermined value or less. be able to. Therefore, it is possible to easily eliminate the difference in timing between the input signal applied to the amplifier 22 and the power supply voltage (drain voltage). In particular, it is convenient in that the timing shift can be easily eliminated in the initial use state where the timing shift is unknown.

  Further, when the peak value appears, the timing is adjusted by coarse adjustment with a relatively large unit adjustment amount, and when the timing is adjusted to be equal to or less than the predetermined value, the unit adjustment amount is relatively small. If the timing is adjusted by fine adjustment, the peak value appears promptly by coarse adjustment regardless of the timing deviation before adjustment, and finally the timing is accurately adjusted by fine adjustment. Can do.

In the above embodiment, since the adjustment signal generator 36 for generating the adjustment signal is provided, the adjustment signal generator 36 outputs the adjustment signal of the spire waveform in the initial state of the start of use. The amplifier circuit 12a can automatically adjust the timing. Further, since the adjustment signal is periodically generated from the adjustment signal generator 36, the timing adjustment becomes easier. As the adjustment signal, a waveform having a high PAPR and few peaks in one cycle (1 is the best) is preferable.
In addition, it is also possible to supply an adjustment signal from the outside separately from the digital signal processing unit 21.

  Moreover, although the gain characteristic by AM-AM is shown as an input / output characteristic in the said embodiment, timing adjustment is similarly carried out also about the phase characteristic of AM-PM by narrowing the width | variety of the input / output characteristic in a peak power area | region. It can be carried out.

  In the above-described embodiment, the adjustment signal generator 36 that generates the adjustment signal is provided. However, the timing adjustment cannot be performed unless the adjustment signal is used. For example, since an actual communication signal has a low PAPR, many peaks appear, and is not periodic, it is difficult to say that it is suitable for timing adjustment. Adjustment is possible.

Note that when performing timing adjustment using signals that include multiple types of peaks with different peak values, it is desirable to adjust the timing at the peak with the maximum amplitude. Timing adjustment is expected. In such a case, if the value of the output y _max is known in advance, a determination step of “y _max is a predetermined value or more?” Is inserted in the middle of steps S7 to S9 in FIG. If so, the process proceeds to step S9. If NO, for example, the process may be configured to return to step S1 and start again.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined not by the above-mentioned meaning but by the scope of claims for patent, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims for patent.

It is a block diagram of a radio | wireless communications system which has a radio base station as a radio | wireless communication apparatus, and a terminal device as a radio | wireless communication apparatus. It is a circuit diagram which shows the hardware constitutions of an amplifier circuit. It is a block diagram which shows the function regarding an amplifier among the internal functions of a digital signal processing part. It is a flowchart which shows the process performed by a digital signal processing part. It is a graph which shows the signal timing of 2 patterns regarding the input signal and power supply voltage which are given to an amplifier. It is a graph which shows the signal timing of the state in which timings mutually correspond regarding the input signal and power supply voltage which are given to an amplifier. It is a graph which expands and shows the state of (b) of Drawing 5 partially. It is a graph of input / output characteristics (AM-AM characteristics) where the horizontal axis represents the output y of the amplifier and the vertical axis represents the gain of the amplifier. FIG. 9 is a partially enlarged view of the input / output characteristics shown in FIG.

Explanation of symbols

1a: radio base station, 1b, 1c, 1d: terminal device, 11: receiver, 11a: amplifier circuit, 12 transmitter, 12a: amplifier circuit, 13: processing unit, 20: power supply modulation unit, 21: digital signal processing Part 22: amplifier 23: envelope amplifier 24: DA converter 25: low pass filter 26: up converter 27: band pass filter 28: driver 29a: down converter 29b: low pass filter 29c: AD converter 29d: low-pass filter, 29e: directional coupler, 30: DPD (distortion compensation unit), 31: controller, 32: timing adjustment unit, 33, 34: timing adjustment circuit, 35: estimation unit, 36: for adjustment Signal generator

Claims (5)

An amplifier;
A power supply modulation section for applying a power supply voltage modulated based on an input signal to the amplifier to the amplifier;
An estimation unit that acquires input / output characteristics of the amplifier and estimates reverse distortion characteristics that cancel distortion characteristics obtained from the input / output characteristics;
A distortion compensation unit that performs distortion compensation by adding the inverse distortion characteristic to an input signal to the amplifier;
A timing adjustment unit that adjusts the relative timing of the input signal and the power supply voltage applied to the amplifier,
The estimation unit and the timing adjustment unit adjust the timing from an unadjusted output when a signal having a spire waveform is input to the amplifier in a state where distortion compensation by the distortion compensation unit is not performed. The output is increased to cause a peak value to appear, and the timing is adjusted so that the value corresponding to the width of the input / output characteristic in the vicinity of the peak value and lower than the peak value is equal to or less than a predetermined value. Amplifying circuit.   2. The amplifier circuit according to claim 1, wherein the timing adjustment unit roughly adjusts the timing when the peak value appears, and finely adjusts the timing when adjusting the timing to be equal to or less than the predetermined value.   The amplifier circuit according to claim 1, further comprising an adjustment signal generation unit that generates the signal having the spire waveform as a timing adjustment signal.   The amplifier circuit according to claim 3, wherein the adjustment signal generation unit periodically generates a signal having the spire waveform. A function for applying a power supply voltage modulated based on an input signal to the amplifier to the amplifier and an input / output characteristic of the amplifier, and estimating a reverse distortion characteristic that cancels the distortion characteristic obtained from the input / output characteristic. Adjustment of an amplifier circuit having a function of performing distortion compensation by adding this to an input signal to the amplifier and a function of adjusting a relative timing of an input signal and a power supply voltage applied to the amplifier A method,
In a state where distortion compensation by the distortion compensation unit is not performed, the output of the amplifier is increased by adjusting the timing from an unadjusted output when a signal having a spire waveform is input to the amplifier, and a peak value appears. Let
Furthermore, the timing adjustment is performed so that a value corresponding to the width of the input / output characteristic at an output lower than the peak value in the vicinity of the peak value is equal to or less than a predetermined value.

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