JP2009232235A - Automatic gain control circuit suitable for signal with high crest factor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic gain control circuit suitable for signal with a high crest factor, which can limit signal clipping to a proper frequency and has potential for improvement effects in an EVM value and BER owing to fast gain adjustment processing. <P>SOLUTION: The automatic gain control circuit 3, which receives a digital modulation signal 25 amplified by an amplifying circuit 2 and generates control signals 21, 23 for correcting the gain of the amplifying circuit 2 according to a signal level of the digital modulation signal 25, detects a clipping frequency of signal level of the modulation signal 25, and generates the control signals 21, 23 for correcting the gain to a larger value as the clipping frequency becomes higher. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an automatic gain control (AGC) suitable for a signal having a high crest factor such as an orthogonal frequency division multiplex (OFDM) modulation signal in which a transmission signal does not have a specific pattern signal section in a wireless communication system. Automatic Gain Control) circuit.

  FIG. 11 is a block diagram illustrating an example of a wireless system having a conventional automatic gain control function. This conventional wireless system includes an analog circuit 100 that receives a wireless signal from an antenna and performs analog signal processing, and a digital signal processing unit 200 that performs digital signal processing of the signal from the analog circuit 100. The analog circuit 100 is a single superheterodyne amplifier circuit, a high-frequency amplifier circuit 101 that amplifies a radio signal, a mixer 102 that converts a high-frequency signal output from the high-frequency amplifier circuit 101 to a low-frequency signal, and an intermediate frequency A band pass filter 103 that extracts a signal, an intermediate frequency amplifier circuit 104 that amplifies the intermediate frequency signal, and an AD converter 105 that performs analog-digital (AD) conversion of the intermediate frequency signal are provided. The high frequency amplifier circuit 101 and the intermediate frequency amplifier circuit 104 are variable amplifier circuits whose gain (gain) can be adjusted by an external control signal.

  On the other hand, the digital signal processing unit 200 demodulates the digital signal from the AD converter 105 to extract data, and performs AGC control according to fluctuations in the level of the digital signal from the AD converter 105. An AGC function unit 201 that generates a signal, outputs the signal to the high frequency amplifier circuit 101 and the intermediate frequency amplifier circuit 104, and adjusts the amplification factor of the high frequency amplifier circuit 101 and the intermediate frequency amplifier circuit 104 is provided.

  In the power control operation using the automatic gain control function shown in FIG. 11, the amplification factors of the high frequency amplifier circuit 101 and the intermediate frequency amplifier circuit 104 are periodically adjusted according to the fluctuation of the reception level input to the analog circuit. Thus, the output level of the AD converter 105 is controlled so as to be always the optimum level for the digital signal processing unit 200. An example is shown in Japanese Patent Laid-Open No. 2002-290178 (Patent Document 1).

In particular, in this power control operation, the effective value energy of the received signal observed at a certain time interval is obtained, the effective value energy is compared with the desired reference effective value energy, and the effective value energy is equal to the reference target value. Thus, the gains of the high frequency amplifier circuit 101 and the intermediate frequency amplifier circuit 104 are adjusted.
Japanese Patent Laid-Open No. 2002-290178

  On the other hand, recent wireless systems employ more complex modulation schemes to improve data rates. In particular, it has been found that the OFDM modulation signal has a higher crest factor than signals of other modulation schemes. FIG. 12 is a graph showing an example of a complementary cumulative distribution function (CCDF) of an OFDM signal based on the wireless device 802.11G.

  In the conventional power control, the signal is integrated at regular time intervals, and the gain of the variable amplifier circuit is adjusted based on the processing result. In this method, in the case of a signal having a high crest factor as shown in FIG. 12, a large amount of distortion occurs in the AD conversion output signal. In the case of the OFDM modulation scheme, the frequency of signal distortion increases in such a power control scheme as the primary modulation of the subcarrier becomes multilevel.

  In a conventional power control method, as a method of suppressing the frequency of signal distortion, there is a method of reducing a reference target value appropriately set in this power control method. However, if the setting is reduced, many signals that are not quantized as AD conversion output data are generated.

  In view of the above, an object of the present invention is to provide an automatic gain control circuit capable of performing appropriate AGC control and suppressing signal clipping to an appropriate frequency even for a signal having a high crest factor such as an OFDM modulation signal. To do.

  The automatic gain control circuit according to the present invention receives the digital modulation signal amplified by the amplification circuit, generates a control signal for correcting the amplification factor of the amplification circuit according to the signal level of the digital modulation signal, It is characterized by detecting the clipping frequency of the signal level of the modulation signal and generating a control signal that corrects the amplification factor higher as the clipping frequency is higher or the cropping frequency is lower.

  With this configuration, even with a signal with a high crest factor such as an OFDM modulated signal, appropriate AGC control can be performed and signal clipping can be suppressed to an appropriate frequency. Therefore, demodulation BER (Bit Error Rate) The effect of suppressing the amount of deterioration of characteristics can be expected.

  According to another aspect of the present invention, the automatic gain control circuit receives the digital modulation signal amplified by the amplification circuit, detects whether the signal level of the modulation signal exceeds a reference value, and detects the detection. A comparator that outputs a value indicating the result, an accumulation circuit that discretely accumulates the output of the comparator, and a value that indicates the accumulation result, and amplification of the modulation signal by the amplifier circuit based on the output of the accumulation circuit Control signal generation circuit for generating a control signal for correcting the rate, and when the output of the accumulation circuit is discretely accumulated, the signal level exceeding the reference value and the signal level not exceeding the reference value Therefore, the ratio between the weight given to the signal level exceeding the reference value and the weight given to the signal level not exceeding the reference value is greater than the ratio of the signal levels of both. And said that no.

  Even with such a configuration, even with a signal having a high crest factor such as an OFDM modulated signal, it is possible to perform appropriate AGC control and suppress signal clipping to an appropriate frequency. The effect of suppressing the amount of deterioration can be expected.

  According to still another aspect of the present invention, the automatic gain control circuit includes a plurality of first comparators, and each of the plurality of first comparators receives the digital modulation signal amplified by the amplifier circuit. The first reference value is compared with the modulation signal, and it is detected whether the signal level of the modulation signal exceeds the first reference value, and a value indicating the detection result is output. The first reference value is A different value is set for each of the plurality of first comparators, and the automatic gain control circuit further adds the outputs from the plurality of first comparators to each other for a predetermined period, and outputs the respective cumulative addition results. And a plurality of second comparators, each of the plurality of second comparators receiving a cumulative addition result from the peak detection occurrence number adder unit, The reference value is compared with this cumulative addition result, and the cumulative addition result It is detected whether the signal level exceeds the second reference value, and a value indicating the sum of the detection results is output. The second reference value is set to a different value for each of the plurality of second comparators. The control signal for correcting the amplification factor of the modulation signal by the amplifier circuit is generated based on the output from the second comparator.

  With such a configuration, as a means for confirming the magnitude of the modulation signal, it has a plurality of threshold values, and the AGC control operation can be appropriately and quickly performed by the threshold value and the determination method. EVM (Error Vector Magnitude) value and BER improvement effect can be expected from quick gain adjustment processing.

  According to the present invention, even with a signal having a high crest factor such as an OFDM modulated signal, appropriate AGC control can be performed, signal clipping can be suppressed to an appropriate frequency, and adjusted to a desired signal level. Therefore, the amount of deterioration of the demodulation BER characteristic is suppressed.

  In addition, according to the present invention, as a means for confirming the magnitude of the modulation signal, it has a plurality of threshold values, and the AGC control operation can be appropriately performed earlier by the threshold value and the determination method. Then, the EVM value and the BER are improved from the quick gain adjustment process.

  Furthermore, according to the present invention, even in a configuration in which a noise component unique to an analog circuit is inserted, and even when the reception level input to the analog circuit is reduced, the correction function of the AGC control signal is used. The gain can be adjusted to a desired reception level, and deterioration of the BER characteristic of demodulation can be suppressed.

  Next, an embodiment of an AGC control unit for OFDM modulation system according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following, illustration and description of parts not directly related to the understanding of the present invention are omitted.

  FIG. 1 is a block diagram of a wireless system using an OFDM modulation scheme AGC control unit according to an embodiment of the present invention. Here, a multi-level quadrature amplitude modulation (QAM) method is used as OFDM symbol mapping, which can be applied to a wireless LAN (local area network), mobile communication, and the like. In principle, non-wireless applications such as power line communications (PLC) are also possible.

  As shown in FIG. 1, the radio system of this embodiment as a whole receives an analog circuit 2 that receives a radio signal from an antenna 1 and performs analog signal processing, and a digital signal that performs digital signal processing of the signal from the analog circuit 2 And processing unit 3. The analog circuit 2 is a single superheterodyne amplifier circuit, a high frequency amplifier circuit (RF AGC) 4 that amplifies a radio signal, and a mixer that converts a high frequency signal output from the high frequency amplifier circuit 4 into a low frequency signal ( MIXER) 5, bandpass filter (BPF) 6 that extracts the intermediate frequency signal, intermediate frequency amplifier circuit (IF AGC) 7 that amplifies the intermediate frequency signal, and AD converter (ADC) 8 that performs AD conversion of the intermediate frequency signal These are connected as shown in the figure.

  The high frequency amplifier circuit 4 and the intermediate frequency amplifier circuit 7 are variable amplifier circuits whose gain (gain) can be adjusted by external control signals 21 and 23, respectively. For example, the gain of the intermediate frequency amplifier circuit 7 increases as the voltage of the control signal 23 increases, and decreases as the voltage decreases. If the voltage of the control signal 23 is constant, amplification is continued with a constant gain.

  On the other hand, the digital signal processing unit 3 demodulates the digital signal 25 from the AD converter 8 to extract data, and generates AGC control signals 21 and 23 according to the level fluctuation of the digital signal 25 In addition, an AGC control unit 10 is provided for outputting to the high frequency amplifier circuit 4 and the intermediate frequency amplifier circuit 7 and adjusting the amplification factor of both.

  2A and 2B are block diagrams of the OFDM modulation scheme AGC control unit 10 according to the embodiment of the present invention. Referring to these figures, the AGC control unit 10 for OFDM modulation system includes a scalar conversion circuit 11, a first comparator unit 12, a peak detection occurrence number adder unit 13, a second comparator unit 14, and an AGC. The correction processing unit 15 is included, and these are connected as illustrated.

  The scalar conversion circuit 11 receives the digital output X of the AD converter 8 and outputs the absolute value | X |. In the present embodiment, the first comparator unit 12 includes four comparators 12a, 12b, 12c, and 12d. The output | X | from the scalar conversion circuit 11 is the four comparators 12a, 12b, 12c, and 12d. Is input to each of the. Further, reference values (integer values in this embodiment) A1, B1, C1, and D1 stored in an external register (not shown) are given to the four comparators 12a, 12b, 12c, and 12d, respectively. . These reference values A1, B1, C1, and D1 are part of important parameters that determine the characteristics of the AGC control unit 10, and are appropriately set according to the required characteristics.

The comparator 12a of the first comparator unit 12 compares the absolute value | X | with the reference value A1, and outputs a logical value “1” as the value a if the absolute value | X | . If the absolute value | X | is less than the reference value A1, a logical value “0” is output as the value a. The comparator 12b compares the absolute value | X | and the reference value B1, and outputs a logical value “1” as the value b if the absolute value | X | is equal to or greater than the reference value B1. If the absolute value | X | is less than the reference value B1, a logical value “0” is output as the value b. The comparator 12c compares the absolute value | X | with the reference value C1, and outputs a logical value “1” as the value c if the absolute value | X | If the absolute value | X | is less than the reference value C1, the logical value “0” is output as the value c. The comparator 12d compares the absolute value | X | with the reference value D1, and outputs a logical value “1” as the value d if the absolute value | X | If the absolute value | X | is less than the reference value D1, a logical value “0” is output as the value d. If the above processing is expressed in C language, the absolute value | X |
if (A1 <= x) a = 1; else a = 0;
if (B1 <= x) b = 1; else b = 0;
if (C1 <= x) c = 1; else c = 0;
if (D1 <= x) d = 1; else d = 0;

FIG. 3 is a diagram showing an example of the operation of the first comparator unit 12. Here, the bit width of the digital signal output from the AD converter 8 is 6 bits, and the reference values A1, B1, C1, and D1 are set to the values “30”, “26”, “18”, and “10”, respectively. . Since the absolute value | X | is processed, the maximum value is “32”. As will be described later, sampling is performed in synchronization with the clock CLK. Reflecting that the values of the reference values A1, B1, C1 and D1 are not equally spaced, the input pattern drawn by the arrows and the output values “0,” of the four comparators 12a, 12b, 12c and 12d There is a difference in the pattern of “1”. That is, AGC control can be adjusted by adjusting the values of the reference values A1, B1, C1, and D1. For example,
(A1-B1) ≥ (B1-C1) ≥ (C1-D1) ≥ D1 and (A1-B1)> D1
And monotonically increasing toward the maximum value. In this example, by setting A1 = 30 and B1 = 26, the higher the clipping frequency, the larger the number of samples. In other words, the larger the crest factor, the greater the number of samples.

  In this embodiment, the peak detection occurrence number adder unit 13 includes four adders 132a, 132b, 132c, and 132d provided with registers 131a, 131b, 131c, and 131d, respectively. For example, the adder 132a receives the output a of the comparator 12a of the first comparator unit 12, and performs cumulative addition to the register 131a. That is, every time the clock CLK rises, the value add_a of the register 131a and the output a of the comparator 12a are added to overwrite the value add_a of the register 131a. When a control signal en1 described later becomes 1, the value add_a of the register 131a is reset to 0 together with the control signal en1 at the rising edge of the clock CLK.

  Further, the value add_a of the register 131a is output to the adder 132a and also to the second comparator unit 14 at the next stage. The remaining adders 132b, 132c, and 132d perform the same operation together with the corresponding registers 131b, 131c, and 131d. Further, the value add_a of the register 131a is output to the adder 132a and is also output to the second comparator unit 14 at the next stage. The remaining adders 132b, 132c, and 132d perform the same operation on the outputs of the comparators 12a, 12b, 12c, and 12d of the first comparator unit 12 together with the corresponding registers 131b, 131c, and 131d.

  Therefore, the outputs of the comparators 12a, 12b, 12c and 12d of the first comparator section 12 are cumulatively added in the cycle of the control signal en1. FIG. 4 is a flowchart for explaining the operation of the peak detection occurrence number adder unit 13, and an algorithm for generating the control signal en1 is also shown. First, in step S41, the counter variable counter1 and the values add_a, add_b, add_c, and add_d of the registers 131a, 131b, 131c, and 131d are reset to “0”. Next, in step S42, the variable counter1 is incremented by “1” at the rising edge of the clock CLK. Next, in step S43, a constant counter_value1 for determining the cycle of the control signal en1 is compared with the counter variable counter1, and if they are not equal, in step S44, the comparators 12a, 12b, 12c, 12d of the first comparator unit 12 are compared. Is added to the values add_a, add_b, add_c, and add_d of the registers 131a, 131b, 131c, and 131d (addition substitution), and the process returns to step S42. If the constant counter_value1 is equal to the counter variable counter1 in step S43, the control signal en1 is set to 1 for one clock CLK and the process returns to step S41.

  The second comparator unit 14 includes four comparators 141a, 141b, 141c, and 141d, and outputs add_a, add_b, add_c, and add_d from the registers 131a, 131b, 131c, and 131d of the peak detection occurrence number adder unit 13 are Are input to each of the four comparators 141a, 141b, 141, and 141d. Further, reference values A2, B2, C2 and D2 stored in the external register are given to each of these four comparators 141a, 141b, 141c and 141d. These reference values A2, B2, C2, and D2 can be set as appropriate.

The comparator 141a compares the output add_a with the reference value A2. If the output add_a is equal to or greater than the reference value A1, the comparator 141a outputs a logical value “−1” as the value a2. If the output add_a is less than the reference value A2, the logical value “0” is output as the value a2. The comparator 141b compares the output add_b with the reference value B2, and outputs “−1” as the value b2 if the output add_b is equal to or greater than the reference value B2. If the output add_b is less than the reference value B2, 0 is output as the value b2. The comparator 141c compares the output add_c with the reference value C2, and outputs “1” as the value c2 if the output add_c is equal to or less than the reference value C2. If the output add_c is less than the reference value C2, 0 is output as the value c2. The comparator 141d compares the output add_d with the reference value D2, and outputs “1” as the value d2 if the output add_d is equal to or less than the reference value D2. If the output add_a is less than the reference value D2, “0” is output as the value d2. The above processing is expressed in C language as follows.
if (A2 <= add_a) a2 = -1; else a2 = 0;
if (B2 <= add_b) b2 = -1; else b2 = 0;
if (C2> = add_c) c2 = 1; else c2 = 0;
if (D2> = add_d) d2 = 1; else d2 = 0;

  The second comparator section 14 further includes a four-input X adder 142. The outputs add_a, add_b, add_c and add_d of the comparators 141a, 141b, 141c and 141d are added by the X adder 142 and the sum X is obtained. Output.

  Further, a Y adder 144 (FIG. 2B) with a register 143 is connected to the X adder 142. The register 143 and the Y adder 144 are also components of the second comparator unit 14. The Y adder 144 receives the output of the X adder 142 and calculates the sum with the value of the register 143. When the control signal en1 becomes “1”, the output of the Y adder 144 is stored in the register 143 at the rising edge of the clock CLK. Further, when a control signal en2 described later becomes “1”, the value of the register 143 is reset to “0”. The value Yout of the register 143 is output to the Y adder 144 and also to the AGC correction processing unit 15 at the next stage. Therefore, the output X of the X adder 142 is cumulatively added in the cycle of the control signal en2.

  As apparent from the above description, the outputs add_a, add_b, add_c, and add_d from the registers 131a, 131b, 131c, and 131d of the peak detection occurrence number adder unit 13 contribute to the output X of the X adder 142. Adjustment can be made by appropriately setting the reference values A2, B2, C2, and D2. That is, it is a parameter that improves the relationship between the crest factor and the AGC control signal described later.

  FIG. 5 is a flowchart for explaining the operation of the Y adder 144 with the register 143, and also shows an algorithm for generating the control signal en2. First, in step S51, the counter variable counter1 and the counter variable counter2 are reset to “0”. Next, in step S52, the counter variable counter1 is incremented by “1” at the rising edge of the clock CLK. Next, in step S53, a constant counter_value1 for determining the cycle of the control signal en1 is compared with the counter variable counter1, and if the two are not equal, the process returns to step S52. If the constant counter_value1 is equal to the counter variable counter1 in step S53, the control signal en1 is set to “1” for one clock CLK, and the process proceeds to step S54. In step S54, the addition X of the output X of the X adder 142 is added to the value Yout stored in the register 143. Next, in step S55, the counter variable counter2 is incremented by “1”. In step S56, the counter variable counter1 is reset to “0”. Next, in step S57, the constant counter_value2 for determining the cycle of the control signal en2 is compared with the counter variable counter2, and if the two are not equal, the process returns to step S52. If the constant counter_value2 is equal to the counter variable counter2 in step S57, the control signal en2 is set to “1” for one clock CLK and the process returns to step S51. The flowcharts of FIGS. 4 and 5 partially include the same processing. However, in this case, it can be easily understood that they can be implemented without any contradiction.

  FIG. 6 is a block diagram showing hardware for mounting the counter variable counter1 and the counter variable counter2. Here, the counter C1 compares the constant counter_value1 with the internal count value counter1, and outputs a control signal en1 when they match. Similarly, the counter C2 compares the constant counter_value2 with the internal count value counter2, and outputs a control signal en2 when they match. The counter C1 counts the clock CLK, and the counter C2 counts the control signal en1.

Referring back to FIG. 2B, the AGC correction processing unit 15 includes a third comparator unit 151 and a Z adder 152. The third comparator unit 151 compares the positive reference value A3 and the negative reference value B3 stored in an external register (not shown) with the output Yout of the second comparator unit 14, and according to the comparison result Output Y1out. Specifically, first, the output Yout is compared with the reference value A3, and if the output Yout is equal to or greater than the reference value A3, the value “2” is output as Y1out. If the output Yout is smaller than the reference value A3 and larger than “0”, the value “1” is output as Y1out. Further, the output Yout is compared with the reference value B3, and if the output Yout is equal to or less than the reference value B3, “−2” is output as Y1out. If the output Yout is larger than the reference value B3 and smaller than “0”, the value “−1” is output as Y1out. If none of the above applies, that is, if the output Yout is “0”, the value “0” is output as Y1out. The above processing is expressed in C language as follows.
if (Yout> = A3) Y1out = 2;
else if ((A3> Yout) &&(Yout> 0)) Y1out = 1;
else if (Yout <= B3) Y1out = -2;
else if ((0> Yout) &&(Yout> B3)) Y1out = -1;
else Y1out = 0;

  The third comparison unit 151 of the AGC correction processing unit 15 operates as shown in FIG. The third comparison unit 151 always compares the reference value A3 and the reference value B3, which are preset fixed parameter threshold values, with the output Yout, and outputs Y1out at a time interval defined by the value counter_value1 according to the result. .

  The Z adder 152 includes a register therein, receives the output Y1out of the third comparator unit 151 and a predetermined constant STEP_VALUE, and performs addition substitution for the value Z of the internal register (not shown). More specifically, the value Z of the internal register is added to the product of the output Y1out of the third comparator unit 151 and a predetermined constant STEP_VALUE, and the result is written back to the internal register. This addition result is written back by storing the output of the adder circuit in the Z adder 152 in the internal register at the rising edge of the clock CLK when a control signal en2 described later becomes “1”. Done. The value Z that is the output of the Z adder 152 is fed back as an AGC control signal 21 or 23 that adjusts the amplification factor of the high-frequency amplifier circuit 4 or the intermediate frequency amplifier circuit 7, respectively. As a feedback method, it is possible to feed back only to the intermediate frequency amplifier circuit 7, or the AGC control signals 21 and 23 may be appropriately distributed to the high frequency amplifier circuit 4 and the intermediate frequency amplifier circuit 7.

  FIG. 8 is a diagram for explaining the characteristics of the operation of the OFDM modulation scheme AGC control unit 1 according to the above-described embodiment of the present invention. The vertical axis shows the distribution of the absolute value | X | of the digital output 25 of the AD converter 8 as complementary cumulative probability distribution characteristics, and the horizontal axis shows the above-mentioned reference values A1, B1, C1 expressed in terms of the crest factor [dB]. And D1 are shown. Here, since the digital output 25 of the AD converter 8 is small with respect to an appropriate level at the time point A, the absolute value display of the complementary cumulative probability distribution characteristic is shifted to the left side. The output Y1out of the three comparison unit 151 becomes positive. Then, when the control signal en2 becomes “1”, the Y1out value is added to the adder Z, the gain is increased, and the reception unit AGC control of the signal having a high crest factor such as the OFDM modulation signal is performed. If the AGC gain adjustment is performed by integrating the difference between the input level and the reference level and adjusting the AGC correction data value by the integral value at a certain timing as in the past, the signal is clipped, The EVM (Error Vector Magnitude) value of the signal becomes worse, and the bit error rate (BER) of the demodulation also deteriorates accordingly. In this embodiment, instead of confirming only the amount of change of energy and performing the AGC control operation only with the amount of change as in the prior art, the size of the data is set for each sample value of the output data 25 of the AD converter 8. It is configured to check, estimate the frequency of clipping of the signal, and perform the AGC control operation according to the frequency. Therefore, signal clipping can be suppressed to an appropriate frequency. Therefore, an effect of suppressing the deterioration amount of the demodulation BER characteristic can be expected. In addition, this embodiment has a plurality of threshold values as means for confirming the size of the data, and the AGC control operation can be appropriately and quickly performed by using the threshold values and the determination method. The EVM value can be improved and the BER improvement effect can be expected from the quick gain adjustment process.

  FIGS. 9A, 9B and 9C are block diagrams of the AGC control unit 1 for OFDM modulation system according to another embodiment of the present invention. The functional blocks other than the digital filter 27 that performs the filtering process of the digital output 25 of the AD converter 8, the first AGC correction processing unit 28, and the second AGC correction processing unit 29 are substantially the same as the corresponding blocks in the previous embodiment. Since the processing is performed, the same reference numerals are used and the description thereof is omitted as appropriate. The third comparison unit 281 of the first AGC correction processing unit 28 performs the same processing as the third comparison unit 151 of the corresponding AGC correction processing unit 15 of the previous embodiment. The digital filter 27 is a band-pass filter, and is provided for the purpose of removing high-frequency noise components contained in the digital output 25 of the AD converter 8.

  Referring to FIG. 9C, the second AGC correction processing unit 29 includes two adders 291 and 292 and one register 293. The adder 291 calculates a difference between the absolute value | X | of the digital output 25 of the AD converter 8 and a predetermined comparison value Ref_Level. The adder 292 adds the output of the adder 291 and the value of the register 293. The register 293 takes in the output of the adder 292 in synchronization with the clock CLK. That is, the difference between the absolute value | X | and the predetermined comparison value Ref_Level is cumulatively added to the register 293. The value add_n_out of the register 293 is output to the Z adder 282 of the first AGC correction processing unit 28. This value add_n_out is a value obtained by cumulatively integrating the difference between the absolute value | X | and the comparison value Ref_Level.

  The Z adder 282 of the first AGC correction processing unit 28 also includes a register therein, and the output Y1out, predetermined constants STEP_VALUE, LIMIT_VALUE, and ADJ_VALUE of the third comparator unit 281 are input to the Z adder 282. As in the previous embodiment, the Z adder 282 adds the product of the output Y1out of the third comparator unit 281 and a predetermined constant STEP_VALUE to the value Z1 of the internal register. If the addition result is smaller than the constant LIMIT_VALUE, it is stored as it is in the internal register as the value Z1, and fed back as AGC control signals 21 and 23 for adjusting the amplification factors of the high frequency amplification circuit 4 and the intermediate frequency amplification circuit 7, respectively.

  When the above-described addition result Z1 in the Z adder 282 is larger than the constant LIMIT_VALUE, a constant ADJ_VALUE is further added to this addition result and added. When the addition result is smaller than the value add_n_out of the register 293 of the second AGC correction processing unit 29, it is fed back as AGC control signals 21 and 23 for adjusting the amplification factors of the high frequency amplifier circuit 4 and the intermediate frequency amplifier circuit 7, respectively.

  If the above-described addition result is larger than the value add_n_out of the register 293 of the second AGC correction processing unit 29, the AGC control for adjusting the amplification factor of the high-frequency amplifier circuit 4 or the intermediate frequency amplifier circuit 7 with the value add_n_out instead of the addition result Feedback as a signal.

  FIG. 10 is a diagram for explaining the operation of the OFDM modulation scheme AGC control unit according to the present embodiment. In this example, the constant LIMIT_VALUE is “700” and ADJ_VALUE is “50”. Here, when the value add_n_out is “700” and the register value Z1 of the Z adder 282 is “600” smaller than the constant LIMIT_VALUE, the register value Z1 is directly output from the Z adder 282, and the high-frequency amplifier circuit 4 Or an AGC control signal for adjusting the amplification factor of the intermediate frequency amplifier circuit 7. When the value add_n_out is 900 and the register value Z1 is 800 larger than the constant LIMIT_VALUE, 50 of the constant ADJ_VALUE is added. Since the addition result is “850” and the value add_n_out of the register 293 of the second AGC correction processing unit 29 is “900”, the addition result value “850” is output from the Z adder 282.

  As in the above-described embodiment, in the mechanism for adjusting the amplification factor of the analog circuit 4 in the first stage by looking at the frequency with which the output signal 25 of the AD converter 8 is clipped within a certain time interval, for example, the IF of FIG. When a specific noise component, especially a specific frequency component such as a clock CLK, is inserted into the AGC control line 23, RF AGC control line 21, or signal line of the analog circuit, AGC control includes the noise. And gain adjustment. In this case, if the reception level input to the analog circuit is sufficiently large with respect to the above-described noise component, the demodulation is not significantly affected. However, when the reception level input to the analog circuit decreases and the noise component reaches a level that affects demodulation, the processing method of the previous embodiment may not be sufficient.

  However, in the mechanism of the present embodiment, the above-described AGC control signal 21 and the above-described AGC control signal 21 and the configuration in which a noise component specific to the analog circuit is inserted, and even when the reception level input to the analog circuit decreases. With the correction function of 23, the gain can be adjusted to a desired reception level, and the effect of suppressing the deterioration of the demodulation BER characteristic can be expected.

  Here, the case where the power control is positive is described. In the case of the negative polarity, the operation is reversed, and when the addition result falls below the negative value add_n_out, the negative value add_n_out is fed back as the AGC control signal.

  The present invention is not limited to the embodiment described above, and can be implemented with various modifications within the technical scope thereof. For example, the embodiments described in FIGS. 9A, 9B, and 9C are particularly effective when a signal that causes clipping of colored noise in a fixed manner is input to the automatic gain control circuit. That is, as a state where the colored noise appears as an influence, there are times when the reception input level is small. Conversely, when the reception input is large, the characteristics may deteriorate. Therefore, when the reception input is large, the operation is performed as in the embodiment described in FIGS. 2A and 2B. When the reception input is small, the operation is performed as in the embodiment described in FIGS. 9A, 9B, and 9C. There is also a method. In this case, it is effective for actual application if the threshold value of the reception input for switching is made variable.

1 is a block diagram of a wireless system using AGC control for an OFDM modulation scheme according to an embodiment of the present invention. FIG. FIG. 2 is a functional block diagram illustrating a partial configuration example of an OFDM modulation scheme AGC control unit in the embodiment illustrated in FIG. 1. It is a functional block diagram which shows the structural example of the remaining part of the AGC control part in the Example. It is a diagram which shows an example of operation | movement of the 1st comparator part in the Example. It is a flowchart explaining operation | movement of the peak detection generation frequency adder part in the Example, The algorithm which produces | generates the control signal en1 is also shown. It is a flowchart explaining operation | movement of the Y adder with the register | resistor in the Example, The algorithm which produces | generates the control signal en2 is also shown. It is a block diagram which shows the example of the hardware which mounts the counter variable in the Example. It is a figure for demonstrating operation | movement of the 3rd comparison part of the AGC correction process part in the Example. It is a figure for demonstrating the characteristic of operation | movement of the AGC control part for OFDM modulation systems by the Example. It is a functional block diagram which shows a part of AGC control part for OFDM modulation systems by the other Example of this invention. It is a functional block diagram which shows another part of AGC control part for OFDM modulation systems by the Example. It is a functional block diagram which shows the remaining part of the AGC control part for OFDM modulation systems by the Example. It is a figure explaining operation | movement of the AGC control part for OFDM modulation systems by the Example. It is a functional block diagram which shows an example of the radio | wireless system provided with the conventional automatic gain control function. It is a graph which shows an example of the complementary cumulative probability distribution characteristic of the OFDM signal of the radio equipment 802.11G.

Explanation of symbols

1 Antenna
2 Analog circuit
3 Digital signal processor
4 High frequency amplifier circuit
5 Mixer
6 Bandpass filter
7 Intermediate frequency amplifier
8 AD converter
9 Demodulation processor
10 Control unit
11 Scalar conversion circuit
12 First comparator section
12a, 12b, 12c, 12d comparator
13 Peak detection frequency adder
14 Second comparator section
15 AGC correction processing section
17 Intermediate frequency amplifier
27 Digital filter
28 First AGC correction processor
29 Second AGC correction processor
100 analog circuit
101 high frequency amplifier circuit
104 Intermediate frequency amplifier
105 AD Converter
131a, 131b, 131c, 131d registers
132a, 132b, 132c, 132d Adder
141a, 141b, 141c, 141d comparator
142 X adder
143 registers
144 Y adder
151 Third comparator
152 Adder
200 Digital signal processor
201 AGC function
281 Comparator
282 Z adder
291 Adder
291 and 292 adders
293 registers

Claims (13)

  An automatic gain control circuit which receives a digital modulation signal amplified by an amplification circuit and generates a control signal for correcting an amplification factor of the amplification circuit according to a signal level of the digital modulation signal, An automatic gain control circuit for detecting a clipping frequency of a signal level of a signal and generating a control signal for correcting the amplification factor higher as the clipping frequency is higher. A comparator that receives the digital modulation signal amplified by the amplifier circuit, detects whether the signal level of the modulation signal exceeds a reference value, and outputs a value indicating the detection result;
An accumulation circuit for discretely accumulating the output of the comparator and outputting a value indicating the accumulation result;
A control signal generation circuit that generates a control signal for correcting an amplification factor of the modulation signal by the amplification circuit based on an output of the accumulation circuit;
When discretely accumulating the output of the accumulator circuit, a substantially different weight is given to a signal level that exceeds the reference value and a signal level that does not exceed the reference value. An automatic gain control circuit, wherein a ratio of a weight given to a signal level exceeding and a weight given to a signal level not exceeding the reference value is larger than a ratio of both signal levels. The digital modulation signal amplified by the amplifier circuit is received, the first reference value is compared with the modulation signal, and it is detected whether or not the signal level of the modulation signal exceeds the first reference value. Including a plurality of first comparators for outputting a value indicating the result, wherein the first reference value is set to a different value for each of the plurality of first comparators;
A peak detection occurrence number adder unit that cumulatively adds the outputs from the plurality of first comparators to each other for a predetermined period and outputs the respective cumulative addition results;
The cumulative addition result from the peak detection occurrence number adder unit is received, the second reference value is compared with the cumulative addition result, and it is determined whether or not the signal level of the cumulative addition result exceeds the second reference value. A plurality of second comparators that detect and output a value indicating the sum of the detection results, and the second reference value is set to a different value for each of the plurality of second comparators,
An automatic gain control circuit for generating a control signal for correcting an amplification factor of the modulation signal by the amplifier circuit based on an output from a second comparator.   4. The automatic gain control circuit according to claim 3, wherein the digital modulation signal is a modulation signal having a high crest factor.   4. The automatic gain control circuit according to claim 3, wherein the digital modulation signal is a signal obtained by amplifying a radio signal.   4. The automatic gain control circuit according to claim 3, wherein the circuit further includes a circuit for performing a scalar conversion of the digital modulation signal, and the first comparator processes the modulation signal from the scalar conversion circuit. An automatic gain control circuit.   7. The automatic gain control circuit according to claim 6, further comprising a circuit that outputs a value obtained by cumulatively integrating a difference between an output from the scalar conversion circuit and a predetermined comparison level, and is positive or negative. An automatic gain control circuit for generating the control signal when the control signal exceeds the integral value in a direction.   7. The automatic gain control circuit according to claim 6, wherein the circuit further includes a digital filter that removes a high-frequency noise component contained in the modulation signal, and the scalar conversion circuit processes the modulation signal from the digital filter. An automatic gain control circuit. The automatic gain control circuit of claim 3, wherein the circuit further comprises:
A first adder for cumulatively adding the output from the second comparator for a predetermined period;
A third comparator that compares the cumulative addition result output from the first adder with a plurality of third reference values and outputs a value corresponding to the comparison result;
An automatic gain control circuit that outputs the control signal based on an output from a third comparator.   10. The automatic gain control circuit according to claim 9, wherein the circuit further includes a second adder, and the second adder circuit receives an output from the first adder, and outputs the output and a predetermined constant. An automatic gain control circuit that calculates a product and updates the control signal by adding the product to a current control signal at a predetermined interval.   4. The automatic gain control circuit according to claim 3, wherein the second adder performs a predetermined addition to the control signal when the control signal exceeds a predetermined level as a result of the cumulative addition. Automatic gain control circuit.   12. The automatic gain control circuit according to claim 11, wherein when the reception input is larger than a predetermined threshold value, the control signal is subjected to a predetermined addition.   13. The automatic gain control circuit according to claim 12, wherein the predetermined threshold value is variable.

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